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Toshiba 15nm MLC datasheet.pdf
1. INTRODUCTION
1.1. General Description
1.2. Definitions and Abbreviations
1.3. Features
1.4. Diagram Legend
2. PHYSICAL INTERFACE
2.1. Pin Descriptions
2.2. PIN ASSIGNMENT (TOP VIEW)
2.3. BLOCK DIAGRAM
2.4. Independent Data Buses
2.5. Absolute Maximum Rating
2.6. Operating Temperature Condition
2.7. Recommended Operating Conditions
2.8. Valid Blocks
2.9. AC Overshoot/Undershoot Requirements
2.10. DC Operating Characteristics
2.11. Differential Input AC Characteristics
2.12. Input/Output Capacitance
2.13. DQ Driver Strength
2.14. Operating condition on transfer rate
2.15. Input/Output Slew rate
2.16. High Speed Toggle DDR with ODT
2.16.1. ODT (On die termination)
2.16.2. ODT setting
2.16.3. ODT behavior during Read operation
2.16.4. ODT behavior during Write operation
2.16.5. Functional Representation of ODT
2.17. R/B and SR[6] Relationship
2.18. Write Protect
3. MEMORY ORGANIZATION
3.1. Addressing
3.1.1. Plane Addressing
3.1.2. Extended Blocks Arrangement
3.2. Factory Defect Mapping
3.2.1. Device Requirements
3.2.2. Host Requirements
4. FUNCTION DESCRIPTION
4.1. Discovery and Initialization
4.1.1. Power-on/off sequence
4.1.2. VPP Initialization
4.1.3. Single Channel Discovery
4.1.4. Dual Channel Discovery
4.2. Mode Selection
4.2.1. Toggle DDR2.0 General Timing
4.2.2. SDR General Timing
4.3. AC Timing Characteristics
5. COMMAND DESCRIPTION AND DEVICE OPERATION
5.1. Basic Command Sets
TOSHIBA CONFIDENTIAL
TOSHIBA
NAND Memory
Toggle DDR2.0
Technical Data Sheet
Rev. 1.0
2015 – 03 – 16
TOSHIBA
Semiconductor & Storage Products
Memory Division
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CONTENTS
INTRODUCTION ............................................................................................................................................. 7
1.
General Description ...................................................................................................................................... 7
1.1.
Definitions and Abbreviations ...................................................................................................................... 7
1.2.
Features ........................................................................................................................................................ 9
1.3.
Diagram Legend.......................................................................................................................................... 10
1.4.
PHYSICAL INTERFACE ................................................................................................................................ 11
2.
Pin Descriptions .......................................................................................................................................... 11
2.1.
PIN ASSIGNMENT (TOP VIEW) .............................................................................................................. 12
2.2.
BLOCK DIAGRAM ..................................................................................................................................... 13
2.3.
Independent Data Buses ............................................................................................................................ 16
2.4.
Absolute Maximum Rating ......................................................................................................................... 16
2.5.
Operating Temperature Condition ............................................................................................................. 16
2.6.
Recommended Operating Conditions ......................................................................................................... 17
2.7.
Valid Blocks ................................................................................................................................................. 18
2.8.
2.9.
AC Overshoot/Undershoot Requirements .................................................................................................. 18
2.10. DC Operating Characteristics .................................................................................................................... 19
2.11. Differential Input AC Characteristics ........................................................................................................ 21
2.12.
Input/Output Capacitance (TOPER =25℃, f=1MHz, VccQ=1.8V) ............................................................... 21
2.13. DQ Driver Strength .................................................................................................................................... 21
2.14. Operating condition on transfer rate ......................................................................................................... 22
2.15.
Input/Output Slew rate .............................................................................................................................. 23
2.16. High Speed Toggle DDR with ODT ............................................................................................................ 25
ODT (On die termination) ...................................................................................................................... 25
2.16.1.
ODT setting ............................................................................................................................................. 25
2.16.2.
ODT behavior during Read operation .................................................................................................... 25
2.16.3.
2.16.4.
ODT behavior during Write operation ................................................................................................... 26
2.16.5.
Functional Representation of ODT ........................................................................................................ 26
2.17. R/ B and SR[6] Relationship ..................................................................................................................... 27
2.18. Write Protect ............................................................................................................................................... 27
3. MEMORY ORGANIZATION .......................................................................................................................... 28
3.1.
Addressing ................................................................................................................................................... 29
Plane Addressing .................................................................................................................................... 30
3.1.1.
Extended Blocks Arrangement............................................................................................................... 30
3.1.2.
Factory Defect Mapping ............................................................................................................................. 31
3.2.
3.2.1.
Device Requirements .............................................................................................................................. 31
3.2.2.
Host Requirements ................................................................................................................................. 32
FUNCTION DESCRIPTION .......................................................................................................................... 33
4.
Discovery and Initialization ....................................................................................................................... 33
4.1.
4.1.1.
Power-on/off sequence............................................................................................................................. 33
VPP Initialization ..................................................................................................................................... 34
4.1.2.
Single Channel Discovery....................................................................................................................... 34
4.1.3.
4.1.4.
Dual Channel Discovery ......................................................................................................................... 34
4.2. Mode Selection ............................................................................................................................................ 35
4.2.1.
Toggle DDR2.0 General Timing ............................................................................................................. 37
4.2.1.1. Command Latch Cycle ............................................................................................................................ 37
4.2.1.2. Address Latch Cycle ............................................................................................................................... 37
4.2.1.3. Basic Data Input Timing ........................................................................................................................ 38
4.2.1.4. Basic Data Output Timing ..................................................................................................................... 39
4.2.1.5. Bus Driving ............................................................................................................................................. 40
4.2.1.6. Read ID Operation .................................................................................................................................. 40
4.2.1.7.
Status Read Cycle ................................................................................................................................... 41
4.2.1.8.
Set Feature.............................................................................................................................................. 42
4.2.1.9. Get Feature ............................................................................................................................................. 42
Page Read Operation .......................................................................................................................... 43
4.2.1.10.
Page Read Operation with Random Data Output ............................................................................ 44
4.2.1.11.
4.2.1.12.
Page Program Operation .................................................................................................................... 45
Page Program Operation with Random Data Input ......................................................................... 46
4.2.1.13.
4.2.2.
SDR General Timing .............................................................................................................................. 47
4.2.2.1. Command Latch Cycle ............................................................................................................................ 47
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4.2.2.2. Address Latch Cycle ............................................................................................................................... 47
4.2.2.3. Basic Data Input Timing ........................................................................................................................ 48
4.2.2.4. Basic Data Output Timing ..................................................................................................................... 48
4.2.2.5. Read ID Operation .................................................................................................................................. 49
Status Read Cycle ................................................................................................................................... 50
4.2.2.6.
4.2.2.7.
Set Feature.............................................................................................................................................. 51
4.2.2.8. Get Feature ............................................................................................................................................. 51
Page Read Operation .............................................................................................................................. 52
4.2.2.9.
Page Program Operation .................................................................................................................... 53
4.2.2.10.
AC Timing Characteristics ......................................................................................................................... 54
4.3.
4.3.1.
Timing Parameters Description ............................................................................................................. 54
4.3.2.
Timing Parameters Table ....................................................................................................................... 56
COMMAND DESCRIPTION AND DEVICE OPERATION .......................................................................... 59
5.
Basic Command Sets .................................................................................................................................. 59
5.1.
5.2.
Basic Operation ........................................................................................................................................... 60
Page Read Operation .............................................................................................................................. 60
5.2.1.
5.2.1.1.
Page Read Operation with Random Data Output ................................................................................. 60
5.2.1.2. Data Out After Status Read ................................................................................................................... 61
5.2.2.
Sequential Cache Read Operation ......................................................................................................... 61
Random Cache Read Operation ............................................................................................................. 62
5.2.3.
Random Data Output for Cache Read ................................................................................................... 62
5.2.4.
Page Program Operation ........................................................................................................................ 63
5.2.5.
5.2.5.1.
Program Operation with Random Data Input ...................................................................................... 63
Cache Program Operation ...................................................................................................................... 64
5.2.6.
Block Erase Operation ............................................................................................................................ 64
5.2.7.
5.2.8.
Copy-Back Program Operation .............................................................................................................. 65
5.2.8.1. Copy-Back Program Operation with Random Data Input .................................................................... 65
Set Feature Operation ............................................................................................................................ 66
5.2.9.
Toggle specific setting (02h) ................................................................................................................... 67
5.2.9.1.
5.2.9.2.
Interface change (80h) ............................................................................................................................ 67
5.2.9.3. Driver strength setting (10h) ................................................................................................................. 68
5.2.9.4. External Vpp(30h) .................................................................................................................................. 68
Get Feature Operation ........................................................................................................................... 69
5.2.10.
Read ID Operation .................................................................................................................................. 70
5.2.11.
00h Address ID Definition .................................................................................................................. 70
5.2.11.1.
5.2.11.2.
40h Address ID Definition .................................................................................................................. 71
Read Status Operation ........................................................................................................................... 72
5.2.12.
Reset Operation ...................................................................................................................................... 73
5.2.13.
Reset LUN Operation ............................................................................................................................. 74
5.2.14.
5.3.
Extended Operation .................................................................................................................................... 75
Extended Command Sets ....................................................................................................................... 75
5.3.1.
Address Input Restrictions for Multi Page / Multi Block Operation .................................................... 76
5.3.2.
Multi Page Read Operation .................................................................................................................... 76
5.3.3.
5.3.4.
Multi Page Sequential Cache Read Operation ...................................................................................... 78
Multi Page Random Cache Read Operation .......................................................................................... 80
5.3.5.
Multi Page Program Operation .............................................................................................................. 81
5.3.6.
Multi Page Cache Program Operation ................................................................................................... 82
5.3.7.
5.3.8.
Multi Block Erase Operation ................................................................................................................. 83
Multi Copy-Back Program Operation .................................................................................................... 83
5.3.9.
5.3.10.
Page Copy (2) Operation ......................................................................................................................... 84
5.3.11. Multi Page Copy (2) Operation .............................................................................................................. 85
5.3.12.
Device Identification Table Read Operation .......................................................................................... 87
Parameter Page Definition ..................................................................................................................... 88
5.3.13.
Read Status Enhanced ......................................................................................................................... 100
5.3.14.
Read LUN #0 Status Operation ........................................................................................................... 101
5.3.15.
Read LUN #1 Status Operation ........................................................................................................... 102
5.3.16.
5.4.
Interleaving Operation ............................................................................................................................. 102
Interleaving Page Program .................................................................................................................. 103
5.4.1.
Interleaving Page Read ........................................................................................................................ 104
5.4.2.
5.4.3.
Interleaving Block Erase ...................................................................................................................... 105
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5.4.4.
Interleaving Multi Page Program ........................................................................................................ 106
5.4.5.
Interleaving Multi Page Read .............................................................................................................. 107
5.4.6.
Interleaving Multi Block Erase ............................................................................................................ 109
5.4.7.
Interleaving Page Program to Read ..................................................................................................... 110
5.4.8.
Interleaving Copy-Back Program (1/2) ................................................................................................ 111
5.4.9.
Interleaving Copy-Back Program (2/2) ................................................................................................ 112
5.4.10.
Interleaving Multi Copy Back Program (1/2) ...................................................................................... 113
5.4.11.
Interleaving Multi Copy Back Program (2/2) ...................................................................................... 114
6.
APPLICATION NOTES AND COMMENTS................................................................................................ 115
7.
Package Dimensions ..................................................................................................................................... 121
8.
Revision History ............................................................................................................................................ 122
RESTRICTIONS ON PRODUCT USE .................................................................................................................. 123
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LIST of FIGURES
Figure 1. Block Diagram (TC58TFG7DDLTA0D) ................................................................................................... 13
Figure 2. Block Diagram (TH58TFG8DDLTA2D) ................................................................................................... 14
Figure 3. Block Diagram (TH58TFG9DDLTA2D) ................................................................................................... 15
Figure 4. Overshoot/Undershoot Diagram .............................................................................................................. 18
Figure 5. Differential Input Signal .......................................................................................................................... 21
Figure 6 tRISE and tFALL Definition for Output Slew Rate ................................................................................. 24
Figure 7 ODT setting through ‘SET FEATURE’ ..................................................................................................... 25
Figure 8 ODT enable/disable during Read .............................................................................................................. 25
Figure 9. ODT enable/disable during Write ............................................................................................................ 26
Figure 10. Functional Representation of ODT ........................................................................................................ 26
Figure 11. Write Protect timing requirements of the Program operation .............................................................. 27
Figure 12. Write Protect timing requirements of the Erase operation .................................................................. 27
Figure 13. Target Organization ............................................................................................................................... 28
Figure 14. Row Address Layout ............................................................................................................................... 29
Figure 15. Position of Plane Address ....................................................................................................................... 30
Figure 16. Area marked in first or last page of block indicating defect ................................................................. 31
Figure 17. Flow chart to create initial invalid block table...................................................................................... 32
Figure 18. Initialization Timing .............................................................................................................................. 33
Figure 19. Command Latch Cycle Timing ............................................................................................................... 37
Figure 20. Address Latch Cycle Timing................................................................................................................... 37
Figure 21. Basic Data Input Timing ........................................................................................................................ 38
Figure 22. Basic Data Output Timing ..................................................................................................................... 39
Figure 23. Bus Driving Timing ................................................................................................................................ 40
Figure 24. Read ID Operation Timing ..................................................................................................................... 40
Figure 25. Status Read Cycle Timing ...................................................................................................................... 41
Figure 26. Status Read Cycle Timing before toggle mode setting at power up sequence ..................................... 41
Figure 27. Set Feature Timing ................................................................................................................................. 42
Figure 28. Get Feature Timing ................................................................................................................................ 42
Figure 29. Page Read Operation Timing ................................................................................................................. 43
Figure 30. Read Hold Operation with CE high .................................................................................................... 43
Figure 31. Page Read Operation with Random Data Output................................................................................. 44
Figure 32. Page Program Operation Timing ........................................................................................................... 45
Figure 33. Page Program Operation with Random Data Input Timing ................................................................ 46
Figure 34. Command Latch Cycle Timing ............................................................................................................... 47
Figure 35. Address Latch Cycle Timing................................................................................................................... 47
Figure 36. Basic Data Input Timing ........................................................................................................................ 48
Figure 37. Basic Data Output Timing ..................................................................................................................... 48
Figure 38. Read ID Operation Timing ..................................................................................................................... 49
Figure 39. Status Read Cycle Timing ...................................................................................................................... 50
Figure 40. Set Feature Timing ................................................................................................................................. 51
Figure 41. Get Feature Timing ................................................................................................................................ 51
Figure 42. Page Read Operation Timing ................................................................................................................. 52
Figure 43. Page Program Operation Timing ........................................................................................................... 53
Figure 44. Page Read Timing ................................................................................................................................... 60
Figure 45. Page Read with Random Data Output Timing ..................................................................................... 60
Figure 46. Data Out After Status Read Timing ...................................................................................................... 61
Figure 47. Sequential Cache Read Timing .............................................................................................................. 61
Figure 48 Random Cache Read Timing ................................................................................................................... 62
Figure 49 Random Data Output for Cache Read Timing ....................................................................................... 62
Figure 50 Page Program Timing .............................................................................................................................. 63
Figure 51. Program operation with Random Data Input Timing .......................................................................... 63
Figure 52. Cache Program Timing ........................................................................................................................... 64
Figure 53. Block Erase Timing ................................................................................................................................ 64
Figure 54. Copy-Back Program Timing ................................................................................................................... 65
Figure 55. Copy-Back Program with Random Data Input Timing ........................................................................ 65
Figure 56. Set Feature Timing ................................................................................................................................. 66
Figure 57. Get Feature Timing ................................................................................................................................ 69
Figure 58 Read ID Timing........................................................................................................................................ 70
Figure 59. Read Status Timing ................................................................................................................................ 72
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Figure 60. Reset timing ............................................................................................................................................ 73
Figure 61. Reset timing during Program operation ................................................................................................ 73
Figure 62. Reset timing during Erase operation ..................................................................................................... 73
Figure 63. Reset timing during Read operation ...................................................................................................... 73
Figure 64. Status Read after Reset operation ......................................................................................................... 74
Figure 65. Successive Reset operation ..................................................................................................................... 74
Figure 66. Single LUN Reset Timing ...................................................................................................................... 74
Figure 67. Example Timing with Multi Page Read (Primary) ............................................................................... 76
Figure 68. Example Timing with Multi Page Read (Secondary) ............................................................................ 77
Figure 69. Example Timing with Multi Page Cache Read (Primary) .................................................................... 78
Figure 70. Example Timing with Multi Page Cache Read (Secondary) ................................................................. 79
Figure 71. Example Timing with Multi Page Cache Read (Primary) .................................................................... 80
Figure 72. Example Timing with Multi Page Program .......................................................................................... 81
Figure 73. Example Timing with Multi Page Cache Program ............................................................................... 82
Figure 74. Example Timing with Multi Block Erase .............................................................................................. 83
Figure 75. Example Timing with Multi Copy-Back Program (Primary) ................................................................ 83
Figure 76. Example Timing with Multi Copy-Back Program (Secondary) ............................................................ 84
Figure 77. Example Timing with Page Copy (2) ..................................................................................................... 84
Figure 78. Example Timing with Multi Page Copy (2) ........................................................................................... 86
Figure 79. Example Timing with Multi Page Copy (2) ........................................................................................... 87
Figure 80. Device Identification Table Read Timing .............................................................................................. 87
Figure 81. Read Status Timing .............................................................................................................................. 100
Figure 82. Read LUN#0 Status Timing ................................................................................................................. 101
Figure 83. Read LUN#1 Status Timing ................................................................................................................. 102
Figure 84. Example Timing with Interleaving Page Program ............................................................................. 103
Figure 85. Example Timing with Interleaving Page Read ................................................................................... 104
Figure 86. Example Timing with Interleaving Block Erase ................................................................................. 105
Figure 87. Example Timing with Interleaving Multi Page Program ................................................................... 106
Figure 88 Example Timing with Interleaving Multi Page Read .......................................................................... 108
Figure 89. Example Timing with Interleaving Multi Block Erase ....................................................................... 109
Figure 90. Example Timing with Interleaving Page Program to Read. ............................................................... 110
Figure 91. Example Timing with Interleaving Copy-Back Program ................................................................... 112
Figure 92. Example Timing with Interleaving Multi Copy-Back Program ......................................................... 114
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LIST of TABLES
TOSHIBA CONFIDENTIAL
______
Table 1 Product Organization .................................................................................................................................... 9
Table 2 Supported Operation Modes ........................................................................................................................ 9
Table 3 Pin Descriptions.......................................................................................................................................... 11
mapping .................................................................................... 16
Table 4 Dual Channel(x8) Data Bus Signal to CE
Table 5 Absolute Maximum Rating ....................................................................................................................... 16
Table 6 Operating Temperature Condition ........................................................................................................... 16
Table 7 Recommended Operating Condition ........................................................................................................ 17
Table 8 Valid Blocks ................................................................................................................................................ 18
Table 9 AC Overshoot/Undershoot Specification .................................................................................................... 18
Table 10 DC & Operating Characteristics for VccQ=3.3V ....................................................................................... 19
Table 11 DC & Operating Characteristics for VccQ=1.8V ....................................................................................... 20
Table 12 AC Characteristics for Differential Input Signal ......................................................................................... 21
Table 13 Input/ Output capacitance ...................................................................................................................... 21
Table 14 DQ Drive Strength Settings ...................................................................................................................... 21
Table 15 Testing Conditions for Impedance Values ................................................................................................. 21
Table 16 Output Drive Strength Impedance Values ................................................................................................ 22
Table 17 Pull-up and Pull-down Output Impedance Mismatch ................................................................................ 22
Table 18 Operating condition on the transfer rate ................................................................................................... 22
Table 19 Derating factor (Differential signaling) ...................................................................................................... 23
Table 20 Derating factor (Single-ended signaling) .................................................................................................. 23
Table 21 Input Slew Rate ........................................................................................................................................ 23
Table 22 Testing Conditions for Input Slew Rate ..................................................................................................... 23
Table 23 Output Slew Rate Requirements .............................................................................................................. 23
Table 24 Testing Conditions for Output Slew Rate .................................................................................................. 24
Table 25. The addressing of this device. .................................................................................................................. 29
Table 26. Extended Blocks Arrangement for LUN #0 ............................................................................................. 30
Table 27. Extended Blocks Arrangement for LUN #1 ............................................................................................. 30
Table 28 Mode Selection ......................................................................................................................................... 35
Table 29 SDR Interface Mode Selection .................................................................................................................. 36
Table 30 Toggle DDR Timing Parameters Description Toggle DDR ..................................................................... 54
Table 31 AC Timing Characteristics Toggle DDR2.0 ............................................................................................... 56
Table 32 AC Test Conditions ................................................................................................................................... 58
Table 33 Read/Program/Erase Timing Characteristics ............................................................................................ 58
Table 34 Basic Command Sets ............................................................................................................................... 59
Table 35 Set feature addresses .............................................................................................................................. 66
Table 36 Toggle specific setting Data ...................................................................................................................... 67
Table 37 Toggle specific setting Data Definition ...................................................................................................... 67
Table 38 Interface change setting data ................................................................................................................... 67
Table 39 Driver Strength Setting Data ..................................................................................................................... 68
Table 40 External VPP Setting Data ....................................................................................................................... 68
Table 41 External VPP Setting Data Definition........................................................................................................ 68
Table 42 00h Address ID Definition Table................................................................................................................ 70
Table 43 2nd ID Data .............................................................................................................................................. 70
Table 44 3rd ID Data ............................................................................................................................................... 70
Table 45 4th ID Data ............................................................................................................................................... 70
Table 46 5th ID Data ............................................................................................................................................... 71
Table 47 6th ID Data ............................................................................................................................................... 71
Table 48 40h Address ID Cycle ............................................................................................................................... 71
Table 49 40h Address ID Definition ......................................................................................................................... 71
Table 50 Read Status Definition for 70h .................................................................................................................. 72
Table 51 Read Status Definition for 71h .................................................................................................................. 72
Table 52 Extended Command Sets ......................................................................................................................... 75
Table 53 Parameter Page Definitions ...................................................................................................................... 88
Table 54 Read Status Enhanced Definition ........................................................................................................... 100
Table 55 Read LUN#0 Status Definition ................................................................................................................ 101
Table 56 Read LUN#1 Status Definition ................................................................................................................ 102
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1.
INTRODUCTION
1.1. General Description
Toggle DDR is a NAND interface for high performance applications which support data read and write operations
using bidirectional DQS.
Toggle DDR NAND has implemented ’Double Data Rate’ without a clock. It is compatible with functions and
command which have been supported in conventional type NAND(i.e. SDR NAND) while providing high data
transfer rate based on the high-speed Toggle DDR Interface and saving power with separated DQ voltage. For
applications that require high capacity and high performance NAND, Toggle DDR NAND is the most appropriate.
Toggle DDR2.0 NAND supports the interface speed of up to 200 MHz (400 Mbps), which is 10 times faster than the
data transfer rate offered by SDR NAND (40 Mbps). Toggle DDR NAND transfers data at high speed using DQS
signal that behaves as a clock, and DQS shall be used only when data is transferred for optimal power consumption.
This device supports both SDR interface and Toggle DDR interface. When starting, the device is activated in SDR
mode. The interface mode can be changed into Toggle DDR interface utilizing specific command issued by the Host.
1.2. Definitions and Abbreviations
SDR
Acronym for single data rate.
DDR
Acronym for double data rate.
Address
The address is comprised of a column address with 2 cycles and a row address with 3 cycles. The row address
identifies the page, block and LUN to be accessed. The column address identifies the byte within a page to access.
The least significant bit of the column address shall always be zero.
Column
The byte location within the page register.
Row
Refer to the block and page to be accessed.
Page
The smallest addressable unit for the Read and the Program operations.
Block
Consists of multiple pages and is the smallest addressable unit for the Erase operation.
Plane
The unit that consists of a number of blocks. There are one or more Planes per LUN.
Page register
Register used to transfer data to and from the Flash Array.
Cache register
Register used to transfer data to and from the Host.
Defect area
The defect area is where factory defects are marked by the manufacturer. Refer to the section 3.2.
Device
The packaged NAND unit. A device may contain more than a target.
LUN (Logical Unit Number)
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