ZCU102开发板原理图.pdf

发布时间：2022-05-30 发布人：admin 分类：说明书资料大小：4.57M 资料格式：pdf 举报版权申诉

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HW-Z1-ZCU102_REV1_0 Sheet Title Page (1)

HW-Z1-ZCU102_REV1_0 Sheet Block Diagram (2)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Bank 0 (3)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 44 (4)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 47 48 (5)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 49 50 (6)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 64 65 (7)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 66 67 (8)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 128 129 130 (9)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 228 229 230 (10)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 500 501 502 - MIO (11)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 503 - Config (12)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 504 - Memory (13)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Banks 505 - GTR (14)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Power 1 (15)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Power 2 (16)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Power 3 (17)

HW-Z1-ZCU102_REV1_0 Sheet Zynq GND (18)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Decoupling 1 (19)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Decoupling 2 (20)

HW-Z1-ZCU102_REV1_0 Sheet Zynq Decoupling 3 (21)

HW-Z1-ZCU102_REV1_0 Sheet JTAG Headers (22)

HW-Z1-ZCU102_REV1_0 Sheet PS DDR4 SODIMM 72 bit (23)

HW-Z1-ZCU102_REV1_0 Sheet PS DDR4 SODIMM Decoupling (24)

HW-Z1-ZCU102_REV1_0 Sheet PL Component DDR4 [15-0] (25)

HW-Z1-ZCU102_REV1_0 Sheet PL FMC HPC0 Header Rows A B C D (26)

HW-Z1-ZCU102_REV1_0 Sheet PL FMC HPC0 Header Rows E F G (27)

HW-Z1-ZCU102_REV1_0 Sheet PL FMC HPC0 Header Rows H J K (28)

HW-Z1-ZCU102_REV1_0 Sheet PL FMC HPC0 Header GND (29)

HW-Z1-ZCU102_REV1_0 Sheet PL FMC HPC1 Header Rows A B C D (30)

HW-Z1-ZCU102_REV1_0 Sheet PL FMC HPC1 Header Rows E F G (31)

HW-Z1-ZCU102_REV1_0 Sheet PL FMC HPC1 Header Rows H J K (32)

HW-Z1-ZCU102_REV1_0 Sheet PL FMC HPC1 Header GND (33)

HW-Z1-ZCU102_REV1_0 Sheet PL SFP+ 2x2 Cage (34)

HW-Z1-ZCU102_REV1_0 Sheet PL HDMI TX (35)

HW-Z1-ZCU102_REV1_0 Sheet PL HDMI RX (36)

HW-Z1-ZCU102_REV1_0 Sheet PL HDMI Clock Recovery (37)

HW-Z1-ZCU102_REV1_0 Sheet System Controller (38)

HW-Z1-ZCU102_REV1_0 Sheet Fixed Clocks (39)

HW-Z1-ZCU102_REV1_0 Sheet PL Programmable Clocks - SMAs (40)

HW-Z1-ZCU102_REV1_0 Sheet PL SFP Clock Recovery (41)

HW-Z1-ZCU102_REV1_0 Sheet Quad USB UART - EEPROM (42)

HW-Z1-ZCU102_REV1_0 Sheet PS PCIe x4 Slot - x8 Connector (43)

HW-Z1-ZCU102_REV1_0 Sheet PS Display Port Connector (44)

HW-Z1-ZCU102_REV1_0 Sheet PS Display Port IO (45)

HW-Z1-ZCU102_REV1_0 Sheet PS QSPI (46)

HW-Z1-ZCU102_REV1_0 Sheet PS SD Card Connector (47)

HW-Z1-ZCU102_REV1_0 Sheet PS GTR MUX - SATA (48)

HW-Z1-ZCU102_REV1_0 Sheet PS MIO PMOD - Button - LED (49)

HW-Z1-ZCU102_REV1_0 Sheet PS CAN Bus (50)

HW-Z1-ZCU102_REV1_0 Sheet PS USB 3_0 ULPI 0 (51)

HW-Z1-ZCU102_REV1_0 Sheet PS 10/100/1000 Ethernet PHY (52)

HW-Z1-ZCU102_REV1_0 Sheet PL Buttons - Switches - LEDs (53)

HW-Z1-ZCU102_REV1_0 Sheet PL EMIO ARM Trace Debug (54)

HW-Z1-ZCU102_REV1_0 Sheet PL PMODs (55)

HW-Z1-ZCU102_REV1_0 Sheet PL SYSMON Prototype Header (56)

HW-Z1-ZCU102_REV1_0 Sheet I2C0 MUXes Expanders Level Shifters PMBUS Header (57)

HW-Z1-ZCU102_REV1_0 Sheet I2C1 MUXes and Level Shifters (58)

HW-Z1-ZCU102_REV1_0 Sheet 12V Power Connectors Switch (59)

HW-Z1-ZCU102_REV1_0 Sheet VCCINT 40A Regulator (60)

HW-Z1-ZCU102_REV1_0 Sheet VCCBRAM 6A Regulator (61)

HW-Z1-ZCU102_REV1_0 Sheet VCCAUX 3A Regulator (62)

HW-Z1-ZCU102_REV1_0 Sheet VCC1V2 2A Regulator (63)

HW-Z1-ZCU102_REV1_0 Sheet VCC3V3 5A Regulator (64)

HW-Z1-ZCU102_REV1_0 Sheet VADJ_FMC 10A Regulator (65)

HW-Z1-ZCU102_REV1_0 Sheet PL_DDR4_VPP_2V5 1A Regulator (66)

HW-Z1-ZCU102_REV1_0 Sheet MGTAVCC 6A Regulator (67)

HW-Z1-ZCU102_REV1_0 Sheet MGTAVTT 6A Regulator (68)

HW-Z1-ZCU102_REV1_0 Sheet MGTVCCAUX 1A Regulator (69)

HW-Z1-ZCU102_REV1_0 Sheet VCCPSINTFP 10A Regulator (70)

HW-Z1-ZCU102_REV1_0 Sheet VCCPSINTLP 2A Regulator (71)

HW-Z1-ZCU102_REV1_0 Sheet VCCPSAUX 500MA Regulator (72)

HW-Z1-ZCU102_REV1_0 Sheet VCCPSPLL 200MA Regulator (73)

HW-Z1-ZCU102_REV1_0 Sheet MGTRAVCC 400MA Regulator (74)

HW-Z1-ZCU102_REV1_0 Sheet MGTRAVTT 100MA Regulator (75)

HW-Z1-ZCU102_REV1_0 Sheet DDR4_DIMM_VDDQ 6A Regulator (76)

HW-Z1-ZCU102_REV1_0 Sheet PS_DDR4_VPP_2V5 1A Regulator (77)

HW-Z1-ZCU102_REV1_0 Sheet VCCOPS 4A Regulator (78)

HW-Z1-ZCU102_REV1_0 Sheet VCCOPS3 300MA Regulator (79)

HW-Z1-ZCU102_REV1_0 Sheet VCCPSDDRPLL 100MA Regulator (80)

HW-Z1-ZCU102_REV1_0 Sheet UTIL_1V13 1A Regulator (81)

HW-Z1-ZCU102_REV1_0 Sheet UTIL_1V8 1A Regulator (82)

HW-Z1-ZCU102_REV1_0 Sheet UTIL_3V3 20A Regulator (83)

HW-Z1-ZCU102_REV1_0 Sheet UTIL_5V0 6A Regulator (84)

HW-Z1-ZCU102_REV1_0 Sheet DDR4 Termination Supply (85)

HW-Z1-ZCU102_REV1_0 Sheet Power Status LEDs (86)

HW-Z1-ZCU102_REV1_0 Sheet Mechanical Components (87)

D C B A 4 3 2 1 HW-Z1-ZCU102 Evaluation Board (XCZU9EG-FFVB1156) DISCLAIMER: XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC, AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE IN THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES. YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST, OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING, BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING, OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX. XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OF THE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION, TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES NO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, OR TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR ASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE DOCUMENTATION. THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. TITLE: Title Page SCHEM, ROHS COMPLIANT HW-Z1-ZCU102_REV1_0 DATE: 09/20/2016:10:26 SHEET SIZE: B SHEET 1 OF 87 ASSY P/N: 0431959 PCB P/N: 1280868 SCH P/N: 0381701 TEST P/N: TSS0179 VER: REV: DRAWN BY: 1.0 01 BF 4 3 2 1 D C B A

4 3 2 1 Prototype Header Display Port Aux MSP430 GPIO IIC0 Connection SYSMON IIC SFP Disables MSP430/CP2108 UART HDMI Control PMOD 125MHz CLK Trace IIC1 Connection Ethernet USB SDIO PMU GPIO PS Display Port Aux 12VDC Pages 44, 56, 38 Pages 6, 34 Pages 54-55, 58 Page 51-52 Pages 47, 44-45 D C B A SFP 2x2 Cage Page 34 FMC HPC0 GT Interface Pages 26-29 FMC HPC0 LA Bus SFP Recovered Clock Pages 26-29 Page 34 FMC HPC0 LA bus HDMI Recovered Clock Pages 41-43 Page 35-37 FMC HPC1 LA Bus Pages 30-33 HDMI TX Clock Pages 35-37 DDR4 Comp. Memory 16-bit: 1 x 16-bit MT40A256M16GE-075E Page 25 49 50 67 HP 48 47 PS 502 PS 501 U1 0 PS 503 (PS-Side CONFIG) XCZU9EGFFVB1156 PS PWR GTH130 GTH129 GTH128 PS GTR505 PS 500 44 PS 504 PS DDR GTH230 GTH229 GTH228 66 HP 65 HP 64 HP FMC HPC1 GT Interface Pages 30-33 HDMI SMA Pages 35-37, 40 MUX connections: PCIe / DisplayPort USB3.0 / SATA Page 43-45, 48, 51 INIT,DONE LEDs PROG. PB PS POR, SRST PBs Page 12 SI570 Programmable Oscillator GPIO 74.25MHz clk PS UART PS I2C PS QSPI DDR4 DUAL 72-Bit SODIMM DDR4 DIMM DECOUPLING Page 40 Page 39 Page 42, 46, 57-58 Page 23 Page 24 PS/PL/System Clock devices JTAG CONN. BANK# PAGE# BANK# PAGE# MECHANICALS Pages 39-41 Page 22 GTR Muxes Pages 48 BANK 0 PS 503 PSDDR 504 BANK 64 BANK 66 BANK 65 BANK 67 PS 500 PS 501, 502 BANK 44 3 12 13 7 8 7 8 11 11 4 BANK 47 BANK 48 BANK 49 BANK 50 MGTH128-130 MGTH228-230 MGTR 505 PWR CONNECTORS 5 5 6 6 9 10 14 59 Page 87 PL PMBUS RAILS: VCCINT @ 40A VCCBRAM @ 6A VCCAUX @ 3A VCC1V2 @ 2A VADJ_FMC @ 10A MGTAVCC @ 6A MGTAVTT @ 6A Pages 60-68 PS PMBUS RAILS: VCCPSINTFP @ 10A VCCPSINTLP @ 2A DDR4_DIMM_VDDDQ @ 6A VCCOPS @ 4A Pags 70-78 Main PMBUS UTIL RAILS UTIL_5V0 @ 10A UTIL_3V3 @ 20A Page 83-84 PL LDOs: PL_DDR4_VPP_2V5 @ 1A PL DDR4 VTT @ 6A MGTVCCAUX @ 1A Page 66, 69, 85 PS LDOs: PS_DDR4_VPP_2V5 @ 1A PS DDR4 VTT @ 6A VCCPSAUX @ 500mA VCCPSPLL @ 200mA MGTRAVCC @ 400mA MGTRAVTT @ 100mA VCCOPS3 @ 300mA VCCPSDDRPLL @ 100mA Page 72-80, 85 UTIL LDOs: UTIL_1V13 @ 1A UTIL_1V8 @ 1A Page 83 TITLE: Block Diagram SCHEM, ROHS COMPLIANT HW-Z1-ZCU102_REV1_0 DATE: 09/20/2016:10:26 SHEET SIZE: B SHEET 2 OF 87 ASSY P/N: 0431959 PCB P/N: 1280868 SCH P/N: 0381701 TEST P/N: TSS0179 VER: REV: DRAWN BY: 1.0 01 BF D C B A 4 3 2 1

4 3 2 1 POR_OVERRIDE select Default: 2-3 GND VCCINT 5 8 J 1 2 3 3 X 1 _ R D H GND SOC_DA7_FFVB1156_IRONWOOD BANK 0 XCZU9FFVB1156 PUDC_B_0_AD15 POR_OVERRIDE_AD14 DXP_W18 DXN_W17 VCCADC_T18 GNDADC_T17 VREFP_V18 VREFN_U17 VP_U18 VN_V17 AD15 AD14 W18 W17 T18 T17 V18 U17 U18 V17 U1 SOC_1156_1MM_IRON SYSMON_DXP SYSMON_DXN SYSMON_VREFP SYSMON_VP_R SYSMON_VN_R 1 2 C25 0.1UF 25V 1 2 R94 4.70K 1% GND IC VOLT REF, 1.25V SOT23_3 FPGA_SYSMON_AVCC 1 REF3012 IN OUT 2 1 2 C492 0.47UF 10V GND 3 U64 1 2 C384 10UF 10V SYSMON_VREFP SYSMON_VREF J90 1 2 3 HDR_1X3 SYSMON_AGND FERRITE-600 2 1 L55 GND SYSMON_AGND D C B A VCCAUX 1 2 1 2 R397 1.00K 1% R291 DNP DNP GND 1 2 VCCAUX FERRITE-600 FPGA_SYSMON_AVCC C902 0.47UF 10V C1 0.1UF 25V 2 1 1 L16 2 SYSMON_AGND FERRITE-600 1 L17 2 SYSMON_AGND GND VCCAUX R290 DNP DNP SYSMON_VP_R_I2C 2 J12 1 SYSMON_VP_R HDR_1X2 1 2 R132 20.5K 1% 1 2 GND 2 SYSMON_VN_R_I2C J13 1 HDR_1X2 SYSMON_VN_R R133 20.5K 1% 1 2 GND SYSMON I2C Address jumpers SYSMON_VP_R SYSMON_VN_R 1 2 C408 2700PF 50V 3 3 4 R 0 0 1 % 1 21 2 3 4 R 0 0 1 % 1 21 SYSMON_VP SYSMON_VN SYSMON_VREF SYSMON_VN VCCINT_VIN_R_N SYSMON_DXP SYSMON_DXN FPGA_SYSMON_AVCC SYSMON_VP VCCINT_VIN_R_P J93 NC NC 1 3 5 7 9 11 2 4 6 8 10 12 70246-1201 SYSMON_AGND Zynq Bank 0 TITLE: Zynq Bank 0 SCHEM, ROHS COMPLIANT HW-Z1-ZCU102_REV1_0 DATE: 09/20/2016:10:26 SHEET SIZE: B SHEET 3 OF 87 ASSY P/N: 0431959 PCB P/N: 1280868 SCH P/N: 0381701 TEST P/N: TSS0179 VER: REV: DRAWN BY: 1.0 01 BF D C B A 4 3 2 1

4 3 2 1 D C B A SOC_DA7_FFVB1156_IRONWOOD BANK 44 XCZU9FFVB1156 IO_L12N_AD0N_44_AE14 IO_L12P_AD0P_44_AE15 IO_L11N_AD1N_44_AG15 IO_L11P_AD1P_44_AF15 IO_L10N_AD2N_44_AG13 IO_L10P_AD2P_44_AG14 IO_L9N_AD3N_44_AF13 IO_L9P_AD3P_44_AE13 IO_L8N_HDGC_AD4N_44_AJ14 IO_L8P_HDGC_AD4P_44_AJ15 IO_L7N_HDGC_AD5N_44_AH13 IO_L7P_HDGC_AD5P_44_AH14 IO_L6N_HDGC_AD6N_44_AL12 IO_L6P_HDGC_AD6P_44_AK13 IO_L5N_HDGC_AD7N_44_AK14 IO_L5P_HDGC_AD7P_44_AK15 IO_L4N_AD8N_44_AM13 IO_L4P_AD8P_44_AL13 IO_L3N_AD9N_44_AP12 IO_L3P_AD9P_44_AN12 IO_L2N_AD10N_44_AN13 IO_L2P_AD10P_44_AM14 IO_L1N_AD11N_44_AP14 IO_L1P_AD11P_44_AN14 AE14 AE15 AG15 AF15 AG13 AG14 AF13 AE13 AJ14 AJ15 AH13 AH14 AL12 AK13 AK14 AK15 AM13 AL13 AP12 AN12 AN13 AM14 AP14 AN14 GPIO_SW_E GPIO_SW_S GPIO_SW_N GPIO_SW_W GPIO_SW_C GPIO_LED_0 GPIO_LED_1 GPIO_LED_2 GPIO_LED_3 GPIO_LED_4 GPIO_LED_5 GPIO_LED_6 GPIO_LED_7 GPIO_DIP_SW7 CLK_74_25_N CLK_74_25_P CPU_RESET GPIO_DIP_SW6 GPIO_DIP_SW5 GPIO_DIP_SW4 GPIO_DIP_SW3 GPIO_DIP_SW2 GPIO_DIP_SW1 GPIO_DIP_SW0 VCC3V3 AF14 VCCO_44_AF14 AJ13 VCCO_44_AJ13 U1 SOC_1156_1MM_IRON D C B A CLK_74_25_P 1 R430 100 1/10W 1% 2 CLK_74_25_N Zynq Banks 44 TITLE: Zynq Banks 44 SCHEM, ROHS COMPLIANT HW-Z1-ZCU102_REV1_0 DATE: 09/20/2016:10:26 SHEET SIZE: B SHEET 4 OF 87 ASSY P/N: 0431959 PCB P/N: 1280868 SCH P/N: 0381701 TEST P/N: TSS0179 VER: REV: DRAWN BY: 1.0 01 BF 4 3 2 1

D C B A 4 3 2 1 SOC_DA7_FFVB1156_IRONWOOD SOC_DA7_FFVB1156_IRONWOOD BANK 47 XCZU9FFVB1156 IO_L12N_AD0N_47_A20 IO_L12P_AD0P_47_B20 IO_L11N_AD1N_47_A22 IO_L11P_AD1P_47_A21 IO_L10N_AD2N_47_B21 IO_L10P_AD2P_47_C21 IO_L9N_AD3N_47_C22 IO_L9P_AD3P_47_D21 IO_L8N_HDGC_AD4N_47_D20 IO_L8P_HDGC_AD4P_47_E20 IO_L7N_HDGC_AD5N_47_D22 IO_L7P_HDGC_AD5P_47_E22 IO_L6N_HDGC_AD6N_47_F20 IO_L6P_HDGC_AD6P_47_G20 IO_L5N_HDGC_AD7N_47_F21 IO_L5P_HDGC_AD7P_47_G21 IO_L4N_AD8N_47_J20 IO_L4P_AD8P_47_J19 IO_L3N_AD9N_47_H21 IO_L3P_AD9P_47_J21 IO_L2N_AD10N_47_K19 IO_L2P_AD10P_47_L19 IO_L1N_AD11N_47_K20 IO_L1P_AD11P_47_L20 A20 B20 A22 A21 B21 C21 C22 D21 D20 E20 D22 E22 F20 G20 F21 G21 J20 J19 H21 J21 K19 L19 K20 L20 PMOD0_0 PMOD0_1 PMOD0_2 PMOD0_3 PMOD0_4 PMOD0_5 PMOD0_6 PMOD0_7 PMOD1_0 PMOD1_1 PMOD1_2 PMOD1_3 PMOD1_4 PMOD1_5 CLK_125_N CLK_125_P PMOD1_6 PMOD1_7 TRACEDATA2 TRACEDATA1 TRACECTL TRACEDATA0 PL_I2C1_SCL_LS PL_I2C1_SDA_LS VCC3V3 E21 VCCO_47_E21 H20 VCCO_47_H20 BANK 48 XCZU9FFVB1156 IO_L12N_AD8N_48_A18 IO_L12P_AD8P_48_A17 IO_L11N_AD9N_48_C19 IO_L11P_AD9P_48_C18 IO_L10N_AD10N_48_B19 IO_L10P_AD10P_48_B18 IO_L9N_AD11N_48_C17 IO_L9P_AD11P_48_D17 IO_L8N_HDGC_48_E18 IO_L8P_HDGC_48_E17 IO_L7N_HDGC_48_D19 IO_L7P_HDGC_48_E19 IO_L6N_HDGC_48_F18 IO_L6P_HDGC_48_F17 IO_L5N_HDGC_48_G19 IO_L5P_HDGC_48_G18 IO_L4N_AD12N_48_K17 IO_L4P_AD12P_48_L17 IO_L3N_AD13N_48_K18 IO_L3P_AD13P_48_L18 IO_L2N_AD14N_48_H17 IO_L2P_AD14P_48_J17 IO_L1N_AD15N_48_H19 IO_L1P_AD15P_48_H18 A18 A17 C19 C18 B19 B18 C17 D17 E18 E17 D19 E19 F18 F17 G19 G18 K17 L17 K18 L18 H17 J17 H19 H18 TRACEDBGRQ TRACESRST_B TRACETDO TRACERTCK TRACETCK TRACETMS TRACETDI TRACETRST_B TRACEDATA15 TRACEDATA14 TRACEDATA13 TRACEDATA12 TRACEDATA11 TRACEDATA10 TRACEDATA9 TRACEDATA8 TRACECLKA TRACEDBGACK TRACEEXTTRIG TRACEDATA7 TRACEDATA6 TRACEDATA5 TRACEDATA4 TRACEDATA3 VCC3V3 G17 VCCO_48_G17 J18 VCCO_48_J18 U1 SOC_1156_1MM_IRON CLK_125_P U1 SOC_1156_1MM_IRON 1 R431 100 1/10W 1% 2 CLK_125_N Zynq Banks 47 48 TITLE: Zynq Banks 47 48 SCHEM, ROHS COMPLIANT HW-Z1-ZCU102_REV1_0 DATE: 09/20/2016:10:26 SHEET SIZE: B SHEET 5 OF 87 ASSY P/N: 0431959 PCB P/N: 1280868 SCH P/N: 0381701 TEST P/N: TSS0179 VER: REV: DRAWN BY: 1.0 01 BF 4 3 2 1 D C B A

D C B A 4 3 2 1 VCC3V3_BUS 1 2 R633 1 2.00K 1/16W 2 1% R632 1 2.00K 1/16W 1% 2 R631 1 2.00K 1/16W 1% 2 R630 2.00K 1/16W 1% 1 2 R894 1 DNP DNP DNP 2 R893 DNP DNP DNP SOC_DA7_FFVB1156_IRONWOOD BANK 49 XCZU9FFVB1156 IO_L12N_AD8N_49_E13 IO_L12P_AD8P_49_F13 IO_L11N_AD9N_49_D12 IO_L11P_AD9P_49_E12 IO_L10N_AD10N_49_B12 IO_L10P_AD10P_49_C12 IO_L9N_AD11N_49_A12 IO_L9P_AD11P_49_A13 IO_L8N_HDGC_49_B13 IO_L8P_HDGC_49_C13 IO_L7N_HDGC_49_B14 IO_L7P_HDGC_49_C14 IO_L6N_HDGC_49_D14 IO_L6P_HDGC_49_E14 IO_L5N_HDGC_49_D15 IO_L5P_HDGC_49_E15 IO_L4N_AD12N_49_A15 IO_L4P_AD12P_49_B15 IO_L3N_AD13N_49_A16 IO_L3P_AD13P_49_B16 IO_L2N_AD14N_49_C16 IO_L2P_AD14P_49_D16 IO_L1N_AD15N_49_F15 IO_L1P_AD15P_49_F16 E13 F13 D12 E12 B12 C12 A12 A13 B13 C13 B14 C14 D14 E14 D15 E15 A15 B15 A16 B16 C16 D16 F15 F16 UART2_TXD_O_FPGA_RXD UART2_RXD_I_FPGA_TXD UART2_RTS_O_B UART2_CTS_I_B MSP430_UCA1_TXD MSP430_UCA1_RXD SFP0_TX_DISABLE SFP1_TX_DISABLE SFP2_TX_DISABLE SFP3_TX_DISABLE SYSMON_SDA SYSMON_SCL HDMI_RX_PWR_DET HDMI_RX_HPD HDMI_RX_CEC_SINK HDMI_RX_SNK_SCL HDMI_RX_SNK_SDA HDMI_TX_EN HDMI_TX_CEC HDMI_TX_HPD HDMI_TX_SRC_SCL HDMI_TX_SRC_SDA HDMI_CTL_SCL HDMI_CTL_SDA VCC3V3 E16 VCCO_49_E16 F14 VCCO_49_F14 SOC_DA7_FFVB1156_IRONWOOD BANK 50 XCZU9FFVB1156 IO_L12N_AD8N_50_J15 IO_L12P_AD8P_50_J16 IO_L11N_AD9N_50_G16 IO_L11P_AD9P_50_H16 IO_L10N_AD10N_50_H14 IO_L10P_AD10P_50_J14 IO_L9N_AD11N_50_G14 IO_L9P_AD11P_50_G15 IO_L8N_HDGC_50_G13 IO_L8P_HDGC_50_H13 IO_L7N_HDGC_50_H12 IO_L7P_HDGC_50_J12 IO_L6N_HDGC_50_F11 IO_L6P_HDGC_50_F12 IO_L5N_HDGC_50_G11 IO_L5P_HDGC_50_H11 IO_L4N_AD12N_50_D10 IO_L4P_AD12P_50_D11 IO_L3N_AD13N_50_E10 IO_L3P_AD13P_50_F10 IO_L2N_AD14N_50_G10 IO_L2P_AD14P_50_H10 IO_L1N_AD15N_50_J10 IO_L1P_AD15P_50_J11 J15 J16 G16 H16 H14 J14 G14 G15 G13 H13 H12 J12 F11 F12 G11 H11 D10 D11 E10 F10 G10 H10 J10 J11 VCC3V3 G12 VCCO_50_G12 J13 VCCO_50_J13 U1 SOC_1156_1MM_IRON U1 SOC_1156_1MM_IRON L12N_AD8N_50_N L12P_AD8P_50_P L11N_AD9N_50_N L11P_AD9P_50_P L10N_AD10N_50_N L10P_AD10P_50_P L9N_AD11N_50_N L9P_AD11P_50_P L8N_HDGC_50_N L8P_HDGC_50_P HDMI_SI5324_LOL HDMI_SI5324_RST HDMI_SI5324_INT_ALM NC NC NC NC MSP430_GPIO_PL_0 MSP430_GPIO_PL_1 MSP430_GPIO_PL_2 MSP430_GPIO_PL_3 SFP_SI5328_INT_ALM PL_I2C0_SCL_LS PL_I2C0_SDA_LS 4 3 2 1 Zynq Banks 49 50 TITLE: Zynq Banks 49 50 SCHEM, ROHS COMPLIANT HW-Z1-ZCU102_REV1_0 DATE: 09/20/2016:10:26 SHEET SIZE: B SHEET 6 OF 87 ASSY P/N: 0431959 PCB P/N: 1280868 SCH P/N: 0381701 TEST P/N: TSS0179 VER: REV: DRAWN BY: 1.0 01 BF D C B A

4 Layout: Place resistor and capacitor for VREF Underneath the FPGA via array right next to the via C3 0.1UF 25V 1 2 GND 3 VCC1V2 1 2 1 2 R769 1.00K 1/16W 1% R770 1.00K 1/16W 1% GND C919 0.1UF 25V 1 2 GND 1 R192 49.9 1/10W 1% SOC_DA7_FFVB1156_IRONWOOD 2 BANK 64 XCZU9FFVB1156 IO_T3U_N12_64_AP1 IO_L24N_T3U_N11_64_AK2 IO_L24P_T3U_N10_64_AK3 IO_L23N_T3U_N9_64_AL1 IO_L23P_T3U_N8_64_AK1 IO_L22N_T3U_N7_DBC_AD0N_64_AL2 IO_L22P_T3U_N6_DBC_AD0P_64_AL3 IO_L21N_T3L_N5_AD8N_64_AN1 IO_L21P_T3L_N4_AD8P_64_AM1 IO_L20N_T3L_N3_AD1N_64_AP3 IO_L20P_T3L_N2_AD1P_64_AN3 IO_L19N_T3L_N1_DBC_AD9N_64_AP2 IO_L19P_T3L_N0_DBC_AD9P_64_AN2 IO_T2U_N12_64_AM3 IO_L18N_T2U_N11_AD2N_64_AK4 IO_L18P_T2U_N10_AD2P_64_AK5 IO_L17N_T2U_N9_AD10N_64_AN4 IO_L17P_T2U_N8_AD10P_64_AM4 IO_L16N_T2U_N7_QBC_AD3N_64_AP6 IO_L16P_T2U_N6_QBC_AD3P_64_AN6 IO_L15N_T2L_N5_AD11N_64_AP4 IO_L15P_T2L_N4_AD11P_64_AP5 IO_L14N_T2L_N3_GC_64_AM5 IO_L14P_T2L_N2_GC_64_AM6 IO_L13N_T2L_N1_GC_QBC_64_AL5 IO_L13P_T2L_N0_GC_QBC_64_AL6 IO_T1U_N12_64_AJ7 IO_L12N_T1U_N11_GC_64_AL7 IO_L12P_T1U_N10_GC_64_AL8 IO_L11N_T1U_N9_GC_64_AK7 IO_L11P_T1U_N8_GC_64_AK8 IO_L10N_T1U_N7_QBC_AD4N_64_AP7 IO_L10P_T1U_N6_QBC_AD4P_64_AN7 IO_L9N_T1L_N5_AD12N_64_AK9 IO_L9P_T1L_N4_AD12P_64_AJ9 IO_L8N_T1L_N3_AD5N_64_AM8 IO_L8P_T1L_N2_AD5P_64_AM9 IO_L7N_T1L_N1_QBC_AD13N_64_AP8 IO_L7P_T1L_N0_QBC_AD13P_64_AN8 IO_T0U_N12_VRP_64_AN11 IO_L6N_T0U_N11_AD6N_64_AK10 IO_L6P_T0U_N10_AD6P_64_AJ10 IO_L5N_T0U_N9_AD14N_64_AP9 IO_L5P_T0U_N8_AD14P_64_AN9 IO_L4N_T0U_N7_DBC_AD7N_64_AP10 IO_L4P_T0U_N6_DBC_AD7P_64_AP11 IO_L3N_T0L_N5_AD15N_64_AM10 IO_L3P_T0L_N4_AD15P_64_AL10 IO_L2N_T0L_N3_64_AM11 IO_L2P_T0L_N2_64_AL11 IO_L1N_T0L_N1_DBC_64_AK12 IO_L1P_T0L_N0_DBC_64_AJ12 VREF_64_AJ11 AP1 AK2 AK3 AL1 AK1 AL2 AL3 AN1 AM1 AP3 AN3 AP2 AN2 AM3 AK4 AK5 AN4 AM4 AP6 AN6 AP4 AP5 AM5 AM6 AL5 AL6 AJ7 AL7 AL8 AK7 AK8 AP7 AN7 AK9 AJ9 AM8 AM9 AP8 AN8 AN11 AK10 AJ10 AP9 AN9 AP10 AP11 AM10 AL10 AM11 AL11 AK12 AJ12 AJ11 VCC1V2 AJ8 VCCO_64_AJ8 AK11 VCCO_64_AK11 AL9 VCCO_64_AL9 DDR4_PAR DDR4_DQ8 DDR4_DQ9 DDR4_DQ10 DDR4_DQ11 DDR4_DQS1_C DDR4_DQS1_T DDR4_DQ12 DDR4_DQ13 DDR4_DQ14 DDR4_DQ15 DDR4_CS_B DDR4_DM1 DDR4_CKE DDR4_DQ0 DDR4_DQ1 DDR4_DQ2 DDR4_DQ3 DDR4_DQS0_C DDR4_DQS0_T DDR4_DQ4 DDR4_DQ5 DDR4_DQ6 DDR4_DQ7 DDR4_A15_CAS_B DDR4_DM0 DDR4_A14_WE_B USER_SI570_N USER_SI570_P DDR4_BG0 DDR4_ACT_B DDR4_CK_C DDR4_CK_T DDR4_ODT DDR4_A16_RAS_B DDR4_A0 DDR4_A1 DDR4_A2 DDR4_A3 VRP_64 DDR4_A4 DDR4_A5 DDR4_A6 DDR4_A7 DDR4_A8 DDR4_A9 DDR4_A10 DDR4_A11 DDR4_A12 DDR4_A13 DDR4_BA0 DDR4_BA1 VADJ_FMC U1 SOC_1156_1MM_IRON VRP_64 1 2 R345 240 1/10W 1% GND USER_SI570_P 1 2 R212 100 1/10W 1% USER_SI570_N D C B A 2 1 FMC_HPC1_VREF_A_M2C 1 2 R747 1 DNP DNP DNP 2 C968 DNP DNP GND NC NC FMC_HPC1_LA09_N FMC_HPC1_LA09_P FMC_HPC1_LA02_N FMC_HPC1_LA02_P FMC_HPC1_LA03_N FMC_HPC1_LA03_P FMC_HPC1_LA04_N FMC_HPC1_LA04_P FMC_HPC1_LA05_N FMC_HPC1_LA05_P FMC_HPC1_LA06_N FMC_HPC1_LA06_P FMC_HPC1_LA07_N FMC_HPC1_LA07_P FMC_HPC1_LA08_N FMC_HPC1_LA08_P FMC_HPC1_LA01_CC_N FMC_HPC1_LA01_CC_P FMC_HPC1_LA10_N FMC_HPC1_LA10_P HDMI_REC_CLOCK_C_N HDMI_REC_CLOCK_C_P FMC_HPC1_LA00_CC_N FMC_HPC1_LA00_CC_P DDR4_RESET_B_LS FMC_HPC1_CLK0_M2C_N FMC_HPC1_CLK0_M2C_P HDMI_TX_LVDS_OUT_N HDMI_TX_LVDS_OUT_P FMC_HPC1_LA11_N FMC_HPC1_LA11_P FMC_HPC1_LA12_N FMC_HPC1_LA12_P FMC_HPC1_LA13_N FMC_HPC1_LA13_P FMC_HPC1_LA14_N FMC_HPC1_LA14_P VRP_65 FMC_HPC1_LA15_N FMC_HPC1_LA15_P FMC_HPC1_LA16_N FMC_HPC1_LA16_P FMC_HPC1_LA22_N FMC_HPC1_LA22_P FMC_HPC1_LA23_N FMC_HPC1_LA23_P FMC_HPC1_LA24_N FMC_HPC1_LA24_P FMC_HPC1_LA25_N FMC_HPC1_LA25_P AG1 AE1 AE2 AD1 AD2 AJ1 AH1 AF1 AF2 AH3 AG3 AJ2 AH2 AD5 AE4 AD4 AF3 AE3 AJ5 AJ6 AJ4 AH4 AG4 AG5 AF5 AE5 AH9 AF7 AE7 AG6 AF6 AF8 AE8 AD6 AD7 AH8 AG8 AH6 AH7 AD9 AE9 AD10 AG9 AG10 AG11 AF11 AF12 AE12 AH11 AH12 AF10 AE10 AD11 SOC_DA7_FFVB1156_IRONWOOD BANK 65 XCZU9FFVB1156 IO_T3U_N12_65_AG1 IO_L24N_T3U_N11_PERSTN0_65_AE1 IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65_AE2 IO_L23N_T3U_N9_65_AD1 IO_L23P_T3U_N8_I2C_SCLK_65_AD2 IO_L22N_T3U_N7_DBC_AD0N_65_AJ1 IO_L22P_T3U_N6_DBC_AD0P_65_AH1 IO_L21N_T3L_N5_AD8N_65_AF1 IO_L21P_T3L_N4_AD8P_65_AF2 IO_L20N_T3L_N3_AD1N_65_AH3 IO_L20P_T3L_N2_AD1P_65_AG3 IO_L19N_T3L_N1_DBC_AD9N_65_AJ2 IO_L19P_T3L_N0_DBC_AD9P_65_AH2 IO_T2U_N12_65_AD5 IO_L18N_T2U_N11_AD2N_65_AE4 IO_L18P_T2U_N10_AD2P_65_AD4 IO_L17N_T2U_N9_AD10N_65_AF3 IO_L17P_T2U_N8_AD10P_65_AE3 IO_L16N_T2U_N7_QBC_AD3N_65_AJ5 IO_L16P_T2U_N6_QBC_AD3P_65_AJ6 IO_L15N_T2L_N5_AD11N_65_AJ4 IO_L15P_T2L_N4_AD11P_65_AH4 IO_L14N_T2L_N3_GC_65_AG4 IO_L14P_T2L_N2_GC_65_AG5 IO_L13N_T2L_N1_GC_QBC_65_AF5 IO_L13P_T2L_N0_GC_QBC_65_AE5 IO_T1U_N12_65_AH9 IO_L12N_T1U_N11_GC_65_AF7 IO_L12P_T1U_N10_GC_65_AE7 IO_L11N_T1U_N9_GC_65_AG6 IO_L11P_T1U_N8_GC_65_AF6 IO_L10N_T1U_N7_QBC_AD4N_65_AF8 IO_L10P_T1U_N6_QBC_AD4P_65_AE8 IO_L9N_T1L_N5_AD12N_65_AD6 IO_L9P_T1L_N4_AD12P_65_AD7 IO_L8N_T1L_N3_AD5N_65_AH8 IO_L8P_T1L_N2_AD5P_65_AG8 IO_L7N_T1L_N1_QBC_AD13N_65_AH6 IO_L7P_T1L_N0_QBC_AD13P_65_AH7 IO_T0U_N12_VRP_65_AD9 IO_L6N_T0U_N11_AD6N_65_AE9 IO_L6P_T0U_N10_AD6P_65_AD10 IO_L5N_T0U_N9_AD14N_65_AG9 IO_L5P_T0U_N8_AD14P_65_AG10 IO_L4N_T0U_N7_DBC_AD7N_65_AG11 IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65_AF11 IO_L3N_T0L_N5_AD15N_65_AF12 IO_L3P_T0L_N4_AD15P_65_AE12 IO_L2N_T0L_N3_65_AH11 IO_L2P_T0L_N2_65_AH12 IO_L1N_T0L_N1_DBC_65_AF10 IO_L1P_T0L_N0_DBC_65_AE10 VREF_65_AD11 AD8 VCCO_65_AD8 AF9 VCCO_65_AF9 AG7 VCCO_65_AG7 U1 SOC_1156_1MM_IRON VRP_65 1 R346 240 1/10W 1% 2 GND D C B A VADJ_FMC_BUS VCC1V2_BUS C369 0.1UF 25V 1 2 GND DDR4_RESET_B_LS R667 1.00K 1 2 1/16W 1% 1 2 C368 0.1UF 25V GND DDR4_RESET_B SN74AVC1T45 6 4 5 VCCB B DIR VCCA A GND 1 3 2 U113 SC70_6 GND Zynq Banks 64 65 TITLE: Zynq Banks 64 65 SCHEM, ROHS COMPLIANT HW-Z1-ZCU102_REV1_0 DATE: 09/20/2016:10:26 SHEET SIZE: B SHEET 7 OF 87 ASSY P/N: 0431959 PCB P/N: 1280868 SCH P/N: 0381701 TEST P/N: TSS0179 VER: REV: DRAWN BY: 1.0 01 BF 4 3 2 1

D C B A 4 3 2 1 SOC_DA7_FFVB1156_IRONWOOD BANK 66 XCZU9FFVB1156 IO_T3U_N12_66_AB1 IO_L24N_T3U_N11_66_W1 IO_L24P_T3U_N10_66_W2 IO_L23N_T3U_N9_66_V1 IO_L23P_T3U_N8_66_V2 IO_L22N_T3U_N7_DBC_AD0N_66_Y1 IO_L22P_T3U_N6_DBC_AD0P_66_Y2 IO_L21N_T3L_N5_AD8N_66_AA1 IO_L21P_T3L_N4_AD8P_66_AA2 IO_L20N_T3L_N3_AD1N_66_AC3 IO_L20P_T3L_N2_AD1P_66_AB3 IO_L19N_T3L_N1_DBC_AD9N_66_AC1 IO_L19P_T3L_N0_DBC_AD9P_66_AC2 IO_T2U_N12_66_AA3 IO_L18N_T2U_N11_AD2N_66_U4 IO_L18P_T2U_N10_AD2P_66_U5 IO_L17N_T2U_N9_AD10N_66_V3 IO_L17P_T2U_N8_AD10P_66_V4 IO_L16N_T2U_N7_QBC_AD3N_66_AC4 IO_L16P_T2U_N6_QBC_AD3P_66_AB4 IO_L15N_T2L_N5_AD11N_66_W4 IO_L15P_T2L_N4_AD11P_66_W5 IO_L14N_T2L_N3_GC_66_AA5 IO_L14P_T2L_N2_GC_66_Y5 IO_L13N_T2L_N1_GC_QBC_66_Y3 IO_L13P_T2L_N0_GC_QBC_66_Y4 IO_T1U_N12_66_AA8 IO_L12N_T1U_N11_GC_66_AA6 IO_L12P_T1U_N10_GC_66_AA7 IO_L11N_T1U_N9_GC_66_Y7 IO_L11P_T1U_N8_GC_66_Y8 IO_L10N_T1U_N7_QBC_AD4N_66_AB5 IO_L10P_T1U_N6_QBC_AD4P_66_AB6 IO_L9N_T1L_N5_AD12N_66_W6 IO_L9P_T1L_N4_AD12P_66_W7 IO_L8N_T1L_N3_AD5N_66_AC8 IO_L8P_T1L_N2_AD5P_66_AB8 IO_L7N_T1L_N1_QBC_AD13N_66_AC6 IO_L7P_T1L_N0_QBC_AD13P_66_AC7 IO_T0U_N12_VRP_66_W9 IO_L6N_T0U_N11_AD6N_66_Y9 IO_L6P_T0U_N10_AD6P_66_Y10 IO_L5N_T0U_N9_AD14N_66_AA12 IO_L5P_T0U_N8_AD14P_66_Y12 IO_L4N_T0U_N7_DBC_AD7N_66_AC9 IO_L4P_T0U_N6_DBC_AD7P_66_AB9 IO_L3N_T0L_N5_AD15N_66_AA10 IO_L3P_T0L_N4_AD15P_66_AA11 IO_L2N_T0L_N3_66_AB10 IO_L2P_T0L_N2_66_AB11 IO_L1N_T0L_N1_DBC_66_AC11 IO_L1P_T0L_N0_DBC_66_AC12 VREF_66_AD12 AB1 W1 W2 V1 V2 Y1 Y2 AA1 AA2 AC3 AB3 AC1 AC2 AA3 U4 U5 V3 V4 AC4 AB4 W4 W5 AA5 Y5 Y3 Y4 AA8 AA6 AA7 Y7 Y8 AB5 AB6 W6 W7 AC8 AB8 AC6 AC7 W9 Y9 Y10 AA12 Y12 AC9 AB9 AA10 AA11 AB10 AB11 AC11 AC12 AD12 VADJ_FMC AA9 VCCO_66_AA9 W8 VCCO_66_W8 Y11 VCCO_66_Y11 FMC_HPC0_VREF_A_M2C 1 2 R748 1 DNP DNP DNP 2 C969 DNP DNP DNP GND NC NC NC NC NC NC FMC_HPC0_LA09_N FMC_HPC0_LA09_P FMC_HPC0_LA02_N FMC_HPC0_LA02_P FMC_HPC0_LA03_N FMC_HPC0_LA03_P FMC_HPC0_LA04_N FMC_HPC0_LA04_P FMC_HPC0_LA05_N FMC_HPC0_LA05_P FMC_HPC0_LA06_N FMC_HPC0_LA06_P FMC_HPC0_LA07_N FMC_HPC0_LA07_P FMC_HPC0_LA08_N FMC_HPC0_LA08_P FMC_HPC0_LA01_CC_N FMC_HPC0_LA01_CC_P FMC_HPC0_LA10_N FMC_HPC0_LA10_P FMC_HPC1_LA17_CC_N FMC_HPC1_LA17_CC_P FMC_HPC0_LA00_CC_N FMC_HPC0_LA00_CC_P FMC_HPC0_CLK0_M2C_N FMC_HPC0_CLK0_M2C_P FMC_HPC1_LA18_CC_N FMC_HPC1_LA18_CC_P FMC_HPC0_LA11_N FMC_HPC0_LA11_P FMC_HPC0_LA12_N FMC_HPC0_LA12_P FMC_HPC0_LA13_N FMC_HPC0_LA13_P FMC_HPC0_LA14_N FMC_HPC0_LA14_P FMC_HPC0_LA15_N FMC_HPC0_LA15_P FMC_HPC0_LA16_N FMC_HPC0_LA16_P FMC_HPC1_LA19_N FMC_HPC1_LA19_P FMC_HPC1_LA20_N FMC_HPC1_LA20_P FMC_HPC1_LA21_N FMC_HPC1_LA21_P SOC_DA7_FFVB1156_IRONWOOD BANK 67 XCZU9FFVB1156 IO_T3U_N12_67_K14 IO_L24N_T3U_N11_67_K15 IO_L24P_T3U_N10_67_L15 IO_L23N_T3U_N9_67_K13 IO_L23P_T3U_N8_67_L13 IO_L22N_T3U_N7_DBC_AD0N_67_M13 IO_L22P_T3U_N6_DBC_AD0P_67_N13 IO_L21N_T3L_N5_AD8N_67_N12 IO_L21P_T3L_N4_AD8P_67_P12 IO_L20N_T3L_N3_AD1N_67_M14 IO_L20P_T3L_N2_AD1P_67_M15 IO_L19N_T3L_N1_DBC_AD9N_67_K16 IO_L19P_T3L_N0_DBC_AD9P_67_L16 IO_T2U_N12_67_K10 IO_L18N_T2U_N11_AD2N_67_K12 IO_L18P_T2U_N10_AD2P_67_L12 IO_L17N_T2U_N9_AD10N_67_L11 IO_L17P_T2U_N8_AD10P_67_M11 IO_L16N_T2U_N7_QBC_AD3N_67_N8 IO_L16P_T2U_N6_QBC_AD3P_67_N9 IO_L15N_T2L_N5_AD11N_67_L10 IO_L15P_T2L_N4_AD11P_67_M10 IO_L14N_T2L_N3_GC_67_P9 IO_L14P_T2L_N2_GC_67_P10 IO_L13N_T2L_N1_GC_QBC_67_N11 IO_L13P_T2L_N0_GC_QBC_67_P11 IO_T1U_N12_67_V9 IO_L12N_T1U_N11_GC_67_R8 IO_L12P_T1U_N10_GC_67_T8 IO_L11N_T1U_N9_GC_67_R9 IO_L11P_T1U_N8_GC_67_R10 IO_L10N_T1U_N7_QBC_AD4N_67_T6 IO_L10P_T1U_N6_QBC_AD4P_67_T7 IO_L9N_T1L_N5_AD12N_67_U8 IO_L9P_T1L_N4_AD12P_67_U9 IO_L8N_T1L_N3_AD5N_67_U6 IO_L8P_T1L_N2_AD5P_67_V6 IO_L7N_T1L_N1_QBC_AD13N_67_V7 IO_L7P_T1L_N0_QBC_AD13P_67_V8 IO_T0U_N12_VRP_67_W10 IO_L6N_T0U_N11_AD6N_67_T11 IO_L6P_T0U_N10_AD6P_67_U11 IO_L5N_T0U_N9_AD14N_67_V11 IO_L5P_T0U_N8_AD14P_67_V12 IO_L4N_T0U_N7_DBC_AD7N_67_R12 IO_L4P_T0U_N6_DBC_AD7P_67_T12 IO_L3N_T0L_N5_AD15N_67_T10 IO_L3P_T0L_N4_AD15P_67_U10 IO_L2N_T0L_N3_67_R13 IO_L2P_T0L_N2_67_T13 IO_L1N_T0L_N1_DBC_67_W11 IO_L1P_T0L_N0_DBC_67_W12 VREF_67_N14 K14 K15 L15 K13 L13 M13 N13 N12 P12 M14 M15 K16 L16 K10 K12 L12 L11 M11 N8 N9 L10 M10 P9 P10 N11 P11 V9 R8 T8 R9 R10 T6 T7 U8 U9 U6 V6 V7 V8 W10 T11 U11 V11 V12 R12 T12 T10 U10 R13 T13 W11 W12 N14 VADJ_FMC P8 VCCO_67_P8 T9 VCCO_67_T9 U7 VCCO_67_U7 FMC_HPC0_VREF_A_M2C 1 2 R749 1 DNP DNP DNP 2 C970 DNP DNP DNP GND NC NC NC NC FMC_HPC0_LA26_N FMC_HPC0_LA26_P FMC_HPC0_LA19_N FMC_HPC0_LA19_P FMC_HPC0_LA20_N FMC_HPC0_LA20_P FMC_HPC0_LA21_N FMC_HPC0_LA21_P FMC_HPC0_LA22_N FMC_HPC0_LA22_P FMC_HPC0_LA23_N FMC_HPC0_LA23_P FMC_HPC0_LA24_N FMC_HPC0_LA24_P FMC_HPC0_LA25_N FMC_HPC0_LA25_P FMC_HPC0_LA18_CC_N FMC_HPC0_LA18_CC_P FMC_HPC0_LA27_N FMC_HPC0_LA27_P FMC_HPC1_CLK1_M2C_N FMC_HPC1_CLK1_M2C_P FMC_HPC0_LA17_CC_N FMC_HPC0_LA17_CC_P FMC_HPC0_CLK1_M2C_N FMC_HPC0_CLK1_M2C_P SFP_REC_CLOCK_C_N SFP_REC_CLOCK_C_P FMC_HPC0_LA28_N FMC_HPC0_LA28_P FMC_HPC0_LA29_N FMC_HPC0_LA29_P FMC_HPC0_LA30_N FMC_HPC0_LA30_P FMC_HPC0_LA31_N FMC_HPC0_LA31_P FMC_HPC0_LA32_N FMC_HPC0_LA32_P FMC_HPC0_LA33_N FMC_HPC0_LA33_P FMC_HPC1_LA26_N FMC_HPC1_LA26_P FMC_HPC1_LA27_N FMC_HPC1_LA27_P FMC_HPC1_LA28_N FMC_HPC1_LA28_P FMC_HPC1_LA29_N FMC_HPC1_LA29_P U1 SOC_1156_1MM_IRON U1 SOC_1156_1MM_IRON 4 3 2 1 Zynq Banks 66 67 TITLE: Zynq Banks 66 67 SCHEM, ROHS COMPLIANT HW-Z1-ZCU102_REV1_0 DATE: 09/20/2016:10:45 SHEET SIZE: B SHEET 8 OF 87 ASSY P/N: 0431959 PCB P/N: 1280868 SCH P/N: 0381701 TEST P/N: TSS0179 VER: REV: DRAWN BY: 1.0 01 BF D C B A

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