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IEEE Std 1149.1-2013 .pdf

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    IEEE Std 1149.1-2013 Front Cover
    Notice to users
    Laws and regulations
    Copyrights
    Updating of IEEE documents
    Errata
    Patents
    Participants
    Introduction
    History of the development of this standard
    Changes introduced by this revision
    Contents
    Figures
    Tables
    Important Notice
    1. Overview
    1.1 Scope
    1.2 Purpose
    1.2.1 Overview of the operation of this standard
    1.2.2 Use of this standard to test an assembled product
    1.2.3 What is a boundary scan?
    1.2.4 Use of this standard to achieve other test goals
    1.3 Document outline
    1.3.1 Specifications
    1.3.2 Descriptions
    1.4 Text conventions
    1.5 Logic diagram conventions
    2. Normative references
    3. Definitions, abbreviations, acronyms, and special terms
    3.1 Definitions
    3.2 Abbreviations and acronyms
    3.3 Special terms
    4. Test access port (TAP)
    4.1 Connections that form the TAP
    4.1.1 Specifications
    Rules
    4.1.2 Description
    4.2 Test clock input (TCK)
    4.2.1 Specifications
    Rules
    Recommendations
    Permissions
    4.2.2 Description
    4.3 Test mode select (TMS) input
    4.3.1 Specifications
    Rules
    Recommendations
    4.3.2 Description
    4.4 Test data input (TDI)
    4.4.1 Specifications
    Rules
    4.4.2 Description
    4.5 Test data output (TDO)
    4.5.1 Specifications
    Rules
    4.5.2 Description
    4.6 Test reset input (TRST*)
    4.6.1 Specifications
    Rules
    Recommendations
    4.6.2 Description
    4.7 Interconnection of components compatible with this standard
    4.7.1 Specifications
    Permissions
    4.7.2 Description
    4.8 Subordination of this standard within a higher level test strategy
    4.8.1 Specifications
    Rules
    Recommendations
    Permissions
    4.8.2 Description
    5. Test logic architecture
    5.1 Test logic design
    5.1.1 Specifications
    Rules
    Permissions
    5.1.2 Description
    5.2 Test logic realization
    5.2.1 Specifications
    Rules
    5.2.2 Description
    6. Test logic controllers
    6.1 TAP controller
    6.1.1 TAP controller state diagram
    6.1.1.1 Specifications
    Rules
    6.1.1.2 Description
    Test-Logic-Reset
    Run-Test/Idle
    Select-DR-Scan
    Select-IR-Scan
    Capture-DR
    Shift-DR
    Exit1-DR
    Pause-DR
    Exit2-DR
    Update-DR
    Capture-IR
    Shift-IR
    Exit1-IR
    Pause-IR
    Exit2-IR
    Update-IR
    General
    6.1.2 TAP controller operation
    6.1.2.1 Specifications
    Rules
    6.1.2.2 Description
    6.1.3 TAP controller initialization
    6.1.3.1 Specifications
    Rules
    6.1.3.2 Description
    6.2 Test mode persistence (TMP) controller
    6.2.1 TMP controller state diagram
    6.2.1.1 Specifications
    Rules
    Recommendations
    6.2.1.2 Description
    6.2.2 TMP controller operation
    6.2.2.1 Specifications
    Rules
    Permissions
    6.2.2.2 Description
    6.2.3 TMP controller initialization
    6.2.3.1 Specifications
    Rules
    6.2.3.2 Description
    7. Instruction register
    7.1 Design and construction of the instruction register
    7.1.1 Specifications
    Rules
    Recommendations
    Permissions
    7.1.2 Description
    7.2 Instruction register operation
    7.2.1 Specifications
    Rules
    7.2.2 Description
    8. Instructions
    8.1 Response of the test logic to instructions
    8.1.1 Specifications
    Rules
    Recommendations
    Permissions
    8.1.2 Description
    8.2 Public instructions
    8.2.1 Specifications
    Rules
    Recommendations
    Permissions
    8.2.2 Description
    8.3 Private instructions
    8.3.1 Specifications
    Rules
    Permissions
    8.3.2 Description
    8.4 BYPASS instruction
    8.4.1 Specifications
    Rules
    Permissions
    Recommendations
    8.4.2 Description
    8.5 Boundary-scan register instructions
    8.5.1 Overview of the operation of the boundary-scan register
    8.5.2 Specifications for boundary-scan register instructions
    8.6 SAMPLE instruction
    8.6.1 Specifications
    Rules
    Recommendations
    Permissions
    8.6.2 Description
    8.7 PRELOAD instruction
    8.7.1 Specifications
    Rules
    Recommendations
    Permissions
    8.7.2 Description
    8.8 EXTEST instruction
    8.8.1 Specifications
    Rules
    Recommendations
    Permissions
    8.8.2 Description
    8.9 INTEST instruction
    8.9.1 Specifications
    Rules
    Recommendations
    Permissions
    8.9.2 Description
    8.10 RUNBIST instruction
    8.10.1 Specifications
    Rules
    Recommendations
    Permissions
    8.10.2 Description
    8.11 CLAMP instruction
    8.11.1 Specifications
    Rules
    Permissions
    8.11.2 Description
    8.12 Device identification register instructions
    8.13 IDCODE instruction
    8.13.1 Specifications
    Rules
    Permissions
    8.13.2 Description
    8.14 USERCODE instruction
    8.14.1 Specifications
    Rules
    Permissions
    8.14.2 Description
    8.15 ECIDCODE instruction
    8.15.1 Specifications
    Rules
    Recommendations
    Permissions
    8.15.2 Description
    8.16 HIGHZ instruction
    8.16.1 Specifications
    Rules
    Permissions
    8.16.2 Description
    8.17 Component initialization instructions and procedures
    8.17.1 Specifications
    Rules
    Permissions
    Recommendations
    8.17.2 Description
    8.18 INIT_SETUP and INIT_SETUP_CLAMP instructions
    8.18.1 Specifications
    Rules
    Permissions
    8.18.2 Description
    8.19 INIT_RUN instruction
    8.19.1 Specifications
    Rules
    Recommendations
    Permissions
    8.19.2 Description
    8.20 CLAMP_HOLD, CLAMP_RELEASE, and TMP_STATUS instructions
    8.20.1 Specifications
    Rules
    Permissions
    8.20.2 Description
    8.21 IC_RESET instruction
    8.21.1 Specifications
    Rules
    Recommendations
    Permissions
    8.21.2 Description
    9. Test data registers
    9.1 Provision of test data registers
    9.1.1 Specifications
    Rules
    Permissions
    Recommendations
    9.1.2 Description
    Bypass register
    Boundary-scan register
    9.1.2.1 Optional standard test data registers
    Device identification register
    Electronic chip identification register
    Initialization data register
    Initialization status register
    TMP status register
    Reset selection register
    9.1.2.2 Design-specific test data registers
    9.2 Design and construction of test data registers
    9.2.1 Specifications
    Rules
    Permissions
    Recommendations
    9.2.2 Description
    9.2.3 TAP-to-TDR interface
    9.2.4 Test data register cell design examples
    Gated-clock example TDR bit
    Ungated-clock example TDR bits
    9.3 Operation of test data registers
    9.3.1 Specifications
    Rules
    Permissions
    Recommendations
    9.3.2 Description
    9.4 Design and control of test data register segments
    9.4.1 Specifications
    Rules
    Permissions
    Recommendations
    9.4.2 Description
    Excludable segments
    Selectable segments
    10. Bypass register
    10.1 Design and operation of the bypass register
    10.1.1 Specifications
    Rules
    10.1.2 Description
    11. Boundary-scan register
    11.1 Introduction
    11.1.1 Approach
    11.1.2 Signal paths to the on-chip system logic
    11.1.3 Boundary-scan register cell
    11.2 Register design
    11.2.1 Specifications
    Rules
    Permissions
    11.2.2 Description
    11.3 Register operation
    11.3.1 Specifications
    Rules
    Permissions
    11.3.2 Description
    11.4 General rules regarding cell provision
    11.4.1 Specification
    Rules
    Permissions
    11.4.2 Description
    11.5 Provision and operation of cells at system logic inputs
    11.5.1 Specifications
    Rules
    Permissions
    11.5.2 Description
    11.6 Provision and operation of cells at system logic outputs
    11.6.1 Specifications
    Rules
    Recommendations
    Permissions
    11.6.2 Description
    11.7 Provision and operation of cells at bidirectional system logic pins
    11.7.1 Specifications
    Rules
    11.7.2 Description
    11.8 Redundant cells
    11.8.1 Specifications
    Rules
    Permissions
    Recommendations
    11.8.2 Description
    11.9 Special cases
    11.9.1 Specifications
    Permissions
    11.9.2 Description
    12. Device identification register
    12.1 Design and operation of the device identification register
    12.1.1 Specifications
    Rules
    12.1.2 Description
    12.2 Manufacturer identity code
    12.2.1 Specifications
    Rules
    Recommendations
    12.2.2 Description
    12.3 Part-number code
    12.3.1 Specifications
    Rules
    Recommendations
    Permissions
    12.3.2 Description
    12.4 Version code
    12.4.1 Specifications
    Rules
    Recommendations
    Permissions
    12.4.2 Description
    13. Electronic chip identification (ECID) register
    13.1 Design and operation of the ECID register
    13.1.1 Specifications
    Rules
    Permissions
    13.1.2 Description
    14. Initialization data register
    14.1 Design and operation of the initialization data register
    14.1.1 Specifications
    Rules
    Recommendations
    Permissions
    14.1.2 Description
    15. Initialization status register
    15.1 Design and operation of the initialization status register
    15.1.1 Specifications
    Rules
    Recommendations
    15.1.2 Description
    16. TMP status register
    16.1 Design and operation of the TMP status register
    16.1.1 Specifications
    Rules
    16.1.2 Description
    17. Reset selection register
    17.1 Design and operation of the reset selection register
    17.1.1 Specifications
    Rules
    Permissions
    17.1.2 Description
    18. Conformance and documentation requirements
    18.1 Claiming conformance to this standard
    18.1.1 Specifications
    Rules
    Recommendations
    Permissions
    18.1.2 Description
    18.2 Prime and second source components
    18.2.1 Specifications
    Rules
    18.2.2 Description
    18.3 Documentation requirements
    18.3.1 Specifications
    Rules
    18.3.2 Description
    Annex A (informative) Example implementation using level-sensitive design techniques
    Annex B (normative) Boundary Scan Description Language (BSDL)
    B.1 General information
    B.1.1 Document outline
    B.1.2 Conventions
    B.1.3 BSDL history
    B.2 Purpose of BSDL
    B.3 Scope of BSDL
    B.4 Relationship of BSDL to VHDL
    B.4.1 Specifications
    Rules
    Permissions
    B.5 Lexical elements of BSDL
    B.5.1 Character set
    B.5.1.1 Specifications
    Rules
    B.5.2 BSDL reserved words
    B.5.2.1 Specifications
    Rules
    B.5.3 VHDL reserved and predefined words
    B.5.3.1 Specifications
    Rules
    B.5.4 Identifiers
    B.5.4.1 Specifications
    Rules
    B.5.5 Numeric literals
    B.5.5.1 Specifications
    Rules
    B.5.5.2 Description
    B.5.6 Strings
    B.5.6.1 Specifications
    Rules
    B.5.6.2 Description
    B.5.7 Information tag
    B.5.7.1 Specifications
    Rules
    B.5.7.2 Description
    B.5.8 Comments
    B.5.8.1 Specifications
    Rules
    B.6 Syntax definition
    B.6.1 BNF conventions
    B.6.2 Commonly used syntactic elements
    B.6.2.1 Specifications
    Syntax
    Rules
    B.7 Components of a BSDL description
    B.7.1 Specifications
    Rules
    Permissions
    B.7.2 Description
    B.8 Entity description
    B.8.1 Overall syntax of the entity description
    B.8.1.1 Specifications
    Syntax
    Rules
    Recommendations
    B.8.2 Generic parameter statement
    B.8.2.1 Specifications
    Syntax
    Rules
    B.8.2.2 Description
    B.8.2.3 Examples
    B.8.3 Logical port description statement
    B.8.3.1 Specifications
    Syntax
    Rules
    Permissions
    B.8.3.2 Description
    B.8.3.3 Example
    B.8.4 Standard use statement
    B.8.4.1 Specifications
    Syntax
    Rules
    B.8.4.2 Description
    B.8.4.3 Examples
    B.8.4.4 Version control
    B.8.5 Use statement
    B.8.5.1 Specifications
    Syntax
    Rules
    B.8.5.2 Description
    B.8.5.3 Example
    B.8.6 Component conformance statement
    B.8.6.1 Specifications
    Syntax
    Rules
    B.8.6.2 Description
    B.8.6.3 Example
    B.8.7 Device package pin mappings
    B.8.7.1 Specifications
    Syntax
    Rules
    Permissions
    B.8.7.2 Examples
    B.8.7.3 Description
    B.8.8 Grouped port identification
    B.8.8.1 Specifications
    Syntax
    Rules
    B.8.8.2 Description
    B.8.8.3 Examples
    B.8.9 Scan port identification
    B.8.9.1 Specifications
    Syntax
    Rules
    B.8.9.2 Description
    Examples
    B.8.10 Compliance-enable description
    B.8.10.1 Specifications
    Syntax
    Rules
    Permissions
    B.8.10.2 Description
    B.8.10.3 Examples
    B.8.11 Instruction register description
    B.8.11.1 Specifications
    Syntax
    Rules
    B.8.11.2 Description
    B.8.11.3 Examples
    B.8.12 Optional device register description
    B.8.12.1 Specifications
    Syntax
    Rules
    Recommendations
    Permissions
    B.8.12.2 Description
    B.8.12.3 Examples
    B.8.13 Register access description
    B.8.13.1 Specifications
    Syntax
    Rules
    B.8.13.2 Examples
    B.8.13.3 Description
    B.8.14 Boundary-scan register description
    B.8.14.1 Specifications
    Syntax
    Rules
    Permissions
    B.8.14.2 Examples
    Example 1
    Example 2
    B.8.14.3 Description
    B.8.14.3.1 element
    B.8.14.3.2 element
    B.8.14.3.3 element
    B.8.14.3.4 element
    B.8.14.3.5 element
    B.8.14.3.6 element
    B.8.14.3.7 element
    B.8.14.3.8 element
    B.8.15 RUNBIST description
    B.8.15.1 Specifications
    Syntax
    Rules
    B.8.15.2 Examples
    B.8.16 INTEST description
    B.8.16.1 Specifications
    Syntax
    Rules
    B.8.16.2 Examples
    B.8.17 System clock requirements attribute
    B.8.17.1 Specifications
    Syntax
    Rules
    B.8.17.2 Description
    B.8.17.3 Examples
    B.8.18 Register mnemonics description
    B.8.18.1 Specifications
    Syntax
    Rules
    B.8.18.2 Description
    B.8.18.3 Examples
    Example 1
    Example 2
    Example 3
    B.8.19 Register fields description
    B.8.19.1 Specifications
    Syntax
    Rules
    B.8.19.2 Description
    B.8.19.3 Examples
    B.8.20 Register field assignment description
    B.8.20.1 Specifications
    Syntax
    Rules
    Recommendations
    B.8.20.2 Description
    B.8.21 Register assembly description
    B.8.21.1 Specifications
    Syntax
    Rules
    Permissions
    Recommendations
    B.8.21.2 Description
    Excludable register segments and domain control
    Selectable register segments
    B.8.21.3 Examples
    Initialization REGISTER_ASSEMBLY example
    Boundary-scan example
    Power-domain control example
    IEEE 1500 WSP Examples
    B.8.22 Register constraint description
    B.8.22.1 Specifications
    Syntax
    Rules
    B.8.22.2 Description
    B.8.22.3 Examples
    B.8.23 Register and power port association attributes
    B.8.23.1 Specifications
    Syntax
    Rules
    B.8.23.2 Description
    B.8.23.3 Examples
    B.8.24 User extensions to BSDL
    B.8.24.1 Specifications
    Syntax
    Rules
    Permissions
    B.8.24.2 Description
    B.8.24.3 Examples
    B.8.25 Design warning
    B.8.25.1 Specifications
    Syntax
    B.8.25.2 Description
    B.8.25.3 Examples
    B.9 Standard BSDL Package STD_1149_1_2013
    B.10 User-supplied BSDL packages
    B.10.1 Specifications
    Syntax
    Rules
    Recommendations
    B.10.2 Description
    B.10.3 Examples
    User-supplied package for boundary-register cells
    User-supplied package body for internal registers
    B.11 BSDL example applications
    B.11.1 Typical application of BSDL
    B.11.2 Boundary-scan register description
    B.11.2.1 Multiple cells per pin
    B.11.2.2 Internal boundary register cells
    B.11.2.3 Merged cells
    B.12 1990 version of BSDL
    B.12.1 1990 Standard VHDL Package STD_1149_1_1990
    B.12.2 Typical application of BSDL, 1990 version
    B.12.3 Obsolete syntax
    B.12.3.1 Syntax
    B.12.4 Miscellaneous points on 1990 version
    B.13 1994 version of BSDL
    B.13.1 Standard VHDL Package STD_1149_1_1994
    B.14 2001 version of BSDL
    B.14.1 Standard VHDL Package STD_1149_1_2001
    Annex C (normative) Procedural Description Language (PDL)
    C.1 General information
    C.1.1 Purpose
    C.1.2 Dependence on Tool Command Language (Tcl)
    C.1.3 Dependence on Boundary Scan Description Language (BSDL)
    C.2 PDL concepts and use model
    C.2.1 Use model introduction
    C.2.2 PDL levels
    C.2.2.1 Level-0 PDL
    C.2.2.2 Level-1 PDL
    C.2.3 PDL procedures
    C.2.4 Read and write with capture-shift-update sequence
    C.2.5 Register state definition
    C.2.6 Level-0 PDL commands
    C.2.7 Specification of names and values
    C.2.8 Retargeting
    C.2.9 Simple PDL Example
    U3.PDL
    MEMB.PDL
    Chip_A.PDL
    C.3 PDL Level 0 command reference
    C.3.1 Understanding a PDL “string”
    C.3.2 BNF conventions
    C.3.3 PDL lexical elements and common syntax
    C.3.3.1 Lexical element specifications
    General rules
    Numeric literal rules
    Identifier rules
    Text string rules
    C.3.3.2 Substitutions
    Rules
    C.3.3.3 Common syntax
    Syntax
    Rules
    Description
    C.3.3.4 PDL reserved words
    Rules
    Recommendations
    C.3.4 PDL File
    Syntax
    Rules
    Permissions
    C.3.5 Procedure definition commands
    C.3.5.1 iSource command
    Syntax
    Rules
    Example
    C.3.5.2 iPDLLevel command
    Syntax
    Rules
    Permissions
    Example
    C.3.5.3 iProcGroup command
    Syntax
    Rules
    Permissions
    Example
    C.3.5.4 iProc command
    Syntax
    Rules
    Predefined procedure names
    C.3.6 Test setup commands
    C.3.6.1 iPrefix command
    Syntax
    Rules
    Examples
    C.3.6.2 iSetInstruction command
    Syntax
    Rules
    Examples
    C.3.6.3 iClock and iClockOverride commands
    Syntax
    Rules
    Examples
    C.3.7 Test execution commands
    C.3.7.1 iRead and iWrite commands
    Syntax
    Rules
    Examples
    C.3.7.2 iApply command
    Syntax
    Rules
    Recommendations
    Examples
    C.3.7.3 iScan command
    Syntax
    Rules
    Examples
    C.3.8 Flow-control commands
    C.3.8.1 iCall command
    Syntax
    Rules
    Examples
    C.3.8.2 iRunLoop command
    Syntax
    Rules
    Recommendations
    Examples
    C.3.8.3 iLoop and iUntil commands
    Syntax
    Rules
    Example A
    Example B
    C.3.8.4 ifTrue, ifFalse and ifEnd commands
    Syntax
    Rules
    Example A
    Example B
    C.3.9 Optimization commands
    C.3.9.1 iMerge command
    Syntax
    Rules
    Example
    C.3.9.2 iTake and iRelease commands
    Syntax
    Rules
    Example
    C.3.10 Miscellaneous commands
    C.3.10.1 iNote command
    Syntax
    Recommendations
    Example A
    Example B
    C.3.10.2 iSetFail command
    Syntax
    Rules
    Recommendations
    Examples
    C.3.11 Low-level commands
    C.3.11.1 iTMSreset and iTRST commands
    Syntax
    Rules
    Recommendations
    Example
    C.3.11.2 iTMSidle command
    Syntax
    Rules
    Examples
    C.4 PDL Level 1 command reference
    C.4.1 Level-1 PDL operation
    C.4.2 iGet command
    Syntax
    Rules
    Example A
    Example B
    Example C
    Example D
    Example E
    Example F
    Example G
    C.4.3 iGetStatus command
    Syntax
    Rules
    Example
    C.5 Example BSDL and PDL for the use model
    C.5.1 BSDL Packages for IP
    MEMB
    SERDES
    C.5.2 BSDL files for components
    Chip_A
    Chip_B
    Chip_C
    C.5.3 PDL files supplied by IP supplier
    MEMB
    SERDES
    C.5.4 PDL files supplied by component supplier
    Chip_A
    Chip_B
    Chip_C
    C.5.5 PDL files coded by test engineer
    U1
    U2
    U3
    U4
    UUT
    Annex D (informative) Integrated examples of BSDL and PDL
    D.1 Initialization example structure and procedures
    D.1.1 Initialization example using register description attributes
    D.1.2 Example PDL for INIT example
    D.2 Multiple wrapper serial port structure and procedures
    D.2.1 Wrapper serial port structural description
    Single WSP
    Multiple selectable and gated WSP
    D.2.2 Wrapper serial port example
    Reg_1500.pdl
    Reg_1500S.pdl
    Reg_1500_Assm.pdl
    Annex E (informative) Example iApply execution flow
    IEEE Standard for Test Access Port and Boundary-Scan Architecture IEEE Computer Society Sponsored by the Test Technology Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA 13 May 2013 IEEE Std 1149.1™-2013 (Revision of IEEE Std 1149.1-2001) Authorized licensed use limited to: University of Virginia Libraries. Downloaded on June 18,2014 at 05:29:00 UTC from IEEE Xplore. Restrictions apply.
    Authorized licensed use limited to: University of Virginia Libraries. Downloaded on June 18,2014 at 05:29:00 UTC from IEEE Xplore. Restrictions apply.
    IEEE Std 1149.1TM-2013 (Revision of IEEE Std 1149.1-2001) IEEE Standard for Test Access Port and Boundary-Scan Architecture Sponsor Test Technology Standards Committee of the IEEE Computer Society Approved 6 February 2013 IEEE-SA Standards Board Authorized licensed use limited to: University of Virginia Libraries. Downloaded on June 18,2014 at 05:29:00 UTC from IEEE Xplore. Restrictions apply.
    Abstract: Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards and the test of internal circuits is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards. Also, a language is defined that allows rigorous structural description of the component-specific aspects of such testability features, and a second language is defined that allows rigorous procedural description of how the testability features may be used. Keywords: boundary scan, boundary-scan architecture, Boundary-Scan Description Language (BSDL), boundary-scan register, circuit boards, circuitry, IEEE 1149.1TM, integrated circuit, printed circuit boards, Procedural Description Language (PDL), test, test access port (TAP), very high speed integrated circuit (VHSIC), VHSIC Hardware Description Language (VHDL) • The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright © 2013 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 13 May 2013. Printed in the United States of America. IEEE registered Engineers, Incorporated. PDF: Print: IEEE prohibits discrimination, harassment and bullying. For more information, visit http://www.ieee.org/web/aboutus/whatis/policies/p9-26.html. No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. the U.S. Patent & Trademark Office, owned by The ISBN 978-0-7381-8263-6 ISBN 978-0-7381-8264-3 Institute of Electrical and Electronics is a trademark in STD98160 STDPD98160 Authorized licensed use limited to: University of Virginia Libraries. Downloaded on June 18,2014 at 05:29:00 UTC from IEEE Xplore. Restrictions apply.
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    Participants At the time this standard was submitted to the IEEE-SA Standards Board for approval, the P1149.1 Working Group had the following membership: C. J. Clark, Chair Carol Pyron, Vice-Chair Carl F. Barnhart, Editor Bill Tuthill, Secretary William Eklow Peter Elias Joshua Ferry Jeff Halnon Dharma Konda Roland R. Latvala Adam W. Ley Sankaran Menon Kent Ng Kenneth P. Parker Francisco Russi John Seibold Roger Sowada Craig Stephan Brian Turmelle Hugh Wallace John Braden Bill Bruce Richard Cornejo Adam Cron Wim Driessen David Dubberke Ted Eaton Heiko Ehrenberg The following members of the individual balloting committee voted on this standard. Balloters may have voted for approval, disapproval, or abstention. Gobinathan Athimolom Carl F. Barnhart Hugh Barrass William Borroz John Braden Dennis Brophy Susan Burgess Gunnar Carlsson Vivek Chickermane C. J. Clark Richard Cornejo Adam Cron Alfred Crouch Frans G De Jong Jason Doege Wim Driessen David Dubberke Sourav Dutta Heiko Ehrenberg William Eklow Peter Elias Joshua Ferry Chris Gorringe Prashant Goteti Robert Gottlieb J. Grealish Randall Groves Jeff Halnon Peter Harrod Neil Glenn Jacobson Rohit Kapur Dharma Konda Roland R. Latvala Philippe LeBourg Adam W. Ley Teresa Lopes Greg Luri Wayne Manges Colin Maunder Ian Mcintosh Harrison Miles Jr. Jeffrey Moore Benoit Nadeau-Dostie Ion Neag Kenneth P. Parker Steve Poehlman Ulrich Pohl Irith Pomeranz John Potter Carol Pyron Mike Ricchetti Gordon Robinson Andrzej Rucinski Francisco Russi Bartien Sayogo John Seibold Ozgur Sinanoglu Roger Sowada Craig Stephan Cees Stork Walter Struppler Stephen Sunter Bambang Suparjo Anthony Suto Efren Taboada David Thompson Brian Turmelle Bill Tuthill Louis Ungar Dmitri Varsanofiev Srinivasa Vemuru John Vergis Tom Waayers Douglas D. Way Thomas Williams Henk Wit Oren Yuen Janusz Zalewski Copyright © 2013 IEEE. All rights reserved. vi Authorized licensed use limited to: University of Virginia Libraries. Downloaded on June 18,2014 at 05:29:00 UTC from IEEE Xplore. Restrictions apply.
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