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MIPI Alliance Standard for Display Bus Interface (DBI-2), versio....pdf
1 Overview
1.1 Scope
1.2 Purpose
2 Terminology
2.1 Definitions
2.2 Abbreviations
2.3 Acronyms
3 References
4 Display Architectures and Interface Constructions
4.1 Display Architectures
4.2 Display Bus Interface Constructions
5 Interface Signal Description
5.1 Power Supply Signals
5.2 Interface Signals
6 Interface I/O Cells
7 Interface Functional Description
7.1 Type A Interface Write and Read Cycles
7.2 Type B Interface Write and Read Cycles
7.3 Type C Interface Write and Read Sequences
7.4 Tearing Effect
8 Interface Electrical Characteristics
8.1 Electrical Characteristics
9 Reset
9.1 Host Input/Output Pins
9.2 Display Input/Output Pins
10 Interface Color Coding
10.1 Serial Interface
10.2 8-bit Interface
10.3 9-bit interface
10.4 16-bit Interface
11 Command Set
12 Interoperability, and Optional Capabilities
MIPI Alliance Standard for Display Bus Interface
MIPI Board approved 16 November 2005
v2.0
* Caution to Implementers *
This document is a MIPI Specification formally approved by the MIPI Alliance Board of
Directors per the process defined in the MIPI Alliance Bylaws. This specification is
currently incomplete because it references other MIPI specifications which are still under
development. This specification may be revised when the referenced specifications are
available. Notices will be sent to members when those referenced specifications are
completed.
Copyright © 2005 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential
Version 2.00 29-Nov-2005
MIPI Alliance Standard for Display Bus Interface
MIPI Alliance Standard for Display Bus Interface
Version 2.00 – 29 November 2005
MIPI Board Approved 16-Nov-2005
Further technical changes to DBI are expected as work continues in the Display Working Group
Copyright © 2005 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
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MIPI Alliance Standard for Display Bus Interface
NOTICE OF DISCLAIMER
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or
controlled by any of the authors or developers of this material or MIPI. The material contained herein is
provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is
provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI
hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not
limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a
particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of
viruses, and of lack of negligence.
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH
REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL
ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT
OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE
GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER
CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR
ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,
WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is
further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the
contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;
and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance
with the contents of this Document. The use or implementation of the contents of this Document may
involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,
patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI
does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any
IPR or claims of IPR as respects the contents of this Document or otherwise.
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:
MIPI Alliance, Inc.
c/o IEEE-ISTO
445 Hoes Lane
Piscataway, NJ 08854
Attn: Board Secretary
Copyright © 2005 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
ii
Version 2.00 29-Nov-2005
MIPI Alliance Standard for Display Bus Interface
Contents
1.1
1.2
Version 2.00 – 29 November 2005 ..................................................................................................................i
1 Overview .................................................................................................................................................5
Scope ...............................................................................................................................................5
Purpose ............................................................................................................................................5
2 Terminology ............................................................................................................................................6
2.1 Definitions.......................................................................................................................................6
2.2 Abbreviations ..................................................................................................................................6
2.3 Acronyms ........................................................................................................................................7
3 References ...............................................................................................................................................8
4 Display Architectures and Interface Constructions .................................................................................9
4.1 Display Architectures ......................................................................................................................9
4.2 Display Bus Interface Constructions .............................................................................................16
Interface Signal Description..................................................................................................................18
Power Supply Signals....................................................................................................................18
Interface Signals ............................................................................................................................18
Interface I/O Cells .................................................................................................................................21
Interface Functional Description ...........................................................................................................22
Type A Interface Write and Read Cycles......................................................................................22
Type B Interface Write and Read Cycles ......................................................................................27
Type C Interface Write and Read Sequences ................................................................................30
Tearing Effect................................................................................................................................37
Interface Electrical Characteristics........................................................................................................38
Electrical Characteristics ...............................................................................................................38
9 Reset ......................................................................................................................................................46
9.1 Host Input/Output Pins..................................................................................................................46
9.2 Display Input/Output Pins .............................................................................................................47
7.1
7.2
7.3
7.4
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8.1
5.1
5.2
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MIPI Alliance Member Confidential.
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MIPI Alliance Standard for Display Bus Interface
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Interface Color Coding......................................................................................................................48
10.1 Serial Interface...............................................................................................................................48
10.2 8-bit Interface ................................................................................................................................50
10.3 9-bit interface ................................................................................................................................55
10.4 16-bit Interface ..............................................................................................................................56
Command Set ....................................................................................................................................63
Interoperability, and Optional Capabilities........................................................................................64
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Copyright © 2005 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
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Version 2.00 29-Nov-2005
MIPI Alliance Standard for Display Bus Interface
MIPI Alliance Standard for Display Bus Interface
1 Overview
This document describes Display Bus Interface (DBI), which is used for display modules. DBI can be
configured for 1, 2, 8, 9 or 16 data signals.
This document defines the interface parameters outlined below for both the host processor and display
module.
• Electrical
• Timings
• Protocol examples
• Measurement methods
• Color coding
• Command set to control display behaviors
1.1 Scope
The Display Bus Interface specification defines the electrical and logical interfaces for mobile device host
processors and display modules. Logical control of the display module functional blocks such as power
supply, timing generator and display drivers is also within the scope of this document. The design of the
functional blocks is not within the scope of this specification.
1.2 Purpose
The Display Bus Interface specification is used by manufacturers to design products that adhere to MIPI
specifications for mobile device processor and display interfaces.
Implementing the DBI standard reduces the time-to-market and design cost of mobile devices by
simplifying the interconnection of products from different manufacturers. In addition, adding new features
such as larger or additional displays to mobile devices is simplified due to the extensible nature of the MIPI
specifications.
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Copyright © 2005 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
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Version 2.00 29-Nov-2005
MIPI Alliance Standard for Display Bus Interface
2 Terminology
2.1 Definitions
Command: Digital information used to control display behavior and to identify the connected display
module
Data: Digital image data stored in the frame memory or numerical information to define the display
module behavior accompanied with a command
Display Controller: Isolated IC silicon chip or integrated functional block in the host processor to control
a display module; may or may not include frame memory
Display Device: Functional device which can show image, such as Liquid Crystal Displays
Display Driver IC: IC silicon chip in a display module used to control the display device; may or may not
include frame memory
Display Glass: Same as display device, coming from material name
Display Module: Functional module to show image on it, can consists of display device, display driver IC,
other peripheral components and circuits and display interface
Display Panel: Same as Display Device, coming from the physical outward appearance of the display
device
Frame Memory: Memory device integrated in a display driver IC or display controller in order to provide
image data for refreshing the display device. Full-frame memory provides a full screen area of image data
while partial-frame memory only provides memory for a portion of the screen area.
Type 1 Display Architecture: One of the defined display module architectures. In DSI, DBI, DPI, and
DCS, a display module architecture in which a display module includes a display device, display driver IC,
full-frame memory, registers, timing controller, non-volatile memory and control interface.
Type 2 Display Architecture: One of the defined display module architectures. In DSI, DBI, DPI, and
DCS, a display module architecture in which a display module includes a display device, display driver IC,
partial-frame memory, registers, timing controller, non-volatile memory, control interface and video stream
interface.
Type 3 Display Architecture: One of the defined display module architectures. In DSI, DBI, DPI, and
DCS, a display module architecture in which a display module includes a display device, display driver IC,
registers, timing controller, non-volatile memory, control interface and video stream interface.
Type 4 Display Architecture: One of the defined display module architectures. In DSI, DBI, DPI, and
DCS, a display module architecture in which a display module includes a display device, display driver IC,
registers, timing controller, control lines and video stream interface.
2.2 Abbreviations
↑
↓
Rising edge active
Falling edge active
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Copyright © 2005 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
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MIPI Alliance Standard for Display Bus Interface
Version 2.00 29-Nov-2005
AGND Power ground
CSX
Chip Select, active low
D/CX Data/Command, Command is active low
DGND Logic level ground
High-Z High Impedance
H-Sync Horizontal Synchronization
RESX Reset signal, active low
RDX Read signal
Ta
Ambient Temperature
WRX Write signal
VDD
VDDI
Power Supply
Logic Level Supply
V-Sync Vertical Synchronization
2.3 Acronyms
ASIC Application Specific Integrated Circuit
CMOS Complementary Metal Oxide Semiconductor
DBI
Display Bus Interface
DCS Display Command Set
DOI
Dependent On Implementation
DSI
I/O
Display Serial Interface
Input/Output
LSB
Least Significant Bit
MIPI Mobile Industry Processor Interface
MSB Most Significant Bit
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Copyright © 2005 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
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