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STM32L-硬件开发手册.pdf
Table 1. Applicable products
1 Glossary
2 Power supplies
2.1 Introduction
Figure 1. Power supply overview
2.1.1 Independent A/D converter supply and reference voltage
2.1.2 Independent LCD supply
2.1.3 Voltage regulator
2.2 Power supply schemes
Figure 2. Power supply scheme
Figure 3. Optional LCD power supply scheme
2.3 Reset and power supply supervisor
Figure 4. Power supply supervisors
2.3.1 Power-on reset (POR)/power-down reset (PDR), brownout reset (BOR)
Figure 5. Power on reset/power down reset waveform
2.3.2 Programmable voltage detector (PVD)
Figure 6. PVD thresholds
2.3.3 Brownout reset (BOR)
2.3.4 System reset
Figure 7. Reset circuit
3 Clocks
3.1 MSI clock
3.2 HSE OSC clock
Figure 8. External clock
Figure 9. Crystal/ceramic resonators
3.2.1 External source (HSE bypass)
3.2.2 External crystal/ceramic resonator (HSE crystal)
3.3 LSE OSC clock
Figure 10. External clock(1)
Figure 11. Crystal/ceramic resonators(1)(2)
3.3.1 External source (LSE bypass)
3.3.2 External crystal/ceramic resonator (LSE crystal)
3.4 Clock security system (CSS)
4 Boot configuration
4.1 Boot mode selection
Table 2. Boot modes
4.2 Boot pin connection
Figure 12. Boot mode selection implementation example
4.3 Embedded boot loader mode
5 Debug management
5.1 Introduction
Figure 13. Host-to-board connection
5.2 SWJ debug port (serial wire and JTAG)
5.3 Pinout and debug port pins
5.3.1 SWJ debug port pins
Table 3. Debug port pin assignment
5.3.2 Flexible SWJ-DP pin assignment
Table 4. SWJ I/O pin availability
5.3.3 Internal pull-up and pull-down resistors on JTAG pins
5.3.4 SWJ debug port connection with standard JTAG connector
Figure 14. JTAG connector implementation
6 Recommendations
6.1 Printed circuit board
6.2 Component position
6.3 Ground and power supply (VSS, VDD, VSSA, VDDA)
6.4 Decoupling
Figure 15. Typical layout for VDD/VSS pair
6.5 Other signals
6.6 Unused I/Os and features
7 Reference design
7.1 Description
7.1.1 Clock
7.1.2 Reset
7.1.3 Boot mode
7.1.4 SWJ interface
7.1.5 Power supply
7.2 Component references
Table 5. Mandatory components
Table 6. Optional components
Figure 16. STM32L152VB(T6) microcontroller reference schematic
Table 7. Reference connection for all packages
8 Revision history
Table 8. Document revision history
AN3216
Application note
Getting started with STM32L1xxx hardware development
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use STM32L1xxx product families and describes the minimum hardware
resources required to develop an STM32L1xxx application.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.
Table 1. Applicable products
Type
Microcontrollers
Product categories
STM32L1 series
June 2013
DocID17496 Rev 7
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www.st.com
Contents
Contents
AN3216
1
2
3
4
5
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Independent A/D converter supply and reference voltage . . . . . . . . . . . . 8
2.1.1
2.1.2
Independent LCD supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3.1
2.2
2.3
Power-on reset (POR)/power-down reset (PDR),
brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 13
Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.2
2.3.3
2.3.4
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
3.2
HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1
3.2.2
External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 17
LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1
3.3.2
External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 18
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3
3.4
Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
4.3
Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2
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AN3216
5.3
Contents
Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1
5.3.2
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Internal pull-up and pull-down resistors on JTAG pins . . . . . . . . . . . . . . 24
5.3.3
5.3.4
SWJ debug port connection with standard JTAG connector . . . . . . . . . 24
6
7
Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
6.2
Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Ground and power supply (VSS, VDD, VSSA, VDDA) . . . . . . . . . . . . . . . . . 25
6.3
6.4
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5
6.6
Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1
7.1.1
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1.2
Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1.3
7.1.4
SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1.5
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID17496 Rev 7
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3
List of tables
List of tables
AN3216
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Debug port pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SWJ I/O pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4/33
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AN3216
List of figures
List of figures
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 1.
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2.
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3.
Power supply supervisors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4.
Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5.
PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6.
Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7.
External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8.
Figure 9.
Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. External clock(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Crystal/ceramic resonators(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14.
JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. STM32L152VB(T6) microcontroller reference schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 29
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5
Glossary
1
Glossary
AN3216
•
•
•
Medium-density devices are microcontrollers where the Flash memory ranges
between 32 and 128 Kbytes.
Medium-density + devices are microcontrollers where the Flash memory is
256 Kbytes.
High-density devices are microcontrollers where the Flash memory is 384 Kbytes.
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AN3216
2
2.1
Power supplies
Power supplies
Introduction
Digital power voltage (VCORE) is provided with an embedded linear voltage regulator with
three different programmable ranges from 1.2 to 1.8 V.
To be fully functional at full speed, the device requires a 2.0 to 3.6 V operating voltage
supply (VDD), making possible to reach the digital power voltage VCORE of 1.8 V (product
voltage range 1).
Product voltage range 2 (VCORE = 1.5 V) and 3 (VCORE = 1.2 V) can be selected when the
VDD operates from 1.65 to 3.6 V. Therefore, frequency is limited to 16 MHz and 4 MHz
respectively.
When the ADC and brownout reset (BOR) are not used, the device can operate at power
voltages below 1.8 V down to 1.65 V.
Figure 1. Power supply overview
(from 1.8 V up to VDDA) VREF+
(must be tied to VSSA) VREF-
(VDD) VDDA
(VSS) VSSA
VSS
VDD
Step-up
converter
VSEL
VDDA domain
ADC
DAC
Temp. sensor
Reset block
PLL
VDD domain
I/O supply
Standby circuitry
(wakeup logic,
IWDG, RTC,
LSE crystal
32 Kbyte osc
RCC CSR)
Voltage regulator
dynamic voltage
scaling
Vcore domain
memories
digital
Core
peripherals
VLCD
LCD
ai17469
Note:
VDDA and VSSA must be connected to VDD and VSS, respectively.
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32
Power supplies
AN3216
2.1.1
The ADC voltage supply input is available on a separate VDDA pin
An isolated supply ground connection is provided on the VSSA pin
Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC and the DAC have an independent power supply
that can be filtered separately, and shielded from noise on the PCB.
•
•
VDDA and VREF require a stable voltage. The consumption on VDDA can reach several mA
(see IDD(ADCx), IDD(DAC), IDD(COMPx), IVDDA, and IVREF in the product datasheets for
further information).
When available (depending on the package), VREF¨ must be tied to VSSA.
On BGA 64-pin and all 100-pin or more packages
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to
VREF+, a separate external reference voltage which is lower than VDD. VREF+ is the highest
voltage, represented by the full scale value, for an analog input (ADC) or output (DAC)
signal.
•
For ADC
–
–
–
–
– When product voltage range 3 is selected (VCORE = 1.2 V), the ADC is low speed
2.4 V ≤ VREF+ = VDDA for full speed (ADCCLK = 16 MHz, 1 Msps)
1.8 V ≤ VREF+ = VDDA for medium speed (ADCCLK = 8 MHz, 500 Ksps)
2.4 V ≤ VREF+ ≠ VDDA for medium speed (ADCCLK = 8 MHz, 500 Ksps)
1.8 V ≤ VREF+ < VDDA for low speed (ADCCLK = 4 MHz, 250 Ksps)
(ADCCLK = 4 MHz, 250 Ksps)
•
For DAC
–
1.8 V≤ VREF+ < VDDA
On packages with 64 pins or less (except BGA package)
VREF+ and VREF- pins are not available. They are internally connected to the ADC voltage
supply (VDDA) and ground (VSSA).
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