论文研究-基于FPGA的MFSK调制系统的设计与实现 .pdf

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中国科技论文在线 http://www.paper.edu.cn )3*$ 0)6. E-mail ccc29@yahoo.cn !"#$%&' !()*+, -./012345'6'789:;<=>?@ABCDE7F 'G':8HI7J:KLMNOPQROSTUV7W<'XY7 Z[\]^_`aST7'G':8HI/ ' FPGA ! "#$%&'()*+,-./0123 4"5623789 : ;<=>?*@ABCDEZCEZCE L6$39?) %&789^':;)*

中国科技论文在线 http://www.paper.edu.cn < 2<%&OR=X>< 2<%&>':U:7YZ;2Q`C [;2=>':U:/H)I]&%O R )*QVW\]^ a/PL 2*NE >N)* NE`CEA@?[B`CIG/R?)=N T9;28>NKU"/ N4"?)70 >NKU`)CKUT H( /7^)D] *< >N6+NN_>N$,4/-.C+N)L6:E/ %&/;-#$F0%F]3H12_2-3<8 Y<856F_26 $F;JK%&/ 456 9H"789:" *ZCHE=>E7 8];H<]3 9=_/;83 - 2 -

中国科技论文在线 http://www.paper.edu.cn B MFSK = f H − f L + 2 f S ; Hf M;=<> Lf M_=<> Sf M%&$F/ 0)6. 9+'/ 0)6. )3*$ ><`C?9B< N< /X@A" 7B]3C@ DE<6-F*H(=>[3]/FG)WYH?AJ789V?A [BNCAKU9FKLY F*H(=>3GI/JK < LM@N`CLKU9M9/ O `C?9<LM@N`CLKU9M9/ < >< 789 I?AFB,T A9/ FG)WY A9GIH=>KU/ < `C C@?9 0)6. 9+'/ PQR S 7 TQU$VW"G 789 JK 4 M library ieee; - 3 -

http://www.paper.edu.cn 中国科技论文在线 use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity MFSK is port(clk :in std_logic; --%&7X start :in std_logic; x y :in std_logic; :out std_logic); --WY 9 -789 -- 9 end MFSK; architecture behav of MFSK is signal q :integer range 0 to 15; --EN signal f :std_logic_vector(3 downto 0); --L9 EE N begin if clk'event and clk='1' then if start='0' then f<="0000"; elsif f="1111" then f<="0000"; else f<=f+1; end if; end if; end process; process(clk) begin -- KE789 3?AFB,T A9 if clk'event and clk='1' then if start='0' then q<=0; elsif q=0 then q<=1;xx(1)<=x;yy<=xx; elsif q=8 then q<=9;xx(0)<=x; else q<=q+1; - 4 -

中国科技论文在线 http://www.paper.edu.cn end if; end if; end process; process(clk,yy) begin --3"G KE789 if clk'event and clk='1' then if start='0' then y<='0'; -- if V\"G A%T =>G elsif yy="00" then y<=not f(3); elsif yy="01" then y<=not f(2); elsif yy="10" then y<=not f(1); else y<=not f(0); end if; end if; end process; end behav; 0)6. 9+'/ ]Q^_`a6TQU$VW `C3DEA3 E,T >aB<0/RM;`a7WY3 / < < - 5 -

中国科技论文在线 http://www.paper.edu.cn )6 ]QNTQS#JK%& - ]Q) 623 !),%& ,T-$/;/P7 #- `CL6" LN L`CG T) 94/;- 9 56FS_%&G/ P7 #- `CLDE 2J&@N C ! ]Q# ##_" Y\'IH0#$% )PT%& ';/& 6 %&%&(878) 45 *+%8?, _%&0%F/ *-a.67 NDE#/E01# 2 3 45`C=X67 ;89U:; <=> %&DE?67 `@ABU:; The MFSK Modulation System Based on FPGA Design and Implementation Cai Chenchen Cheng Can Yu Wanli School of Information and Electrical Engineering CUMT,XuZhouO221008R E-mail ccc29@yahoo.cn ABSTRACT Using multicarrier MFSK as the system of the communication system, which inherits the stable reliability and also is compatible with the advantages in the high-use-rate of frequency spectru m for the Orthogonal Frequency Division Multiplexing and greater capability of resisting multi- route-interference and the frequency choice decline for the Multi-Carrier(MC) Modulation rechn ology. In order to study MFSK (M-ary frequency shift keying) modulation system, this paper b ased on field programmable gate arrays, application of basic principles of modulation and dem odulation, in the 2FSK based on hierarchical and modular design approach to achieve the MFS K modulation circuit, Simulation results not only show the correctness of the design, but also verify MFSK modulation and demodulation of the basic principles. Keywords: MFSK FPGA VHDL Modulation - 6 -

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论文研究-基于FPGA的MFSK调制系统的设计与实现 .pdf

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