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关于mipi DSI接口的介绍（官方全英文资料）.pdf
1 Overview
1.1 Scope
1.2 Purpose
2 Terminology (informative)
2.1 Definitions
2.2 Abbreviations
2.3 Acronyms
3 References (informative)
3.1 Display Bus Interface Standard for Parallel Signaling (DBI-2)
3.2 Display Pixel Interface Standard for Parallel Signaling (DPI-2)
3.3 MIPI Alliance Specification for Display Command Set (DCS)
3.4 MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2)
3.5 MIPI Alliance Specification for D-PHY (D-PHY)
4 DSI Introduction
4.1 DSI Layer Definitions
4.2 Command and Video Modes
4.2.1 Command Mode
4.2.2 Video Mode Operation
4.2.3 Virtual Channel Capability
5 DSI Physical Layer
5.1 Data Flow Control
5.2 Bidirectionality and Low Power Signaling Policy
5.3 Command Mode Interfaces
5.4 Video Mode Interfaces
5.5 Bidirectional Control Mechanism
5.6 Clock Management
5.6.1 Clock Requirements
5.6.2 Clock Power and Timing
5.7 System Power-Up and Initialization
6 Multi-Lane Distribution and Merging
6.1 Multi-Lane Interoperability and Lane-number Mismatch
6.1.1 Clock Considerations with Multi-Lane
6.1.2 Bidirectionality and Multi-Lane Capability
6.1.3 SoT and EoT in Multi-Lane Configurations
7 Low-Level Protocol Errors and Contention
7.1 Low-Level Protocol Errors
7.1.1 SoT Error
7.1.2 SoT Sync Error
7.1.3 EoT Sync Error
7.1.4 Escape Mode Entry Command Error
7.1.5 LP Transmission Sync Error
7.1.6 False Control Error
7.2 Contention Detection and Recovery
7.2.1 Contention Detection in LP Mode
7.2.2 Contention Recovery Using Timers
7.3 Additional Timers
7.3.1 Turnaround Acknowledge Timeout (TA_TO)
7.3.2 Peripheral Reset Timeout (PR_TO)
7.4 Acknowledge and Error Reporting Mechanism
8 DSI Protocol
8.1 Multiple Packets per Transmission
8.2 Packet Composition
8.3 Endian Policy
8.4 General Packet Structure
8.4.1 Long Packet Format
8.4.2 Short Packet Format
8.5 Common Packet Elements
8.5.1 Data Identifier Byte
8.5.2 Error Correction Code
8.6 Interleaved Data Streams
8.6.1 Interleaved Data Streams and Bidirectionality
8.7 Processor to Peripheral Direction (Processor-Sourced) Packet Data Types
8.8 Processor-to-Peripheral Transactions – Detailed Format Description
8.8.1 Sync Event (H Start, H End, V Start, V End), Data Type = XX 0001 (0xX1)
8.8.2 EoTp, Data Type = 00 1000 (0x08)
8.8.3 Color Mode Off Command, Data Type = 00 0010 (0x02)
8.8.4 Color Mode On Command, Data Type = 01 0010 (0x12)
8.8.5 Shutdown Peripheral Command, Data Type = 10 0010 (0x22)
8.8.6 Turn On Peripheral Command, Data Type = 11 0010 (0x32)
8.8.7 Generic Short WRITE Packet with 0, 1, or 2 parameters, Data Types = 00 0011 (0x03), 01 0011 (0x13), 10 0011 (0x23), Respectively
8.8.8 Generic READ Request with 0, 1, or 2 Parameters, Data Types = 00 0100 (0x04), 01 0100 (0x14), 10 0100(0x24), Respectively
8.8.9 DCS Commands
8.8.10 Set Maximum Return Packet Size, Data Type = 11 0111 (0x37)
8.8.11 Null Packet (Long), Data Type = 00 1001 (0x09)
8.8.12 Blanking Packet (Long), Data Type = 01 1001 (0x19)
8.8.13 Generic Long Write, Data Type = 10 1001 (0x29)
8.8.14 Loosely Packed Pixel Stream, 20-bit YCbCr 4:2:2 Format, Data Type = 00 1100 (0x0C)
8.8.15 Packed Pixel Stream, 24-bit YCbCr 4:2:2 Format, Data Type = 01 1100 (0x1C)
8.8.16 Packed Pixel Stream, 16-bit YCbCr 4:2:2 Format, Data Type = 10 1100 (0x2C)
8.8.17 Packed Pixel Stream, 30-bit Format, Long Packet, Data Type = 00 1101 (0x0D)
8.8.18 Packed Pixel Stream, 36-bit Format, Long Packet, Data Type = 01 1101 (0x1D)
8.8.19 Packed Pixel Stream, 12-bit YCbCr 4:2:0 Format, Data Type = 11 1101 (0x3D)
8.8.20 Packed Pixel Stream, 16-bit Format, Long Packet, Data Type 00 1110 (0x0E)
8.8.21 Packed Pixel Stream, 18-bit Format, Long Packet, Data Type = 01 1110 (0x1E)
8.8.22 Pixel Stream, 18-bit Format in Three Bytes, Long Packet, Data Type = 10 1110 (0x2E)
8.8.23 Packed Pixel Stream, 24-bit Format, Long Packet, Data Type = 11 1110 (0x3E)
8.8.24 DO NOT USE and Reserved Data Types
8.9 Peripheral-to-Processor (Reverse Direction) LP Transmissions
8.9.1 Packet Structure for Peripheral-to-Processor LP Transmissions
8.9.2 System Requirements for ECC and Checksum and Packet Format
8.9.3 Appropriate Responses to Commands and ACK Requests
8.9.4 Format of Acknowledge and Error Report and Read Response Data Types
8.9.5 Error Reporting Format
8.10 Peripheral-to-Processor Transactions – Detailed Format Description
8.10.1 Acknowledge and Error Report, Data Type 00 0010 (0x02)
8.10.2 Generic Short Read Response, 1 or 2 Bytes, Data Types = 01 0001 or 01 0010, Respectively
8.10.3 Generic Long Read Response with Optional Checksum, Data Type = 01 1010 (0x1A)
8.10.4 DCS Long Read Response with Optional Checksum, Data Type 01 1100 (0x1C)
8.10.5 DCS Short Read Response, 1 or 2 Bytes, Data Types = 10 0001 or 10 0010, Respectively
8.10.6 Multiple Transmissions and Error Reporting
8.10.7 Clearing Error Bits
8.11 Video Mode Interface Timing
8.11.1 Transmission Packet Sequences
8.11.2 Non-Burst Mode with Sync Pulses
8.11.3 Non-Burst Mode with Sync Events
8.11.4 Burst Mode
8.11.5 Parameters
8.12 TE Signaling in DSI
9 Error-Correcting Code (ECC) and Checksum
9.1 Packet Header Error Detection/Correction
9.2 Hamming Code Theory
9.3 Hamming-modified Code Applied to DSI Packet Headers
9.4 ECC Generation on the Transmitter
9.5 Applying ECC on the Receiver
9.6 Checksum Generation for Long Packet Payloads
10 Compliance, Interoperability, and Optional Capabilities
10.1 Display Resolutions
10.2 Pixel Formats
10.2.1 Video Mode
10.2.2 Command Mode
10.3 Number of Lanes
10.4 Maximum Lane Frequency
10.5 Bidirectional Communication
10.6 ECC and Checksum Capabilities
10.7 Display Architecture
10.8 Multiple Peripheral Support
10.9 EoTp Support and Interoperability
Annex A Contention Detection and Recovery Mechanisms (informative)
A.1 PHY Detected Contention
A.1.1 Protocol Response to PHY Detected Faults
Annex B Checksum Generation Example (informative)
Annex C Interlaced Video Transmission Sourcing
Version 1.02.00 28-Jun-2010
MIPI Alliance Specification for DSI
MIPI Alliance Specification for
Display Serial Interface
Version 1.02.00 – 28 June 2010
MIPI Board Approved 20-Oct-2010
Further technical changes to this document are expected as work continues in the Display Working Group
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
Version 1.02.00 28-Jun-2010
NOTICE OF DISCLAIMER
MIPI Alliance Specification for DSI
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled
by any of the authors or developers of this material or MIPI®. The material contained herein is provided on
an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS
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All materials contained herein are protected by copyright laws, and may not be reproduced, republished,
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Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:
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Attn: Board Secretary
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1.1
1.2
2.1
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Contents
Version 1.02.00 – 28 June 2010 ....................................................................................................................... i
1 Overview ............................................................................................................................................... 10
Scope ............................................................................................................................................. 10
Purpose .......................................................................................................................................... 10
Terminology (informative) .................................................................................................................... 11
Definitions ..................................................................................................................................... 11
Abbreviations ................................................................................................................................ 12
Acronyms ...................................................................................................................................... 12
3 References (informative) ....................................................................................................................... 15
3.1
Display Bus Interface Standard for Parallel Signaling (DBI-2) .................................................... 15
Display Pixel Interface Standard for Parallel Signaling (DPI-2) ................................................... 16
3.2
3.3 MIPI Alliance Specification for Display Command Set (DCS) .................................................... 16
3.4 MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2)..................................................... 16
3.5 MIPI Alliance Specification for D-PHY (D-PHY) ........................................................................ 16
4 DSI Introduction .................................................................................................................................... 17
DSI Layer Definitions ................................................................................................................... 18
Command and Video Modes ......................................................................................................... 19
Command Mode .................................................................................................................... 19
Video Mode Operation .......................................................................................................... 19
Virtual Channel Capability .................................................................................................... 20
5 DSI Physical Layer ................................................................................................................................ 21
Data Flow Control ......................................................................................................................... 21
Bidirectionality and Low Power Signaling Policy ........................................................................ 21
Command Mode Interfaces ........................................................................................................... 22
Video Mode Interfaces .................................................................................................................. 22
Bidirectional Control Mechanism ................................................................................................. 22
Clock Management ........................................................................................................................ 23
Clock Requirements .............................................................................................................. 23
Clock Power and Timing ....................................................................................................... 24
System Power-Up and Initialization .............................................................................................. 24
6 Multi-Lane Distribution and Merging ................................................................................................... 26
6.1 Multi-Lane Interoperability and Lane-number Mismatch ............................................................. 27
Clock Considerations with Multi-Lane .................................................................................. 28
Bidirectionality and Multi-Lane Capability ........................................................................... 28
SoT and EoT in Multi-Lane Configurations .......................................................................... 28
5.1
5.2
5.3
5.4
5.5
5.6
4.2.1
4.2.2
4.2.3
5.6.1
5.6.2
5.7
6.1.1
6.1.2
6.1.3
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7.2
7.3
7.4
7.3.1
7.3.2
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7.1
7.2.1
7.2.2
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
Low-Level Protocol Errors and Contention .......................................................................................... 31
Low-Level Protocol Errors ............................................................................................................ 31
SoT Error ............................................................................................................................... 31
SoT Sync Error ...................................................................................................................... 32
EoT Sync Error ...................................................................................................................... 32
Escape Mode Entry Command Error ..................................................................................... 33
LP Transmission Sync Error .................................................................................................. 33
False Control Error ................................................................................................................ 33
Contention Detection and Recovery .............................................................................................. 34
Contention Detection in LP Mode ......................................................................................... 34
Contention Recovery Using Timers ...................................................................................... 34
Additional Timers .......................................................................................................................... 37
Turnaround Acknowledge Timeout (TA_TO) ....................................................................... 37
Peripheral Reset Timeout (PR_TO) ....................................................................................... 37
Acknowledge and Error Reporting Mechanism ............................................................................ 38
8 DSI Protocol .......................................................................................................................................... 39
8.1 Multiple Packets per Transmission ................................................................................................ 39
8.2
Packet Composition ....................................................................................................................... 40
8.3
Endian Policy ................................................................................................................................ 41
General Packet Structure ............................................................................................................... 41
8.4
Long Packet Format ............................................................................................................... 41
Short Packet Format .............................................................................................................. 43
Common Packet Elements ............................................................................................................. 43
Data Identifier Byte ............................................................................................................... 43
Error Correction Code ........................................................................................................... 44
Interleaved Data Streams ............................................................................................................... 45
Interleaved Data Streams and Bidirectionality ...................................................................... 45
Processor to Peripheral Direction (Processor-Sourced) Packet Data Types .................................. 46
Processor-to-Peripheral Transactions – Detailed Format Description ........................................... 47
8.8.1
Sync Event (H Start, H End, V Start, V End), Data Type = XX 0001 (0xX1) ...................... 47
8.8.2
EoTp, Data Type = 00 1000 (0x08) ....................................................................................... 47
Color Mode Off Command, Data Type = 00 0010 (0x02) .................................................... 48
8.8.3
8.8.4
Color Mode On Command, Data Type = 01 0010 (0x12) ..................................................... 48
Shutdown Peripheral Command, Data Type = 10 0010 (0x22) ............................................. 49
8.8.5
8.8.6
Turn On Peripheral Command, Data Type = 11 0010 (0x32) ............................................... 49
8.8.7
Generic Short WRITE Packet with 0, 1, or 2 parameters, Data Types = 00 0011 (0x03), 01
0011 (0x13), 10 0011 (0x23), Respectively .......................................................................................... 49
8.6
8.7
8.8
8.4.1
8.4.2
8.5.1
8.5.2
8.6.1
8.5
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8.9
8.8.8
Generic READ Request with 0, 1, or 2 Parameters, Data Types = 00 0100 (0x04), 01 0100
(0x14), 10 0100(0x24), Respectively .................................................................................................... 49
DCS Commands .................................................................................................................... 50
8.8.9
8.8.10
Set Maximum Return Packet Size, Data Type = 11 0111 (0x37) .......................................... 51
8.8.11 Null Packet (Long), Data Type = 00 1001 (0x09) ................................................................. 51
8.8.12 Blanking Packet (Long), Data Type = 01 1001 (0x19) .......................................................... 51
8.8.13 Generic Long Write, Data Type = 10 1001 (0x29) ................................................................ 51
8.8.14
Loosely Packed Pixel Stream, 20-bit YCbCr 4:2:2 Format, Data Type = 00 1100 (0x0C) ... 51
Packed Pixel Stream, 24-bit YCbCr 4:2:2 Format, Data Type = 01 1100 (0x1C) ................. 53
8.8.15
8.8.16
Packed Pixel Stream, 16-bit YCbCr 4:2:2 Format, Data Type = 10 1100 (0x2C) ................. 54
8.8.17
Packed Pixel Stream, 30-bit Format, Long Packet, Data Type = 00 1101 (0x0D) ................ 54
Packed Pixel Stream, 36-bit Format, Long Packet, Data Type = 01 1101 (0x1D) ................ 55
8.8.18
8.8.19
Packed Pixel Stream, 12-bit YCbCr 4:2:0 Format, Data Type = 11 1101 (0x3D) ................ 56
Packed Pixel Stream, 16-bit Format, Long Packet, Data Type 00 1110 (0x0E) .................... 57
8.8.20
8.8.21
Packed Pixel Stream, 18-bit Format, Long Packet, Data Type = 01 1110 (0x1E) ................. 58
8.8.22
Pixel Stream, 18-bit Format in Three Bytes, Long Packet, Data Type = 10 1110 (0x2E) ..... 60
Packed Pixel Stream, 24-bit Format, Long Packet, Data Type = 11 1110 (0x3E) ................. 61
8.8.23
8.8.24 DO NOT USE and Reserved Data Types .............................................................................. 62
Peripheral-to-Processor (Reverse Direction) LP Transmissions ................................................... 62
Packet Structure for Peripheral-to-Processor LP Transmissions ........................................... 62
System Requirements for ECC and Checksum and Packet Format ....................................... 63
Appropriate Responses to Commands and ACK Requests.................................................... 63
Format of Acknowledge and Error Report and Read Response Data Types ......................... 65
Error Reporting Format ......................................................................................................... 65
8.10 Peripheral-to-Processor Transactions – Detailed Format Description ........................................... 67
8.10.1 Acknowledge and Error Report, Data Type 00 0010 (0x02) ................................................. 68
8.10.2 Generic Short Read Response, 1 or 2 Bytes, Data Types = 01 0001 or 01 0010, Respectively
8.10.3 Generic Long Read Response with Optional Checksum, Data Type = 01 1010 (0x1A) ....... 68
8.10.4 DCS Long Read Response with Optional Checksum, Data Type 01 1100 (0x1C) ............... 69
8.10.5 DCS Short Read Response, 1 or 2 Bytes, Data Types = 10 0001 or 10 0010, Respectively . 69
8.10.6 Multiple Transmissions and Error Reporting ........................................................................ 69
8.10.7 Clearing Error Bits ................................................................................................................. 69
8.11 Video Mode Interface Timing ....................................................................................................... 69
Transmission Packet Sequences ............................................................................................ 70
8.11.1
8.11.2 Non-Burst Mode with Sync Pulses ........................................................................................ 71
8.11.3 Non-Burst Mode with Sync Events ....................................................................................... 72
8.11.4 Burst Mode ............................................................................................................................ 73
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
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9.1
9.2
9.3
9.4
9.5
9.6
Parameters ............................................................................................................................. 74
8.12 TE Signaling in DSI ...................................................................................................................... 75
Error-Correcting Code (ECC) and Checksum ....................................................................................... 77
Packet Header Error Detection/Correction .................................................................................... 77
Hamming Code Theory ................................................................................................................. 77
Hamming-modified Code Applied to DSI Packet Headers ........................................................... 78
ECC Generation on the Transmitter .............................................................................................. 81
Applying ECC on the Receiver ..................................................................................................... 82
Checksum Generation for Long Packet Payloads .......................................................................... 82
Compliance, Interoperability, and Optional Capabilities .................................................................. 84
10.1 Display Resolutions ....................................................................................................................... 84
10.2 Pixel Formats ................................................................................................................................. 85
10.2.1 Video Mode ........................................................................................................................... 85
10.2.2 Command Mode .................................................................................................................... 85
10.3 Number of Lanes ........................................................................................................................... 85
10.4 Maximum Lane Frequency ............................................................................................................ 85
10.5 Bidirectional Communication........................................................................................................ 86
10.6 ECC and Checksum Capabilities ................................................................................................... 86
10.7 Display Architecture ...................................................................................................................... 86
10.8 Multiple Peripheral Support .......................................................................................................... 86
10.9 EoTp Support and Interoperability ................................................................................................ 86
Annex A Contention Detection and Recovery Mechanisms (informative) ............................................... 87
PHY Detected Contention ............................................................................................................. 87
Protocol Response to PHY Detected Faults ........................................................................... 87
Annex B Checksum Generation Example (informative) .......................................................................... 93
Interlaced Video Transmission Sourcing ................................................................................... 95
Annex C
A.1
A.1.1
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Figures
Figure 1 DSI Transmitter and Receiver Interface ..........................................................................................17
Figure 2 DSI Layers ......................................................................................................................................18
Figure 3 Basic HS Transmission Structure ....................................................................................................21
Figure 4 Peripheral Power-Up Sequencing Example ....................................................................................25
Figure 5 Lane Distributor Conceptual Overview ..........................................................................................26
Figure 6 Lane Merger Conceptual Overview ................................................................................................27
Figure 7 Four-Lane Transmitter with Two-Lane Receiver Example ............................................................28
Figure 8 Two Lane HS Transmission Example .............................................................................................29
Figure 9 Three Lane HS Transmission Example ...........................................................................................30
Figure 10 HS Transmission Examples with EoTp disabled ..........................................................................40
Figure 11 HS Transmission Examples with EoTp enabled ...........................................................................40
Figure 12 Endian Example (Long Packet) .....................................................................................................41
Figure 13 Long Packet Structure ...................................................................................................................42
Figure 14 Short Packet Structure ...................................................................................................................43
Figure 15 Data Identifier Byte .......................................................................................................................44
Figure 16 Interleaved Data Stream Example with EoTp disabled .................................................................45
Figure 17 Logical Channel Block Diagram (Receiver Case) ........................................................................45
Figure 18 20-bit per Pixel – YCbCr 4:2:2 Format, Long Packet ...................................................................52
Figure 19 24-bit per Pixel – YCbCr 4:2:2 Format, Long Packet ...................................................................53
Figure 20 16-bit per Pixel – YCbCr 4:2:2 Format, Long Packet ...................................................................54
Figure 21 30-bit per Pixel (Packed) – RGB Color Format, Long Packet ......................................................55
Figure 22 36-bit per Pixel (Packed) – RGB Color Format, Long Packet ......................................................56
Figure 23 12-bit per Pixel – YCbCr 4:2:0 Format (Odd Line), Long Packet ................................................57
Figure 24 12-bit per Pixel – YCbCr 4:2:0 Format (Even Line), Long Packet ...............................................57
Figure 25 16-bit per Pixel – RGB Color Format, Long Packet .....................................................................58
Figure 26 18-bit per Pixel (Packed) – RGB Color Format, Long Packet ......................................................59
Figure 27 18-bit per Pixel (Loosely Packed) – RGB Color Format, Long Packet ........................................60
Figure 28 24-bit per Pixel – RGB Color Format, Long Packet .....................................................................61
Figure 29 Video Mode Interface Timing Legend ..........................................................................................71
Figure 30 Video Mode Interface Timing: Non-Burst Transmission with Sync Start and End ......................72
Figure 31 Video Mode Interface Timing: Non-burst Transmission with Sync Events .................................73
Figure 32 Video Mode Interface Timing: Burst Transmission ......................................................................74
Figure 33 24-bit ECC generation on TX side ................................................................................................81
Figure 34 24-bit ECC on RX Side Including Error Correction .....................................................................82
Figure 35 Checksum Transmission ...............................................................................................................83
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Figure 36 16-bit CRC Generation Using a Shift Register .............................................................................83
Figure 37 LP High LP Low Contention Case 1 ....................................................................................89
Figure 38 LP High LP Low Contention Case 2 ....................................................................................91
Figure 39 LP High LP Low Contention Case 3 ....................................................................................92
Figure 40 Video Mode Interface Timing: Non-burst Transmission with Sync Start and End (Interlaced
Video) ............................................................................................................................................................95
Figure 41 Video Mode Interface Timing: Non-burst Transmission with Sync Events (Interlaced Video) ...96
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