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SD Specifications Part 1 Physical Layer Specification Version 3.....pdf
Revision History
Table of Contents
Table of Figures
Table of Tables
1. General Description
2. System Features
3. SD Memory Card System Concept
3.1 Read-Write Property
3.2 Supply Voltage
3.3 Card Capacity
3.4 Speed Class
3.5 Bus Topology
3.6 Bus Protocol
3.7 SD Memory Card–Pins and Registers
3.8 ROM Card
3.9 Ultra High Speed Phase I (UHS-I) Card
4. SD Memory Card Functional Description
4.1 General
4.2 Card Identification Mode
4.2.1 Card Reset
4.2.2 Operating Condition Validation
4.2.3 Card Initialization and Identification Process
4.2.3.1 Initialization Command (ACMD41)
4.2.4 Bus Signal Voltage Switch Sequence
4.2.4.1 Initialization Sequence for UHS-I
4.2.4.2 Timing to Switch Signal Voltage
4.2.4.3 Timing of Voltage Switch Error Detection
4.2.4.4 Voltage Switch Command
4.2.4.5 Tuning Command
4.2.4.6 An Example of UHS-I System Block Diagram
4.3 Data Transfer Mode
4.3.1 Wide Bus Selection/Deselection
4.3.2 2GByte Card
4.3.3 Data Read
4.3.4 Data Write
4.3.5 Erase
4.3.6 Write Protect Management
4.3.7 Card Lock/Unlock Operation
4.3.7.1 General
4.3.7.2 Parameter and the Result of CMD42
4.3.7.3 Forcing Erase
4.3.7.3.1 Force Erase Function to the Locked Card
4.3.7.4 Relation Between ACMD6 and Lock/Unlock State
4.3.7.5 Commands Accepted for Locked Card
4.3.7.6 Two Types of Lock/Unlock Card
4.3.8 Content Protection
4.3.9 Application-Specific Commands
4.3.9.1 Application-Specific Command – APP_CMD (CMD55)
4.3.9.2 General Command - GEN_CMD (CMD56)
4.3.10 Switch Function Command
4.3.10.1 General
4.3.10.2 Mode 0 Operation - Check Function
4.3.10.3 Mode 1 Operation - Set Function
4.3.10.4 Switch Function Status
4.3.10.4.1 Busy Status Indication for Functions
4.3.10.4.2 Data Structure Version
4.3.10.4.3 Function Table of Switch Command
4.3.10.5 Relationship between CMD6 data & other commands
4.3.10.6 Switch Function Flow Example
4.3.10.7 Example of Checking
4.3.10.8 Example of Switching
4.3.11 High-Speed Mode (25 MB/sec interface speed)
4.3.12 Command System
4.3.13 Send Interface Condition Command (CMD8)
4.3.14 Command Functional Difference in Card Capacity Types
4.4 Clock Control
4.5 Cyclic Redundancy Code (CRC)
4.6 Error Conditions
4.6.1 CRC and Illegal Command
4.6.2 Read, Write and Erase Timeout Conditions
4.6.2.1 Read
4.6.2.2 Write
4.6.2.3 Erase
4.7 Commands
4.7.1 Command Types
4.7.2 Command Format
4.7.3 Command Classes
4.7.4 Detailed Command Description
4.8 Card State Transition Table
4.9 Responses
4.9.1 R1 (normal response command):
4.9.2 R1b
4.9.3 R2 (CID, CSD register)
4.9.4 R3 (OCR register)
4.9.5 R6 (Published RCA response)
4.9.6 R7 (Card interface condition)
4.10 Two Status Information of SD Memory Card
4.10.1 Card Status
4.10.2 SD Status
4.11 Memory Array Partitioning
4.12 Timings
4.12.1 Command and Response
4.12.2 Data Read
4.12.3 Data Write
4.12.4 Timing Values
4.12.5 Timing Changes in SDR50 and SDR104 Modes
4.12.5.1 CRC Status Start Timing
4.12.5.2 Read Block Gap
4.12.5.3 CMD12 Timing Modification in Write Operation
4.12.5.4 CMD12 Timing Modification in Read Operation
4.12.6 Timing Changes in DDR50 Mode
4.12.6.1 Definition of Odd / Even
4.12.6.2 Protocol Principles
4.12.6.3 CRC Status Token Conventions os DDR50
4.12.6.4 CRC16 of DDR50
4.12.6.5 Data Access Timing example in DDR50
4.12.6.6 Clock Control
4.12.6.7 Reset Command
4.13 Speed Class Specification
4.13.1 Speed Class Specification for SDSC and SDHC
4.13.1.1 Allocation Unit (AU)
4.13.1.2 Recording Unit (RU)
4.13.1.3 Write Performance
4.13.1.4 Read Performance
4.13.1.5 Performance Curve Definition
4.13.1.6 Speed Class Definition
4.13.1.7 Consideration for Inserting FAT Update during Recording
4.13.1.7.1 Measurement Condition to determine Average TFw
4.13.1.7.2 Maximum FAT write Time
4.13.1.8 Measurement Conditions and Requirements of the Speed Class
4.13.2 Speed Class Specification for SDXC
4.13.2.1 Speed Class Parameters
4.13.2.2 Write Performance
4.13.2.3 Read Performance
4.13.2.4 FAT Update
4.13.2.5 CI (Continuous Information) Update
4.13.2.6 Distinction of Data Type
4.13.2.7 Measurement Conditions and Requirements of the Speed Class for SDXC
4.13.2.8 Speed Class Control Command (CMD20)
4.13.2.9 Example of Speed Class Recording Sequence
4.14 Erase Timeout Calculation
5. Card Registers
5.1 OCR register
5.2 CID register
5.3 CSD Register
5.3.1 CSD_STRUCTURE
5.3.2 CSD Register (CSD Version 1.0)
5.3.3 CSD Register (CSD Version 2.0)
5.4 RCA register
5.5 DSR register (Optional)
5.6 SCR register
6. SD Memory Card Hardware Interface
7. SPI Mode
Appendix A (Normative) : Reference
Appendix B (Normative) : Special Terms
Appendix C (Informative) :Examples for Fixed Delay UHS-I Host Design
Appendix D : UHS-I Tuning Procedure
Appendix E : Host Design Recommendation
SD Specifications
Part 1
Physical Layer Specification
Version 3.00
April 16, 2009
SD Group
Panasonic Corporation
SanDisk Corporation
Toshiba Corporation
Technical Committee
SD Card Association
NETCOM DIGITAL (HONG KONG) LTDDownloaded by VANESSA CHUI NETCOM DIGITAL (HONG KONG) LTD on 07/26/2009
Physical Layer Specification Version 3.00
©Copyright 2001-2009 SD Group (Panasonic, SanDisk, Toshiba) and SD Card Association
Revision History
Version
1.0
1.01
1.10
Date
March 22, 2000
April 15, 2001
October 15, 2004
May 9, 2006
2.00
April 16, 2009
3.00
Changes compared to previous issue
Base version (Draft only)
Initial release version
- Version 1.01 + supplementary notes Version 1.01e(March 21, 2004)
- CMD6 (Switch Function command) is specified and CMD34-37, 50
and 57 are reserved for new command system.
- High-Speed mode is specified.(Up to 25 MB/sec Read/Write rate)
- eCommerce command set and Vendor Specific command set are
specified
- Version 1.10 + supplementary notes Version 1.00.
- High Capacity SD Memory Card is specified. (Up to and including 32
GB)
Followings are added to the Version 2.00
(1) Physical Ver2.00 Supplementary Notes Version 1.00 is applied.
(2) Extended Capacity (SDXC) is supported
(3) Ultra High Speed I (UHS-I) is supported
(4) Speed Class Specification Update
(5) Set Block Count Command (CMD23) is added
To the extent this proposed specification, which is being submitted for review under the IP
Policy, implements, incorporates by reference or refers to any portion of versions 1.0 or 1.01
of the SD Specifications (including Parts 1 through 4), adoption of the proposed specification
shall require Members utilizing the adopted specification to obtain the appropriate licenses
from the SD-3C, LLC, as required for the utilization of those portion(s) of versions 1.0 or 1.01
of the SD Specifications.
For example, implementation of the SD Specifications in a host device under versions 1.0 or
1.01 and under the adopted specification requires the execution of a SD Host Ancillary
License Agreement with the SD-3C, LLC; and implementation of the SD Specifications under
versions 1.0 or 1.01 and under the proposed specification in a SD Card containing any
memory storage capability (other than for storage of executable code for a controller or
microprocessor within the SD Card) requires the execution of a SD Memory Card License
Agreement with the SD-3C, LLC.
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Physical Layer Specification Version 3.00
©Copyright 2001-2009 SD Group (Panasonic, SanDisk, Toshiba) and SD Card Association
Conditions for publication
Publisher:
SD Card Association
2400 Camino Ramon, Suite 375
San Ramon, CA 94583 USA
Telephone: +1 (925) 275-6615,
Fax: +1 (925) 886-4870
E-mail: office@sdcard.org
The SD Group
Copyright Holders:
Panasonic Corporation
SanDisk Corporation
Toshiba Corporation
The SD Card Association
Notes:
The copyright of the previous versions (Version 1.00 and 1.01) and all corrections or non-material
changes thereto are owned by SD Group.
The copyright of material changes to the previous versions (Version 1.01) are owned by SD Card
Association.
Confidentiality:
The contents of this document are deemed confidential information of the SD-3C LLC and/or the SD
Card Association (the "Disclosers"). As such, the contents and your right to use the contents are
subject to the confidentiality obligations stated in the written agreement you entered into with the
Disclosers which entitled you to receive this document, such as a Non-Disclosure Agreement, the
License Agreement for SDA Memory Card Specifications (also known as "LAMS"), the SD
Host/Ancillary Product License Agreement (also known as "HALA") or the IP Policy.
Disclaimers:
The information contained herein is presented only as a standard specification for SD Card and SD
Host/Ancillary products. No responsibility is assumed by SD Card Association for any damages, any
infringements of patents or other right of the third parties, which may result from its use. No license is
granted by implication or otherwise under any patent or rights of SD Group and SD Card Association or
others.
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Physical Layer Specification Version 3.00
©Copyright 2001-2009 SD Group (Panasonic, SanDisk, Toshiba) and SD Card Association
Conventions Used in This Document
Naming Conventions
• Some terms are capitalized to distinguish their definition from their common English meaning. Words
not capitalized have their common English meaning.
Numbers and Number Bases
• Hexadecimal numbers are written with a lower case "h" suffix, e.g., FFFFh and 80h.
• Binary numbers are written with a lower case "b" suffix (e.g., 10b).
• Binary numbers larger than four digits are written with a space dividing each group of four digits, as in
1000 0101 0010b.
• All other numbers are decimal.
Key Words
• May:
• Shall:
Indicates flexibility of choice with no implied recommendation or requirement.
Indicates a mandatory
requirements to ensure interchangeability and to claim conformance with the specification.
requirement. Designers shall
implement such mandatory
• Should: Indicates a strong recommendation but not a mandatory requirement. Designers should
give strong consideration to such recommendations, but there is still a choice in
implementation.
Application Notes
Some sections of this document provide guidance to the host implementers as follows:
Application Note:
This is an example of an application note.
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Physical Layer Specification Version 3.00
©Copyright 2001-2009 SD Group (Panasonic, SanDisk, Toshiba) and SD Card Association
Table of Contents
1. General Description............................................................................................................1
2. System Features .................................................................................................................3
3. SD Memory Card System Concept....................................................................................5
3.1 Read-Write Property......................................................................................................................5
3.2 Supply Voltage...............................................................................................................................5
3.3 Card Capacity................................................................................................................................6
3.4 Speed Class ..................................................................................................................................7
3.5 Bus Topology .................................................................................................................................8
3.5.1 SD Bus....................................................................................................................................8
3.5.2 SPI Bus ...................................................................................................................................9
3.6 Bus Protocol ................................................................................................................................10
3.6.1 SD Bus..................................................................................................................................10
3.6.2 SPI Bus .................................................................................................................................13
3.7 SD Memory Card–Pins and Registers.........................................................................................14
3.8 ROM Card ...................................................................................................................................16
3.8.1 Register Setting Requirements .............................................................................................16
3.8.2 Unsupported Commands ......................................................................................................16
3.8.3 Optional Commands .............................................................................................................16
3.8.4 WP Switch.............................................................................................................................16
3.9 Ultra High Speed Phase I (UHS-I) Card ......................................................................................17
3.9.1 UHS-I Operation Modes........................................................................................................17
3.9.2 UHS-I Card Types .................................................................................................................17
3.9.3 Host and Card Combination..................................................................................................18
3.9.4 Bus Speed Modes Selection Sequence................................................................................19
3.9.5 UHS System Block Diagram .................................................................................................20
3.9.5.1 Variable Sampling Host......................................................................................................... 20
3.9.5.2 Fixed Sampling Host............................................................................................................. 20
3.9.6 Summary of Bus Speed Mode ..............................................................................................21
4. SD Memory Card Functional Description .......................................................................22
4.1 General........................................................................................................................................22
4.2 Card Identification Mode..............................................................................................................23
4.2.1 Card Reset............................................................................................................................23
4.2.2 Operating Condition Validation..............................................................................................23
4.2.3 Card Initialization and Identification Process ........................................................................25
4.2.3.1 Initialization Command (ACMD41)........................................................................................ 27
4.2.4 Bus Signal Voltage Switch Sequence ...................................................................................28
4.2.4.1 Initialization Sequence for UHS-I .......................................................................................... 28
4.2.4.2 Timing to Switch Signal Voltage............................................................................................ 29
4.2.4.3 Timing of Voltage Switch Error Detection.............................................................................. 30
4.2.4.4 Voltage Switch Command..................................................................................................... 30
4.2.4.5 Tuning Command ................................................................................................................. 31
4.2.4.6 An Example of UHS-I System Block Diagram....................................................................... 33
4.3 Data Transfer Mode.....................................................................................................................34
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Physical Layer Specification Version 3.00
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4.3.1 Wide Bus Selection/Deselection ...........................................................................................36
4.3.2 2 GByte Card ........................................................................................................................36
4.3.3 Data Read .............................................................................................................................36
4.3.4 Data Write .............................................................................................................................37
4.3.5 Erase.....................................................................................................................................39
4.3.6 Write Protect Management ...................................................................................................39
4.3.7 Card Lock/Unlock Operation.................................................................................................40
4.3.7.1 General................................................................................................................................. 40
4.3.7.2 Parameter and the Result of CMD42.................................................................................... 42
4.3.7.3 Forcing Erase ....................................................................................................................... 44
4.3.7.3.1 Force Erase Function to the Locked Card...................................................................... 44
4.3.7.4 Relation Between ACMD6 and Lock/Unlock State................................................................ 45
4.3.7.5 Commands Accepted for Locked Card ................................................................................. 45
4.3.7.6 Two Types of Lock/Unlock Card............................................................................................ 46
4.3.8 Content Protection ................................................................................................................46
4.3.9 Application-Specific Commands............................................................................................47
4.3.9.1 Application-Specific Command – APP_CMD (CMD55)......................................................... 47
4.3.9.2 General Command - GEN_CMD (CMD56)........................................................................... 47
4.3.10 Switch Function Command .................................................................................................48
4.3.10.1 General............................................................................................................................... 48
4.3.10.2 Mode 0 Operation - Check Function ................................................................................... 50
4.3.10.3 Mode 1 Operation - Set Function........................................................................................ 50
4.3.10.4 Switch Function Status........................................................................................................ 52
4.3.10.4.1 Busy Status Indication for Functions ............................................................................ 53
4.3.10.4.2 Data Structure Version ................................................................................................. 54
4.3.10.4.3 Function Table of Switch Command............................................................................. 54
4.3.10.5 Relationship between CMD6 data & other commands ....................................................... 56
4.3.10.6 Switch Function Flow Example ........................................................................................... 57
4.3.10.7 Example of Checking.......................................................................................................... 59
4.3.10.8 Example of Switching ......................................................................................................... 60
4.3.11 High-Speed Mode (25 MB/sec interface speed)..................................................................61
4.3.12 Command System...............................................................................................................61
4.3.13 Send Interface Condition Command (CMD8) .....................................................................62
4.3.14 Command Functional Difference in Card Capacity Types...................................................63
4.4 Clock Control...............................................................................................................................64
4.5 Cyclic Redundancy Code (CRC) .................................................................................................65
4.6 Error Conditions...........................................................................................................................67
4.6.1 CRC and Illegal Command ...................................................................................................67
4.6.2 Read, Write and Erase Timeout Conditions ..........................................................................67
4.6.2.1 Read ..................................................................................................................................... 67
4.6.2.2 Write ..................................................................................................................................... 67
4.6.2.3 Erase .................................................................................................................................... 68
4.7 Commands ..................................................................................................................................69
4.7.1 Command Types ...................................................................................................................69
4.7.2 Command Format .................................................................................................................69
4.7.3 Command Classes................................................................................................................69
4.7.4 Detailed Command Description ............................................................................................72
4.8 Card State Transition Table .........................................................................................................80
4.9 Responses...................................................................................................................................82
4.9.1 R1 (normal response command):..........................................................................................82
4.9.2 R1b........................................................................................................................................82
4.9.3 R2 (CID, CSD register) .........................................................................................................82
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Physical Layer Specification Version 3.00
©Copyright 2001-2009 SD Group (Panasonic, SanDisk, Toshiba) and SD Card Association
4.9.4 R3 (OCR register) .................................................................................................................83
4.9.5 R6 (Published RCA response) ..............................................................................................83
4.9.6 R7 (Card interface condition) ................................................................................................84
4.10 Two Status Information of SD Memory Card .............................................................................85
4.10.1 Card Status .........................................................................................................................85
4.10.2 SD Status ............................................................................................................................89
4.11 Memory Array Partitioning .........................................................................................................93
4.12 Timings ......................................................................................................................................95
4.12.1 Command and Response ...................................................................................................95
4.12.2 Data Read ...........................................................................................................................97
4.12.3 Data Write ...........................................................................................................................98
4.12.4 Timing Values....................................................................................................................101
4.12.5 Timing Changes in SDR50 and SDR104 Modes ..............................................................102
4.12.5.1 CRC Status Start Timing ................................................................................................... 102
4.12.5.2 Read Block Gap................................................................................................................ 102
4.12.5.3 CMD12 Timing Modification in Write Operation ................................................................ 102
4.12.5.4 CMD12 Timing Modification in Read Operation................................................................ 103
4.12.5.5 Timing Values ................................................................................................................... 104
4.12.6 Timing Changes in DDR50 Mode......................................................................................105
4.12.6.1 Definition of Odd / Even.................................................................................................... 105
4.12.6.2 Protocol Principles ............................................................................................................ 105
4.12.6.3 CRC Status Token Conventions of DDR50 ....................................................................... 106
4.12.6.4 CRC16 of DDR50 ............................................................................................................. 106
4.12.6.5 Data Access Timing example in DDR50 ........................................................................... 107
4.12.6.6 Clock Control .................................................................................................................... 107
4.12.6.7 Reset Command............................................................................................................... 107
4.13 Speed Class Specification .......................................................................................................108
4.13.1 Speed Class Specification for SDSC and SDHC ..............................................................108
4.13.1.1 Allocation Unit (AU)........................................................................................................... 108
4.13.1.2 Recording Unit (RU) ......................................................................................................... 108
4.13.1.3 Write Performance............................................................................................................ 109
4.13.1.4 Read Performance.............................................................................................................110
4.13.1.5 Performance Curve Definition............................................................................................110
4.13.1.6 Speed Class Definition.......................................................................................................111
4.13.1.7 Consideration for Inserting FAT Update during Recording.................................................112
4.13.1.7.1 Measurement Condition to determine Average TFw .....................................................112
4.13.1.7.2 Maximum FAT Write Time ...........................................................................................112
4.13.1.8 Measurement Conditions and Requirements of the Speed Class......................................113
4.13.1.8.1 Measurement Conditions ............................................................................................113
4.13.1.8.2 Requirements of the Performance Parameters for Each Speed Class........................113
4.13.1.8.3 Requirements of SD File System ................................................................................113
4.13.2 Speed Class Specification for SDXC................................................................................. 114
4.13.2.1 Speed Class Parameters ...................................................................................................114
4.13.2.1.1 AU ...............................................................................................................................114
4.13.2.1.2 RU...............................................................................................................................114
4.13.2.2 Write Performance.............................................................................................................114
4.13.2.2.1 Measurement of Pw ....................................................................................................114
4.13.2.2.2 Performance Move......................................................................................................115
4.13.2.3 Read Performance.............................................................................................................115
4.13.2.4 FAT Update........................................................................................................................115
4.13.2.5 CI (Continuous Information) Update ..................................................................................115
4.13.2.6 Distinction of Data Type .....................................................................................................116
4.13.2.7 Measurement Conditions and Requirements of the Speed Class for SDXC......................116
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Physical Layer Specification Version 3.00
©Copyright 2001-2009 SD Group (Panasonic, SanDisk, Toshiba) and SD Card Association
4.13.2.7.1 Measurement Conditions ............................................................................................116
4.13.2.7.2 Requirements of the Performance Parameters for Each Speed Class........................117
4.13.2.7.3 Requirements of SD File System ................................................................................117
4.13.2.8 Speed Class Control Command (CMD20) .........................................................................117
4.13.2.8.1 Definition of Each Function .........................................................................................118
4.13.2.8.2 Requirements for Speed Class Host ...........................................................................118
4.13.2.9 Example of Speed Class Recording Sequence .................................................................118
4.14 Erase Timeout Calculation.......................................................................................................120
4.14.1 Erase Unit .........................................................................................................................120
4.14.2 Case Analysis of Erase Time Characteristics....................................................................120
4.14.3 Method for Erase Large Areas ..........................................................................................121
4.14.4 Calculation of Erase Timeout Value Using the Parameter Registers ................................121
4.14.5 Set Block Count Command...............................................................................................122
5. Card Registers ................................................................................................................123
5.1 OCR register..............................................................................................................................124
5.2 CID register ...............................................................................................................................125
5.3 CSD Register.............................................................................................................................127
5.3.1 CSD_STRUCTURE ............................................................................................................127
5.3.2 CSD Register (CSD Version 1.0) ........................................................................................128
5.3.3 CSD Register (CSD Version 2.0) ........................................................................................135
5.4 RCA register ..............................................................................................................................138
5.5 DSR register (Optional) .............................................................................................................138
5.6 SCR register..............................................................................................................................138
6. SD Memory Card Hardware Interface............................................................................141
6.1 Hot Insertion and Removal ........................................................................................................142
6.2 Card Detection (Insertion/Removal) ..........................................................................................142
6.3 Power Protection (Insertion/Removal).......................................................................................143
6.4 Power Scheme ..........................................................................................................................144
6.4.1 Power Up ............................................................................................................................144
6.4.1.1 Power Up Time ................................................................................................................... 145
6.4.1.2 Power On or Power Cycle................................................................................................... 145
6.4.1.3 Power Supply Ramp Up...................................................................................................... 145
6.4.2 Power Down and Power Cycle............................................................................................145
6.5 Programmable Card Output Driver (Optional) ...........................................................................146
6.6 Bus Operating Conditions for 3.3V Signaling ............................................................................148
6.6.1 Threshold Level for High Voltage Range ............................................................................148
6.6.2 Peak Voltage and Leakage Current ....................................................................................148
6.6.3 Current Consumption..........................................................................................................148
6.6.4 Bus signal line load .............................................................................................................149
6.6.5 Bus Signal Levels................................................................................................................149
6.6.6 Bus Timing (Default)............................................................................................................150
6.6.7 Bus Timing (High-Speed Mode) ..........................................................................................152
6.7 Driver Strength and Bus Timing for 1.8V Signaling ...................................................................154
6.7.1 Output Driver Strength ........................................................................................................154
6.7.1.1 4-Level Driver Strength ....................................................................................................... 154
6.7.1.2 I/O Drive Strength Types..................................................................................................... 154
6.7.1.3 I/O Driver Target AC Characteristics ................................................................................... 155
6.7.1.3.1 Requirement for Rise / Fall Time.................................................................................. 155
6.7.1.3.2 Design Target for Ratio of Rise / Fall Time ................................................................... 155
6.7.1.3.3 Output Driver Test Circuit ............................................................................................. 156
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