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mipi_D-PHY_specification_v2-1-er01.pdf

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    Errata 01
    Contents
    Figures
    Tables
    Release History
    1 Introduction
    1.1 Scope
    1.2 Purpose
    2 Terminology
    2.1 Use of Special Terms
    2.2 Definitions
    2.3 Abbreviations
    2.4 Acronyms
    3 References
    4 D-PHY Overview
    4.1 Summary of PHY Functionality
    4.2 Mandatory Functionality
    5 Architecture
    5.1 Lane Modules
    5.2 Master and Slave
    5.3 High Frequency Clock Generation
    5.4 Clock Lane, Data Lanes and the PHY-Protocol Interface
    5.5 Selectable Lane Options
    5.6 Lane Module Types
    5.6.1 Unidirectional Data Lane
    5.6.2 Bi-directional Data Lanes
    5.6.2.1 Bi-directional Data Lane without High-Speed Reverse Communication
    5.6.2.2 Bi-directional Data Lane with High-Speed Reverse Communication
    5.6.3 Clock Lane
    5.7 Configurations
    5.7.1 Unidirectional Configurations
    5.7.1.1 PHY Configuration with a Single Data Lane
    5.7.1.2 PHY Configuration with Multiple Data Lanes
    5.7.1.3 Dual-Simplex (Two Directions with Unidirectional Lanes)
    5.7.2 Bi-Directional Half-Duplex Configurations
    5.7.2.1 PHY Configurations with a Single Data Lane
    5.7.2.2 PHY Configurations with Multiple Data Lanes
    5.7.3 Mixed Data Lane Configurations
    6 Global Operation
    6.1 Transmission Data Structure
    6.1.1 Data Units
    6.1.2 Bit order, Serialization, and De-Serialization
    6.1.3 Encoding and Decoding
    6.1.4 Data Buffering
    6.2 Lane States and Line Levels
    6.3 Operating Modes: Control, High-Speed, and Escape
    6.4 High-Speed Data Transmission
    6.4.1 Burst Payload Data
    6.4.2 Start-of-Transmission
    6.4.3 End-of-Transmission
    6.4.4 HS Data Transmission Burst
    6.5 Bi-directional Data Lane Turnaround
    6.6 Escape Mode
    6.6.1 Remote Triggers
    6.6.2 Low-Power Data Transmission
    6.6.3 Ultra-Low Power State
    6.6.4 Escape Mode State Machine
    6.7 High-Speed Clock Transmission
    6.8 Clock Lane Ultra-Low Power State
    6.9 Global Operation Timing Parameters
    6.10 System Power States
    6.11 Initialization
    6.12 Calibration
    6.13 Alternate Calibration Sequence
    6.14 Preamble Sequence
    6.15 HS-Idle State
    6.16 Sync Patterns
    6.17 Global Operation Flow Diagram
    6.18 Data Rate Dependent Parameters (informative)
    6.18.1 Parameters Containing Only UI Values
    6.18.2 Parameters Containing Time and UI values
    6.18.3 Parameters Containing Only Time Values
    6.18.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent
    6.19 Interoperability
    7 Fault Detection
    7.1 Contention Detection
    7.2 Sequence Error Detection
    7.2.1 SoT Error
    7.2.2 SoT Sync Error
    7.2.3 EoT Sync Error
    7.2.4 Escape Mode Entry Command Error
    7.2.5 LP Transmission Sync Error
    7.2.6 False Control Error
    7.3 Protocol Watchdog Timers (informative)
    7.3.1 HS RX Timeout
    7.3.2 HS TX Timeout
    7.3.3 Escape Mode Timeout
    7.3.4 Escape Mode Silence Timeout
    7.3.5 Turnaround Errors
    8 Interconnect and Lane Configuration
    8.1 Lane Configuration
    8.2 Boundary Conditions
    8.3 Definitions
    8.4 S-parameter Specifications
    8.5 Characterization Conditions
    8.6 Interconnect Specifications
    8.6.1 Differential Characteristics
    8.6.1.1 Differential Insertion Loss for Data Rate ≥ 80 Mbps and ≤ 1.5 Gbps
    8.6.1.2 Differential Insertion Loss for Data Rate > 1.5 Gbps and ≤ 4.5 Gbps
    8.6.1.3 Differential Reflection Loss for Data Rate ≥ 80 Mbps and ≤ 1.5 Gbps
    8.6.1.4 Differential Reflection Loss for Data Rate >1.5 Gbps and ≤ 4.5 Gbps
    8.6.2 Common-mode Characteristics
    8.6.3 Intra-Lane Cross-Coupling
    8.6.4 Mode-Conversion Limits
    8.6.5 Inter-Lane Cross-Coupling
    8.6.6 Inter-Lane Static Skew
    8.7 Driver and Receiver Characteristics
    8.7.1 Differential Characteristics
    8.7.2 Common-Mode Characteristics
    8.7.3 Mode-Conversion Limits
    9 Electrical Characteristics
    9.1 Driver Characteristics
    9.1.1 High-Speed Transmitter
    9.1.1.1 Differential & Common Mode Swing
    9.1.1.2 Differential Voltage Mismatch
    9.1.1.3 Static Common Mode Mismatch & Transient Common Mode Voltage
    9.1.1.4 Output Resistance
    9.1.1.5 Rise/Fall Times
    9.1.1.6 Half Swing Mode
    9.1.1.7 De-emphasis
    9.1.2 Low-Power Transmitter
    9.2 Receiver Characteristics
    9.2.1 High-Speed Receiver
    9.2.2 Low-Power Receiver
    9.3 Line Contention Detection
    9.4 Input Characteristics
    10 High-Speed Data-Clock Timing
    10.1 High-Speed Clock Timing
    10.2 Forward High-Speed Data Transmission Timing
    10.2.1 Data-Clock Timing Specifications
    10.2.1.1 Data Rate ≥ 0.08 Gbps and ≤ 1 Gbps
    10.2.1.2 Data Rate > 1 Gbps and ≤ 1.5 Gbps
    10.2.1.3 Data Rate > 1.5 Gbps and ≤ 4.5 Gbps
    10.2.2 Normative Spread Spectrum Clocking (SSC)
    10.2.3 Transmitter Eye Diagram Specification
    10.2.4 Receiver Eye Diagram Specification
    10.3 Reverse High-Speed Data Transmission Timing
    10.4 Operating Modes: Data Rate and Channel Support Guidance
    11 Regulatory Requirements
    12 Built-In HS Test Mode (Informative)
    12.1 Introduction
    12.2 Entering the HS Test Mode
    12.3 HS Test Mode
    12.4 Special Case: Multi-Lane Testing
    12.5 Exiting from HS Test Mode
    Annex A Logical PHY-Protocol Interface Description (informative)
    A.1 Signal Description
    A.2 High-Speed Transmit from the Master Side
    A.3 High-Speed Receive at the Slave Side
    A.4 High-Speed Transmit from the Slave Side
    A.5 High-Speed Receive at the Master Side
    A.6 Low-Power Data Transmission
    A.7 Low-Power Data Reception
    A.8 Turn-around
    A.9 Calibration
    A.10 High Speed Receive in HS-Idle State
    A.11 Optical Link Support
    A.11.1 System Setup
    A.11.2 Serializer and De-Serializer Block Diagrams
    A.11.3 Timing Constraints
    A.11.4 System Constraints
    A.11.4.1 Bus Turnaround
    A.11.4.2 Equalization (De-emphasis), Deskewing, and Spread Spectrum Clocking
    A.11.4.3 TWAIT-OPTICAL
    A.12 Higher Data Rate Operation
    Annex B Interconnect Design Guidelines (informative)
    B.1 Practical Distances
    B.2 RF Frequency Bands: Interference
    B.3 Transmission Line Design
    B.4 Reference Layer
    B.5 Printed-Circuit Board
    B.6 Flex-foils
    B.7 Series Resistance
    B.8 Connectors
    Annex C 8b9b Line Coding for D-PHY (normative)
    C.1 Line Coding Features
    C.1.1 Enabled Features for the Protocol
    C.1.2 Enabled Features for the PHY
    C.2 Coding Scheme
    C.2.1 8b9b Coding Properties
    C.2.2 Data Codes: Basic Code Set
    C.2.3 Comma Codes: Unique Exception Codes
    C.2.4 Control Codes: Regular Exception Codes
    C.2.5 Complete Coding Scheme
    C.3 Operation with the D-PHY
    C.3.1 Payload: Data and Control
    C.3.1.1 Idle/Sync Comma Symbols
    C.3.1.2 Protocol Marker Comma Symbol
    C.3.1.3 EoT Marker
    C.3.2 Details for HS Transmission
    C.3.2.1 SoT
    C.3.2.2 HS Transmission Payload
    C.3.2.3 EoT
    C.3.3 Details for LP Transmission
    C.3.3.1 SoT
    C.3.3.2 LP Transmission Payload
    C.3.3.3 EoT
    C.4 Error Signaling
    C.5 Extended PPI
    C.6 Complete Code Set
    Annex D Description of the PRBS9 Generator
    Errata 01 13-Nov-2017 Errata 01 for MIPI D-PHY Specification v2.1 Errata 01 for MIPI D-PHYSM Specification Specification Version 2.1 Specification Dated 15 December 2016 Specification MIPI Board Adopted 28 December 2015 Errata 01 Dated 13 November 2017 Errata MIPI Board Approved 30 November 2017 * IMPORTANT NOTE TO IMPLEMENTERS * • • • • The changes listed in this Errata document will be made in the next edition of this MIPI Specification. Implementations should observe all changes listed here. The location of each change is also marked in the attached copy of the MIPI Specification. To reduce the risk of incorrect implementations, we suggest you consider discarding any previous copies of this MIPI Specification not so marked. This MIPI Specification as modified by the changes listed in this Errata document is also a MIPI Specification, as the MIPI Bylaws defines the term. • MIPI member companies’ rights and obligations apply to the modified MIPI Specification as defined in the MIPI Membership Agreement and MIPI Bylaws. Copyright © 2017 MIPI Alliance, Inc. All rights reserved. Confidential 1
    Errata for MIPI D-PHY Specification v2.1 Errata 01 13-Nov-2017 1 2 3 4 5 6 7 This Errata document includes 11 changes to the Board Adopted MIPI Specification for D-PHY v2.1. These changes are listed below as separate Items, and are highlighted in the attached copy of the adopted Specification: • Items 1 and 3 contain the key Technical corrections: the seed of the PRBS9 generator is changed, and Figure 28 is replaced with a new Figure 89 (which appears in a new Annex D, see Item 10). • Item 7 addresses the fact that changing the seed results in a different PRBS9 bit sequence. • Most of the other Items are Editorial, and necessitated by the key Technical Items. Item 1 Spec Page Number PDF Page Number 48 68 2 48 68 3 48 68 4 48 68 Correction Editorial or Technical: Technical Location: Line 655 Correction: Change “000000001” to “011111111” Reason: Use same seed value as in Section 12.3, for consistency Technical Impact: Changes the bit sequence of the PRBS9 test pattern Editorial or Technical: Editorial Location: Line 658 Correction: Change “…Data[7:0]. Data[7:0] is the output of the Q8 through Q1 registers, as shown in Figure 28.” To “…Data[7:0]. Data[7:0] is shown in Annex D.” Reason: Material has moved to new Annex (see Item 10) Technical Impact: None Editorial or Technical: Technical Location: Line 662 Correction: Delete Figure 28, and replace all references to “Figure 28” with references to ”Figure 89 in Annex D” Reason: Material has moved to a new Annex (see Item 10) Technical Impact: Clarification of tapping points, and location of LSB and MSB in figure Editorial or Technical: Editorial Location: Line 665 Correction: Change “1000 0000 0001 0000” To “1111 1111 1000 0011” Reason: Updates the example to reflect technical changes made in Items 1, 6, 7, and 10 Technical Impact: None 2 Copyright © 2017 MIPI Alliance, Inc. All rights reserved. Confidential
    Errata 01 13-Nov-2017 5 6 104 124 104 124 Errata 01 for MIPI D-PHY Specification v2.1 Editorial or Technical: Editorial Location: Line 1372 Correction: Insert closing parenthesis ‘)‘ at end of line Reason: Copy editing error in adopted Specification Technical Impact: None Editorial or Technical: Technical Location: Lines 1377 and 1378 Correction: Change “…[15:0] with a 16 bit seed register initialized 0x00FF:” To “…with a register initialized to 011111111 (Q9:Q1):” Reason: Remove reference to register size Technical Impact: Changes the bit sequence of the PRBS9 test pattern Copyright © 2017 MIPI Alliance, Inc. All rights reserved. Confidential 3
    Errata for MIPI D-PHY Specification v2.1 7 104 124 Errata 01 13-Nov-2017 Editorial or Technical: Technical Location: Lines 1379 through 1386 Correction: Replace line 1379 plus the entire PRBS9 test pattern with the ‘Replacement PRBS9 Test Pattern” shown below Reason: Result of change to the PRBS9 seed value and tapping points, as well as location of LSB and MSB in PRBS generator Technical Impact: Changes the bit sequence of the PRBS9 test pattern Replacement PRBS9 Test Pattern: 0b11111111_10000011_11011111_00010111_ 00110010_00001001_01001110_11010001_ 11100111_11001101_10001010_10010001_ 11000110_11010101_11000100_11000100_ 01000000_00100001_00011000_01001110_ 01010101_10000110_11110100_11011100_ 10001010_00010101_10100111_11101100_ 10010010_11011111_10010011_01010011_ 00110000_00011000_11001010_00110100_ 10111111_10100010_11000111_01011001_ 01100111_10001111_10111010_00001101_ 01101101_11011000_00101101_01111101_ 01010100_00001010_01010111_10010111_ 01110000_00111001_11010010_01111010_ 11101010_00100100_00110011_10000101_ 11101101_10011010_00011101_1110000/1_ 11111111_00000111_10111110_00101110_ 01100100_00010010_10011101_10100011_ 11001111_10011011_00010101_00100011_ 10001101_10101011_10001001_10001000_ 10000000_01000010_00110000_10011100_ 10101011_00001101_11101001_10111001_ 00010100_00101011_01001111_11011001_ 00100101_10111111_00100110_10100110_ 01100000_00110001_10010100_01101001_ 01111111_01000101_10001110_10110010_ 11001111_00011111_01110100_00011010_ 11011011_10110000_01011010_11111010_ 10101000_00010100_10101111_00101110_ 11100000_01110011_10100100_11110101_ 11010100_01001000_01100111_00001011_ 11011011_00110100_00111011_110000/11_ 11111110 4 Copyright © 2017 MIPI Alliance, Inc. All rights reserved. Confidential
    Errata 01 13-Nov-2017 Errata 01 for MIPI D-PHY Specification v2.1 8 104 124 Editorial or Technical: Editorial Location: Before line 1387 Correction: Insert 9 104 124 10 144 164 “The repetition period is 511 bits, and it starts with eight ones of the PRBS9 sequence based on seed of 011111111 (Q9:Q1). In the PRBS9 sequence shown above, every repetition period is separated by a red slash (‘/’), and every byte is separated by an underscore (‘_’).” Reason: Explains PRBS9 test pattern and improved formatting in the replacement PRBS9 test pattern (see Item 7) Technical Impact: None Editorial or Technical: Editorial Location: Line 1391 Correction: Change ‘data are’ to ‘data is’ Reason: Grammar edit Technical Impact: None Editorial or Technical: Both Location: After page 144 (i.e., after Annex C and before Participants section) Correction: Insert new Annex D as shown on the following page Reason: Revised description of the PRBS9 Generator, corrected PRBS9 seed value, and resulting change to PRBS9 test pattern is required Technical Impact: Changes the PRBS9 seed value and bit sequence of the PRBS9 test pattern 11 6 26 Editorial or Technical: Editorial Location: After line 161 Correction: Insert new document reference [ITUT01] as shown below Reason: The new Annex D cites ITU-150, and this Item provides the reference to the document. Technical Impact: None [ITUT01] ITU-T Recommendation O.150, Specifications of measuring equipment – Equipment for the measurement of digital and analogue/digital parameters – General requirements for instrumentation for performance measurements on digital transmission equipment, , International Telecommunications Union, 5 October 1992. Copyright © 2017 MIPI Alliance, Inc. All rights reserved. Confidential 5
    Errata for MIPI D-PHY Specification v2.1 Errata 01 13-Nov-2017 Annex D Description of the PRBS9 Generator The PRBS9 generator is used for calibration (Section 6.13) and for the HS Test Mode (Section 12.3). Per ITU-150 [ITUT01], the data stream is generated by a shift register set with the following feedback: x0 + x5 + x9. The generator is connected to the serializer as shown in Figure 89. Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Q 9 D a t a 7 MSB D a t a 0 LSB D a t a 6 D a t a 5 D a t a 4 D a t a 3 D a t a 2 D a t a 1 8-Bit Data Serializer (LSB first) PAD Bit Domain Figure 89 PRBS Generator and Connection to the Serializer With the seed of 0b011111111 [Q9:Q1], the following data stream is produced (repetition length 511 bits): 0b11111111_10000011_11011111_00010111_00110010_00001001_01001110_11010001_ 11100111_11001101_10001010_10010001_11000110_11010101_11000100_11000100_ 01000000_00100001_00011000_01001110_01010101_10000110_11110100_11011100_ 10001010_00010101_10100111_11101100_10010010_11011111_10010011_01010011_ 00110000_00011000_11001010_00110100_10111111_10100010_11000111_01011001_ 01100111_10001111_10111010_00001101_01101101_11011000_00101101_01111101_ 01010100_00001010_01010111_10010111_01110000_00111001_11010010_01111010_ 11101010_00100100_00110011_10000101_11101101_10011010_00011101_1110000/1_ 11111111_00000111_10111110_00101110_01100100_00010010_10011101_10100011_ 11001111_10011011_00010101_00100011_10001101_10101011_10001001_10001000_ 10000000_01000010_00110000_10011100_10101011_00001101_11101001_10111001_ 00010100_00101011_01001111_11011001_00100101_10111111_00100110_10100110_ 01100000_00110001_10010100_01101001_01111111_01000101_10001110_10110010_ 11001111_00011111_01110100_00011010_11011011_10110000_01011010_11111010_ 10101000_00010100_10101111_00101110_11100000_01110011_10100100_11110101_ 11010100_01001000_01100111_00001011_11011011_00110100_00111011_110000/11_ 11111110 The repetition period is 511 bits, and it starts with eight ones of the PRBS9 sequence (based on seed of 0b011111111 [Q9:Q1]). In the PRBS9 sequence shown above, every repetition period is separated by a red slash (‘/’), and every byte is separated by an underscore (‘_’). (End of new Annex D) 6 Copyright © 2017 MIPI Alliance, Inc. All rights reserved. Confidential
    Specification for D-PHYSM Version 2.1 15 December 2016 MIPI Board Adopted 28 March 2017 This document is a MIPI Specification. MIPI member companies’ rights and obligations apply to this MIPI Specification as defined in the MIPI Membership Agreement and MIPI Bylaws. Further technical changes to this document are expected as work continues in the PHY Working Group. Copyright © 2007-2017 MIPI Alliance, Inc. All rights reserved. Confidential
    Specification for D-PHY Version 2.1 15-Dec-2016 NOTICE OF DISCLAIMER The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI®. The material contained herein is provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document; and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance with the contents of this Document. The use or implementation of the contents of this Document may involve or require the use of intellectual property rights (“IPR”) including (but not limited to) patents, patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any IPR or claims of IPR as respects the contents of this Document or otherwise. Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: MIPI Alliance, Inc. c/o IEEE-ISTO 445 Hoes Lane Piscataway, NJ 08854 Attn: Board Secretary ii Copyright © 2007-2017 MIPI Alliance, Inc. All rights reserved. Confidential
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