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软核cortexM1/M3 的FPGA实现介绍.pdf
Arm® Cortex®-M3 DesignStart™ FPGA-Xilinx edition User Guide
Table of Contents
Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographic conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1 : Introduction
1.1 : Cortex®-M3 DesignStart™ FPGA-Xilinx edition package
1.2 : Directory structure
1.3 : Cortex®-M3 processor integration
2 : Installing the Cortex®-M3 DesignStart™ example design
2.1 : Installing board files
2.2 : Setting local drive for Windows
2.3 : Installing Arm IP repository
2.4 : Installing Arm software repository
2.5 : Downloading QSPI memory models
2.5.1 : Micron QSPI model
2.5.2 : Cypress QSPI model
2.6 : Configuring simulation in Vivado
3 : Cortex®-M3 processor IP configuration
3.1 : Configuration tab
3.2 : Debug tab
3.3 : Instruction Memory tab
3.4 : Data Memory tab
3.5 : Cortex®-M3 processor signals
4 : Working with the Cortex®-M3 DesignStart™ example design
4.1 : Editing the A7 example design
4.2 : Debug
4.3 : Memory map
4.4 : QSPI multiplexing for the V2C-DAPLink board
4.5 : Interrupt mapping
4.6 : Constraints
4.7 : Loading the pre-built bitstream
4.8 : Loading the flash file
4.9 : Bit file regeneration
4.10 : Simulation
4.10.1 : Testbench conditionals
4.10.2 : Executing code from QSPI
4.10.3 : Wave files
5 : V2C-DAPLink board
5.1 : V2C-DAPLink adaptor board features
5.2 : V2C-DAPLink configuration
5.3 : Flash download requirements
5.4 : V2C-DAPLink board layout
5.5 : Conditions to enable the DAP interface
5.6 : DAP drivers
5.7 : Programming the V2C-DAPLink QSPI using drag and drop
5.8 : Using the μVision debugger to communicate through V2C-DAPLink
5.9 : Using the μVision debugger to download projects through the flash programming utility
5.10 : Recovering the DAP connection
6 : Example software design
6.1 : Example software design for Arty A7
6.2 : Example software design directory structure
6.3 : Example design reference files
6.4 : Generating the Arty A7 board support package
6.5 : Building the example software design
6.5.1 : Software design post processing
6.6 : Software update flow
6.6.1 : Generating the MMI file
6.6.2 : Generating bit and flash files
6.6.3 : Programming
A : Revisions
A.1 : Revisions
Arm® Cortex®-M3 DesignStart™ FPGA-
Xilinx edition
Revision: r0p0
User Guide
Copyright © 2018 Arm Limited or its affiliates. All rights reserved.
101483_0000_00_en
Arm® Cortex®-M3 DesignStart™ FPGA-Xilinx edition
Arm® Cortex®-M3 DesignStart™ FPGA-Xilinx edition
User Guide
Copyright © 2018 Arm Limited or its affiliates. All rights reserved.
Release Information
Document History
Issue
0000-00
Date
29 October 2018
Confidentiality
Non-Confidential
Change
First release for r0p0.
Non-Confidential Proprietary Notice
This document is protected by copyright and other related rights and the practice or implementation of the information contained in
this document may be protected by one or more patents or pending patent applications. No part of this document may be
reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by
estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.
Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use
the information for the purposes of determining whether implementations infringe any third party patents.
THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES,
EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE
WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has
undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other
rights.
This document may include technical inaccuracies or typographical errors.
TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES,
INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR
CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING
OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of
this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is
not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to Arm’s customers is
not intended to create or refer to any partnership relationship with any other company. Arm may make changes to this document at
any time and without notice.
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The Arm corporate logo and words marked with ® or ™ are registered trademarks or trademarks of Arm Limited (or its
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trademarks of their respective owners. Please follow Arm’s trademark usage guidelines at http://www.arm.com/company/policies/
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Copyright © 2018 Arm Limited (or its affiliates). All rights reserved.
Arm Limited. Company 02557590 registered in England.
110 Fulbourn Road, Cambridge, England CB1 9NJ.
LES-PRE-20349
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Non-Confidential
2
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in
accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.
Arm® Cortex®-M3 DesignStart™ FPGA-Xilinx edition
Unrestricted Access is an Arm internal classification.
Product Status
The information in this document is Final, that is for a developed product.
Web Address
http://www.arm.com
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3
Contents
Arm® Cortex®-M3 DesignStart™ FPGA-Xilinx edition
User Guide
Chapter 1
Chapter 2
Chapter 3
Preface
About this book ...................................................... ...................................................... 7
Feedback ...................................................................................................................... 9
Introduction
1.1
1.2
1.3
Cortex®-M3 DesignStart™ FPGA-Xilinx edition package .......................................... 1-11
Directory structure ................................................. ................................................. 1-12
Cortex®-M3 processor integration ............................................................................ 1-13
Installing the Cortex®-M3 DesignStart™ example design
2.1
2.2
2.3
2.4
2.5
2.6
Installing board files ................................................ ................................................ 2-15
Setting local drive for Windows ....................................... ....................................... 2-17
Installing Arm IP repository ...................................................................................... 2-18
Installing Arm software repository ..................................... ..................................... 2-19
Downloading QSPI memory models ........................................................................ 2-21
Configuring simulation in Vivado ...................................... ...................................... 2-23
Cortex®-M3 processor IP configuration
3.1
3.2
3.3
3.4
Configuration tab .................................................. .................................................. 3-25
Debug tab ................................................................................................................ 3-27
Instruction Memory tab ............................................................................................ 3-29
Data Memory tab .................................................. .................................................. 3-31
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Copyright © 2018 Arm Limited or its affiliates. All rights reserved.
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4
Chapter 4
Chapter 5
Chapter 6
3.5
Cortex®-M3 processor signals ........................................ ........................................ 3-33
Working with the Cortex®-M3 DesignStart™ example design
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
Editing the A7 example design ................................................................................ 4-36
Debug ...................................................................................................................... 4-37
Memory map ............................................................................................................ 4-38
QSPI multiplexing for the V2C-DAPLink board ........................... ........................... 4-41
Interrupt mapping .................................................................................................... 4-42
Constraints .............................................................................................................. 4-43
Loading the pre-built bitstream ................................................................................ 4-44
Loading the flash file ................................................................................................ 4-45
Bit file regeneration .................................................................................................. 4-47
Simulation ................................................................................................................ 4-48
V2C-DAPLink board
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
V2C-DAPLink adaptor board features .................................. .................................. 5-50
V2C-DAPLink configuration .......................................... .......................................... 5-52
Flash download requirements ........................................ ........................................ 5-53
V2C-DAPLink board layout ...................................................................................... 5-54
Conditions to enable the DAP interface ................................. ................................. 5-56
DAP drivers ...................................................... ...................................................... 5-57
Programming the V2C-DAPLink QSPI using drag and drop ................. ................. 5-58
Using the μVision debugger to communicate through V2C-DAPLink .......... .......... 5-60
Using the μVision debugger to download projects through the flash programming
utility ........................................................................................................................ 5-62
Recovering the DAP connection .............................................................................. 5-65
5.10
Example software design
6.1
6.2
6.3
6.4
6.5
6.6
Example software design for Arty A7 ...................................................................... 6-68
Example software design directory structure ............................. ............................. 6-69
Example design reference files ....................................... ....................................... 6-70
Generating the Arty A7 board support package ...................................................... 6-71
Building the example software design .................................. .................................. 6-77
Software update flow ............................................... ............................................... 6-78
Appendix A
Revisions
A.1
Revisions ................................................... ................................................... Appx-A-81
101483_0000_00_en
Copyright © 2018 Arm Limited or its affiliates. All rights reserved.
Non-Confidential
5
Preface
This preface introduces the Arm® Cortex®-M3 DesignStart™ FPGA-Xilinx edition User Guide.
It contains the following:
• About this book on page 7.
• Feedback on page 9.
101483_0000_00_en
Copyright © 2018 Arm Limited or its affiliates. All rights reserved.
Non-Confidential
6
Preface
About this book
About this book
This book describes how to use the Cortex®-M3 DesignStart™ FPGA-Xilinx edition to design your
system using the Cortex-M3 processor. This book also describes an example design for the Digilent Arty
Artix 7 (A7) development board.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2,
where:
rm Identifies the major revision of the product, for example, r1.
pn Identifies the minor revision or modification status of the product, for example, p2.
Intended audience
The intended audience is system designers, system integrators, and verification engineers who want to
implement the processor in a Field-Programmable Gate Array (FPGA) using the Xilinx Vivado tools.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
The Cortex-M3 DesignStart™ FPGA-Xilinx edition package provides an easy way to use the
Cortex-M3 processor in the Xilinx Vivado design environment. The Cortex-M3 processor is
intended for deeply embedded applications, usually in ASIC designs. It can be implemented in
FPGA, but is not optimized for timing. The processor implements the Armv7‑M architecture.
Chapter 2 Installing the Cortex®-M3 DesignStart™ example design
This chapter describes the Cortex-M3 DesignStart example design installation process.
Chapter 3 Cortex®-M3 processor IP configuration
After installing the Arm IP Integrator (IPI) repository, you can find the Cortex-M3 processor
package in the Vivado IP catalog.
Chapter 4 Working with the Cortex®-M3 DesignStart™ example design
This chapter describes how to work with an example design targeting a low-cost evaluation board,
Digilent Arty Artix 7 (A7). This example design is provided to demonstrate the integration and
software development using the Cortex-M3 processor. The example is based on the Digilent Arty
A7-35T board, and uses some of the standard Xilinx peripherals to connect to some of the
features on the board. The example is intended to show typical usage, rather than a completely
minimal Cortex-M3 processor design.
Chapter 5 V2C-DAPLink board
The optional V2C-DAPLink adaptor board provides a debug flow that is familiar to anyone who
is used to working with Cortex‑M microcontrollers. It allows Arty FPGA boards to be used with
mbed OS 2 Classic. This chapter describes the optional V2C-DAPLink adaptor board and how it
is used.
Chapter 6 Example software design
This chapter describes an example software design, and describes how to build and debug it.
Appendix A Revisions
This appendix describes the technical changes between released issues of this document.
Glossary
The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for those
terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning
differs from the generally accepted meaning.
101483_0000_00_en
Copyright © 2018 Arm Limited or its affiliates. All rights reserved.
Non-Confidential
7
Preface
About this book
See the Arm® Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
ADD Rd, SP, #
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the
Arm® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
Additional reading
This book contains information that is specific to this product. See the following documents for other
relevant information.
Arm publications
• Cortex®-M3 Technical Reference Manual (100165).
• Arm® CoreSight™ SoC-400 Technical Reference Manual (DDI 0480).
The following confidential book is only available to licensees:
Cortex®-M3 Integration and Implementation Manual (DII 0240B).
Other publications
IEEE Std 1149.1-2001, Test Access Port and Boundary-Scan Architecture (JTAG).
•
• ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic.
101483_0000_00_en
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Non-Confidential
8
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