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IEEE 1012-2012.pdf
IEEE Std 1012-2012 Front Cover
Title Page
Notice to users
Laws and regulations
Copyrights
Updating of IEEE documents
Errata
Patents
Participants
Introduction
Contents
Important notice
1. Overview
1.1 Scope
1.2 Purpose
1.3 Field of application
1.4 V&V objectives
1.5 Organization of the standard
1.6 Audience
1.7 Conformance
1.8 Disclaimer
2. Normative references
3. Definitions, abbreviations, and acronyms
3.1 Definitions
3.2 Abbreviations and acronyms
4. Relationships between V&V and life cycle processes
5. Integrity levels
6. V&V processes overview
6.1 General
6.2 V&V testing
7. Common V&V activities
7.1 Activity: V&V Management
7.2 Activity: Acquisition Support V&V
7.3 Activity: Supply Planning V&V
7.4 Activity: Project Planning V&V
7.5 Activity: Configuration Management V&V
8. System V&V activities
8.1 Activity: Stakeholder Requirements Definition V&V
The purpose of the Stakeholder Requirements Definition Process is to define the requirements for a system that can provide the services needed by users and other stakeholders in a defined environment. It identifies stakeholders, or stakeholder classes...
The V&V effort shall perform, as specified in Table 2b for the selected integrity level, the following Stakeholder Requirements Definition V&V tasks described in Table 1b:
8.2 Activity: Requirements Analysis V&V
8.3 Activity: Architectural Design V&V
8.4 Activity: Implementation V&V
8.5 Activity: Integration V&V
8.6 Activity: Transition V&V
8.7 Activity: Operation V&V
8.8 Activity: Maintenance V&V
8.9 Activity: Disposal V&V
9. Software V&V activities
9.1 Activity: Software Concept V&V
9.2 Activity: Software Requirements V&V
9.3 Activity: Software Design V&V
9.4 Activity: Software Construction V&V
9.5 Activity: Software Integration Test V&V
9.6 Activity: Software Qualification Test V&V
9.7 Activity: Software Acceptance Test V&V
9.8 Activity: Software Installation and Checkout V&V
9.9 Activity: Software Operation V&V
9.10 Activity: Software Maintenance V&V
9.11 Activity: Software Disposal V&V
10. Hardware V&V activities
10.1 Activity: Hardware Concept V&V
10.2 Activity: Hardware Requirements V&V
10.3 Activity: Hardware Design V&V
10.4 Activity: Hardware Fabrication V&V
10.5 Activity: Hardware Integration Test V&V
10.6 Activity: Hardware Qualification Test V&V
10.7 Activity: Hardware Acceptance Test V&V
10.8 Activity: Hardware Transition V&V
10.9 Activity: Hardware Operation V&V
10.10 Activity: Hardware Maintenance V&V
10.11 Activity: Hardware Disposal V&V
11. V&V reporting, administrative, and documentation requirements
11.1 V&V reporting requirements
11.2 V&V administrative requirements
11.3 V&V documentation requirements
12. V&V plan outline
12.1 Overview
12.2 VVP Section 1: Purpose
12.3 VVP Section 2: Referenced documents
12.4 VVP Section 3: Definitions
12.5 VVP Section 4: V&V overview
12.5.1 VVP Section 4.1: Organization
12.5.2 VVP Section 4.2: Master schedule
12.5.3 VVP Section 4.3: Integrity level scheme
12.5.4 VVP Section 4.4: Resources summary
12.5.5 VVP Section 4.5: Responsibilities
12.5.6 VVP Section 4.6: Tools, techniques, and methods
12.6 VVP Section 5: V&V processes
12.6.1 VVP Section 5.1: Common V&V Processes, Activities, and Tasks
12.6.2 VVP Section 5.2: System V&V Processes, Activities, and Tasks
12.6.3 VVP Section 5.3: Software V&V Processes, Activities, and Tasks
12.6.4 VVP Section 5.4: Hardware V&V Processes, Activities, and Tasks
12.7 VVP Section 6: V&V reporting requirements
12.8 VVP Section 7: V&V administrative requirements
12.8.1 General
12.8.2 VVP Section 7.1: Anomaly resolution and reporting
12.8.3 VVP Section 7.2: Task iteration policy
12.8.4 VVP Section 7.3: Deviation policy
12.8.5 VVP Section 7.4: Control procedures
12.8.6 VVP Section 7.5: Standards, practices, and conventions
12.9 VVP Section 8: V&V test documentation requirements
Annex A (informative) Mapping of IEEE 1012 V&V activities and tasks
A.1 Mapping of ISO/IEC 15288 V&V requirements to IEEE 1012 V&V activities and tasks
A.2 Mapping of IEEE 1012 V&V activities to ISO/IEC 15288 system life cycle processes and activities
A.3 Mapping of ISO/IEC 12207 V&V requirements to IEEE 1012 V&V activities and tasks
A.4 Mapping of IEEE 1012 V&V activities to IEEE 12207 software life cycle processes and activities
Annex B (informative) A risk-based, integrity-level scheme
Annex C (informative) Definition of independent V&V (IV&V)
C.1 Technical independence
C.2 Managerial independence
C.3 Financial independence
C.4 Forms of independence
C.4.1 Classical IV&V
C.4.2 Modified IV&V
C.4.3 Integrated IV&V
C.4.4 Internal IV&V
C.4.5 Embedded V&V
Annex D (informative) V&V of reuse software
D.1 Purpose
D.2 V&V of software developed in a reuse process
D.2.1 V&V of assets in development
D.2.2 V&V of reused assets
D.3 V&V of software developed and reused outside of a reuse process
Annex E (informative) V&V measures
E.1 Introduction
E.2 Measures for evaluating anomaly density
E.3 Measures for evaluating V&V effectiveness
E.4 Measures for evaluating V&V efficiency
Annex F (informative) Example of V&V relationships to other project responsibilities
Annex G (informative) Optional V&V tasks
Annex H (informative) Environmental factors considerations
H.1 Introduction
H.2 In the agreement processes
H.3 In the organizational project-enabling processes
H.4 In the project processes
H.5 In the technical processes
Annex I (informative) V&V of system, software, and hardware integration
I.1 Introduction
I.2 Examples of system failures caused by integration issues
I.2.1 Year 2000 System Integration Issue
I.2.2 System architecture integration issues
I.3 System, software, and hardware interaction issues
Annex J (informative) Hazard, security, and risk analyses
J.1 Hazard analysis
Annex K (informative) Example of assigning and changing the system integrity level of “supporting system functions”
Annex L (informative) Mapping of ISO/IEC/IEEE 15288 and IEEE 12207 process outcomes to V&V tasks
Annex M (informative) Bibliography
Software Verification and Validation
IEEE Standard for System and
IEEE Computer Society
Software & Systems Engineering Standards Committee (C/S2ESC)
Sponsored by the
IEEE
3 Park Avenue
New York, NY 10016-5997
USA
25 May 2012
IEEE Std 1012™-2012
(Revision of
IEEE Std 1012-2004)
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IEEE Std 1012TM-2012
(Revision of
IEEE Std 1012-2004)
IEEE Standard for System and
Software Verification and Validation
Sponsor
Software & Systems Engineering Standards Committee (C/S2ESC)
of the
IEEE Computer Society
Approved 29 March 2012
IEEE-SA Standards Board
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Abstract: Verification and validation (V&V) processes are used to determine whether the
development products of a given activity conform to the requirements of that activity and whether
the product satisfies its intended use and user needs. V&V life cycle process requirements are
specified for different integrity levels. The scope of V&V processes encompasses systems,
software, and hardware, and it includes their interfaces. This standard applies to systems,
software, and hardware being developed, maintained, or reused [legacy, commercial off-the-shelf
(COTS), nondevelopmental items]. The term software also includes firmware and microcode, and
each of the terms system, software, and hardware includes documentation. V&V processes
include the analysis, evaluation, review, inspection, assessment, and testing of products.
Keywords: environmental verification and validation (V&V) factors, hardware V&V, IEEE 1012,
integrity level, independent V&V (IV&V), risk/hazard/security analyses, software life cycle,
software V&V, system life cycle, system V&V, V&V, V&V measures, V&V of reuse software
The Institute of Electrical and Electronics Engineers, Inc.
3 Park Avenue, New York, NY 10016-5997, USA
Copyright © 2012 by The Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published 25 May 2012. Printed in the United States of America.
IEEE is a registered trademark in the U.S. Patent & Trademark Office, owned by The Institute of Electrical and Electronics
Engineers, Incorporated.
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of the publisher.
ISBN 978-0-7381-7268-2
ISBN 978-0-7381-7374-0
STD97243
STDPD97243
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Patents
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Participants
At the time this standard was submitted to the IEEE-SA Standards Board for approval, the Std for
Software Verification and Validation Working Group (C/S2ESC/1012_WG) Working Group had the
following membership:
Roger U. Fujii, Chair
Kenneth A. Costello, Vice Chair
Edward A. Addy, Secretary
Uma Ferrell
Kevin R. Finlay
Eva Freund
Ron Greenthaler
Jon D. Hagar
George Hughes
Lisa A. Jensen
Lance Kelson
Thomas M. Kurihara
Carol Long
Charles R. Martin
Dan McCaugherty
Robert R. Moniri
James W. Moore
Kevin Morgan
Jeff Northey
Nitin Patel
Robert A. Peterson
Michael D. Prendergast
Laura Pullum
Steven R. Rakitin
Scott W. Schield
Raymond Senechal
Luca Spotorno
Eric Sylvania
Gina To
Hasso Von Bredow
Michael E. Waterman
Kurt Woodham
Steve Yang
Stephen Allott
Susan M. Burgess
Tiffany Burgess
William Burgess
Milton Concepcion
Darrell Cooksey
Paul D. Croll
David H. Daniel
Taz Daughtrey
Jon Davis
Ronald Dean
Josiah Devasirvatham
Harpal Dhama
Stephen Driskell
Christof Ebert
The following members of the individual balloting committee voted on this standard. Balloters may have
voted for approval, disapproval, or abstention.
Edward A. Addy
Johann Amsenga
T. Ankrum
Chris Bagge
Charles Barest
H. Stephen Berger
Juris Borzovs
Pieter Botman
Susan M. Burgess
Mark Bushnell
Juan Carreon
Sue Carroll
Lawrence Catchpole
Keith Chow
Darrell Cooksey
Kenneth A. Costello
Paul D. Croll
David H. Daniel
Geoffrey Darnton
Ronald Dean
Joseph Decuir
Thomas Dineen
Randall Dotson
Sourav Dutta
Andrew Fieldsend
Gregory Fleming
Andre Fournier
Eva Freund
David Friscia
Daniel Lindberg
Vincent Lipsio
Greg Luri
Wayne W. Manges
Edward Mccall
Dan McCaugherty
Robert R. Moniri
James W. Moore
Michael S. Newman
Warren Odess-Gillett
Robert A. Peterson
William Petit
Michael D. Prendergast
Iulian Profir
Laura Pullum
Steven Rakitin
Annette Reilly
Robert Robinson
Keith Roseberry
Terence Rout
Randall Safier
Bartien Sayogo
Robert Schaaf
Hans Schaefer
Scott W. Schield
David Schultz
Stephen Schwarm
Raymond Senechal
John Short
Roger U. Fujii
David Fuschi
Lewis Gray
Ron Greenthaler
J. Gregory
Randall Groves
Jon D. Hagar
John Harauz
Mark Henley
David Herrell
Rutger A. Heunks
Frank Hill
Werner Hoelzl
George Hughes
Peter Hung
Noriyuki Ikeuchi
Atsushi Ito
Mark Jaeger
Cheryl Jones
Anatol Kark
Piotr Karocki
Yuri Khersonsky
Dwayne Knirk
Thomas M. Kurihara
George Kyle
Susan Land
Claude Laporte
J. Dennis Lawrence
David Leciston
Copyright © 2012 IEEE. All rights reserved.
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