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vivado tcl 命令手册.pdf
Vivado Design Suite Tcl Command Reference Guide
Revision History
Ch. 1: Introduction
Overview of Tcl Capabilities in Vivado
Launching the Vivado Design Suite
Tcl Shell Mode
Tcl Batch Mode
Vivado IDE Mode
Tcl Journal Files
Tcl Help
Scripting in Tcl
Tcl Initialization Scripts
Sourcing a Tcl Script
Using Tcl.pre and Tcl.post Hook Scripts
General Tcl Syntax Guidelines
First Class Tcl Objects and Relationships
Object Types and Definitions
Querying Objects
Object Properties
Filtering Based on Properties
Handling Lists of Objects
Object Relationships
Errors, Warnings, Critical Warnings, and Info Messages
Ch. 2: Tcl Commands
Tcl Command Categories
Tcl Commands Listed by Category
Ch. 3: Tcl Commands Listed Alphabetically
add_bp
add_cells_to_pblock
add_condition
add_drc_checks
add_files
add_force
add_hw_hbm_pc
add_hw_probe_enum
add_peripheral_interface
add_wave
add_wave_divider
add_wave_group
add_wave_marker
add_wave_virtual_bus
all_clocks
all_cpus
all_dsps
all_fanin
all_fanout
all_ffs
all_hsios
all_inputs
all_latches
all_outputs
all_rams
all_registers
apply_bd_automation
apply_board_connection
apply_hw_ila_trigger
archive_project
assign_bd_address
auto_detect_xpm
boot_hw_device
calc_config_time
can_resolve_reference
check_syntax
check_timing
checkpoint_vcd
close_bd_design
close_design
close_hw
close_hw_target
close_project
close_saif
close_sim
close_vcd
close_wave_config
commit_hw_hbm
commit_hw_mig
commit_hw_sio
commit_hw_sysmon
commit_hw_vio
compile_c
compile_simlib
config_compile_simlib
config_design_analysis
config_hw_sio_gts
config_ip_cache
config_timing_analysis
config_timing_corners
config_webtalk
connect_bd_intf_net
connect_bd_net
connect_debug_cores
connect_debug_port
connect_hw_server
connect_net
convert_ips
convert_ngc
copy_bd_objs
copy_ip
copy_run
create_bd_addr_seg
create_bd_cell
create_bd_design
create_bd_intf_net
create_bd_intf_pin
create_bd_intf_port
create_bd_intf_tlm_port
create_bd_net
create_bd_pin
create_bd_port
create_bd_tlm_port
create_cell
create_clock
create_dashboard_gadget
create_debug_core
create_debug_port
create_drc_check
create_drc_ruledeck
create_drc_violation
create_fileset
create_generated_clock
create_gui_custom_command
create_gui_custom_command_arg
create_hw_axi_txn
create_hw_bitstream
create_hw_cfgmem
create_hw_device
create_hw_probe
create_hw_sio_link
create_hw_sio_linkgroup
create_hw_sio_scan
create_hw_sio_sweep
create_hw_target
create_interface
create_ip
create_ip_run
create_macro
create_net
create_partition_def
create_pblock
create_peripheral
create_pin
create_port
create_port_on_reconfigurable_module
create_pr_configuration
create_project
create_property
create_reconfig_module
create_report_config
create_rqs_run
create_run
create_slack_histogram
create_sysgen
create_waiver
create_wave_config
create_xps
current_bd_design
current_bd_instance
current_board
current_board_part
current_design
current_fileset
current_frame
current_hw_cfgmem
current_hw_device
current_hw_ila
current_hw_ila_data
current_hw_server
current_hw_target
current_instance
current_pr_configuration
current_project
current_run
current_scope
current_sim
current_time
current_vcd
current_wave_config
decrypt_bitstream
delete_bd_objs
delete_clock_networks_results
delete_dashboard_gadgets
delete_debug_core
delete_debug_port
delete_drc_check
delete_drc_ruledeck
delete_fileset
delete_hw_axi_txn
delete_hw_bitstream
delete_hw_cfgmem
delete_hw_probe
delete_hw_target
delete_interface
delete_ip_run
delete_macros
delete_partition_defs
delete_pblocks
delete_power_results
delete_pr_configurations
delete_reconfig_modules
delete_report_configs
delete_rpm
delete_runs
delete_timing_results
delete_utilization_results
delete_waivers
describe
detect_hw_sio_links
disconnect_bd_intf_net
disconnect_bd_net
disconnect_debug_port
disconnect_hw_server
disconnect_net
display_hw_ila_data
display_hw_sio_scan
encrypt
endgroup
exclude_bd_addr_seg
execute_hw_svf
export_as_example_design
export_bd_synth
export_ip_user_files
export_simulation
extract_files
filter
find_bd_objs
find_routing_path
find_top
flush_vcd
generate_base_platform
generate_mem_files
generate_pblock
generate_peripheral
generate_reports
generate_rl_platform
generate_shx_platform
generate_target
get_bd_addr_segs
get_bd_addr_spaces
get_bd_cells
get_bd_designs
get_bd_intf_nets
get_bd_intf_pins
get_bd_intf_ports
get_bd_nets
get_bd_pins
get_bd_ports
get_bel_pins
get_bels
get_board_bus_nets
get_board_buses
get_board_component_interfaces
get_board_component_modes
get_board_component_pins
get_board_components
get_board_interface_ports
get_board_ip_preferences
get_board_jumpers
get_board_parameters
get_board_part_interfaces
get_board_part_pins
get_board_parts
get_boards
get_cdc_violations
get_cells
get_cfgmem_parts
get_clock_regions
get_clocks
get_dashboard_gadgets
get_debug_cores
get_debug_ports
get_designs
get_drc_checks
get_drc_ruledecks
get_drc_violations
get_example_designs
get_files
get_filesets
get_generated_clocks
get_gui_custom_command_args
get_gui_custom_commands
get_hierarchy_separator
get_highlighted_objects
get_hw_axi_txns
get_hw_axis
get_hw_cfgmems
get_hw_devices
get_hw_hbms
get_hw_ila_datas
get_hw_ilas
get_hw_migs
get_hw_probes
get_hw_servers
get_hw_sio_commons
get_hw_sio_gtgroups
get_hw_sio_gts
get_hw_sio_iberts
get_hw_sio_linkgroups
get_hw_sio_links
get_hw_sio_plls
get_hw_sio_rxs
get_hw_sio_scans
get_hw_sio_sweeps
get_hw_sio_txs
get_hw_sysmon_reg
get_hw_sysmons
get_hw_targets
get_hw_vios
get_interfaces
get_io_standards
get_iobanks
get_ip_upgrade_results
get_ipdefs
get_ips
get_lib_cells
get_lib_pins
get_libs
get_macros
get_marked_objects
get_methodology_checks
get_methodology_violations
get_msg_config
get_net_delays
get_nets
get_nodes
get_objects
get_package_pins
get_param
get_partition_defs
get_parts
get_path_groups
get_pblocks
get_pins
get_pips
get_pkgpin_bytegroups
get_pkgpin_nibbles
get_ports
get_pplocs
get_pr_configurations
get_primitives
get_projects
get_property
get_reconfig_modules
get_report_configs
get_runs
get_scopes
get_selected_objects
get_simulators
get_site_pins
get_site_pips
get_sites
get_slrs
get_speed_models
get_stacks
get_template_bd_designs
get_tiles
get_timing_arcs
get_timing_paths
get_value
get_waivers
get_wave_configs
get_waves
get_wires
group_bd_cells
group_path
help
highlight_objects
implement_debug_core
implement_mig_cores
import_files
import_ip
import_synplify
import_xise
import_xst
include_bd_addr_seg
infer_diff_pairs
instantiate_example_design
instantiate_template_bd_design
iphys_opt_design
launch_chipscope_analyzer
launch_impact
launch_runs
launch_sdk
launch_simulation
limit_vcd
link_design
list_features
list_hw_samples
list_param
list_property
list_property_value
list_targets
load_features
lock_design
log_saif
log_vcd
log_wave
ltrace
make_bd_intf_pins_external
make_bd_pins_external
make_diff_pair_ports
make_wrapper
mark_objects
modify_debug_ports
move_bd_cells
move_dashboard_gadget
move_files
move_wave
open_bd_design
open_checkpoint
open_dsa
open_example_project
open_hw
open_hw_target
open_io_design
open_project
open_report
open_run
open_saif
open_vcd
open_wave_config
open_wave_database
opt_design
pause_hw_hbm_amon
phys_opt_design
place_cell
place_design
place_pblocks
place_ports
platform_verify
power_opt_design
pr_recombine
pr_subdivide
pr_verify
program_hw_cfgmem
program_hw_devices
ptrace
read_bd
read_checkpoint
read_csv
read_edif
read_hw_ila_data
read_hw_sio_scan
read_hw_sio_sweep
read_ip
read_iphys_opt_tcl
read_mem
read_saif
read_schematic
read_twx
read_verilog
read_vhdl
read_xdc
readback_hw_cfgmem
readback_hw_device
redo
refresh_design
refresh_hw_axi
refresh_hw_device
refresh_hw_hbm
refresh_hw_mig
refresh_hw_server
refresh_hw_sio
refresh_hw_sysmon
refresh_hw_target
refresh_hw_vio
refresh_meminit
regenerate_bd_layout
register_proc
reimport_files
relaunch_sim
remove_bps
remove_cell
remove_cells_from_pblock
remove_conditions
remove_drc_checks
remove_files
remove_forces
remove_gui_custom_command_args
remove_gui_custom_commands
remove_hw_hbm_pc
remove_hw_probe_enum
remove_hw_sio_link
remove_hw_sio_linkgroup
remove_hw_sio_scan
remove_hw_sio_sweep
remove_net
remove_pin
remove_port
remove_wave
rename_cell
rename_net
rename_pin
rename_port
rename_ref
reorder_files
replace_bd_cell
report_bd_diffs
report_bps
report_bus_skew
report_carry_chains
report_cdc
report_clock_interaction
report_clock_networks
report_clock_utilization
report_clocks
report_compile_order
report_conditions
report_config_timing
report_control_sets
report_datasheet
report_debug_core
report_design_analysis
report_disable_timing
report_drc
report_drivers
report_environment
report_exceptions
report_frames
report_high_fanout_nets
report_hw_axi_txn
report_hw_mig
report_hw_targets
report_incremental_reuse
report_io
report_ip_status
report_methodology
report_objects
report_operating_conditions
report_param
report_phys_opt
report_pipeline_analysis
report_power
report_power_opt
report_pr_configuration_analysis
report_property
report_pulse_width
report_qor_assessment
report_qor_suggestions
report_ram_utilization
report_route_status
report_scopes
report_sdx_utilization
report_sim_device
report_simlib_info
report_ssn
report_stacks
report_switching_activity
report_synchronizer_mtbf
report_timing
report_timing_summary
report_transformed_primitives
report_utilization
report_values
report_waivers
reset_drc
reset_drc_check
reset_hw_axi
reset_hw_ila
reset_hw_vio_activity
reset_hw_vio_outputs
reset_methodology
reset_methodology_check
reset_msg_config
reset_msg_count
reset_operating_conditions
reset_param
reset_project
reset_property
reset_runs
reset_simulation
reset_ssn
reset_switching_activity
reset_target
reset_timing
resize_net_bus
resize_pblock
resize_pin_bus
resize_port_bus
restart
resume_hw_hbm_amon
route_design
run
run_hw_axi
run_hw_hbm_amon
run_hw_ila
run_hw_sio_scan
run_hw_sio_sweep
run_state_hw_jtag
runtest_hw_jtag
save_bd_design
save_bd_design_as
save_constraints
save_constraints_as
save_project_as
save_wave_config
scan_dr_hw_jtag
scan_ir_hw_jtag
select_objects
select_wave_objects
set_bus_skew
set_case_analysis
set_clock_groups
set_clock_latency
set_clock_sense
set_clock_uncertainty
set_data_check
set_delay_model
set_disable_timing
set_external_delay
set_false_path
set_hierarchy_separator
set_hw_sysmon_reg
set_input_delay
set_input_jitter
set_load
set_logic_dc
set_logic_one
set_logic_unconnected
set_logic_zero
set_max_delay
set_max_time_borrow
set_min_delay
set_msg_config
set_multicycle_path
set_operating_conditions
set_output_delay
set_package_pin_val
set_param
set_part
set_power_opt
set_propagated_clock
set_property
set_speed_grade
set_switching_activity
set_system_jitter
set_units
set_value
setup_ip_static_library
setup_pr_configurations
show_objects
show_schematic
split_diff_pair_ports
start_gui
start_vcd
startgroup
step
stop
stop_gui
stop_hw_hbm_amon
stop_hw_sio_scan
stop_hw_sio_sweep
stop_vcd
swap_locs
synth_design
synth_ip
tie_unused_pins
undo
ungroup_bd_cells
unhighlight_objects
unmark_objects
unplace_cell
unregister_proc
unselect_objects
update_clock_routing
update_compile_order
update_design
update_files
update_hw_firmware
update_hw_gpio
update_ip_catalog
update_macro
update_module_reference
update_timing
upgrade_bd_cells
upgrade_ip
upload_hw_ila_data
validate_bd_design
validate_dsa
validate_ip
verify_hw_devices
version
wait_on_hw_ila
wait_on_hw_sio_scan
wait_on_hw_sio_sweep
wait_on_run
write_bd_layout
write_bd_tcl
write_bitstream
write_bmm
write_bsdl
write_cfgmem
write_checkpoint
write_csv
write_debug_probes
write_dsa
write_dsa_rom
write_edif
write_hw_ila_data
write_hw_sio_scan
write_hw_sio_sweep
write_hw_svf
write_hwdef
write_ibis
write_inferred_xdc
write_ip_tcl
write_iphys_opt_tcl
write_mem_info
write_peripheral
write_project_tcl
write_schematic
write_sdf
write_sysdef
write_verilog
write_vhdl
write_waivers
write_xdc
xsim
Appx. A: Additional Resources and Legal Notices
Vivado Design Suite Tcl
Command Reference Guide
UG835 (v2018.3) December 5, 2018
Revision History
Revision History
The following table shows the revision history for this document:
Section
Revision Summary
12/5/2018 v2018.3
add_hw_hbm_pc, create_bd_intf_tlm_port, create_bd_tlm_port,
create_dashboard_gadget, delete_dashboard_gadgets, get_dashboard_gadgets,
move_dashboard_gadget, open_dsa, pause_hw_hbm_amon, pr_recombine,
pr_subdivide, remove_hw_hbm_pc, report_bd_diffs, reset_runs,
resume_hw_hbm_amon, run_hw_hbm_amon, stop_hw_hbm_amon, write_dsa
create_bd_cell, create_ip, create_waiver, current_time, get_bd_designs,
get_speed_models, get_waivers, group_path, iphys_opt_design, link_design,
open_checkpoint, open_wave_database, opt_design, phys_opt_design,
read_iphys_opt_tcl, report_bus_skew, report_clock_utilization,
report_design_analysis, report_ip_status, report_methodology, report_power,
report_qor_suggestions, report_timing, report_timing_summary, save_project_as,
update_hw_firmware, write_checkpoint, write_iphys_opt_tcl, write_ip_tcl,
write_waivers, xsim
06/06/2018 v2018.2
create_bd_intf_tlm_port, create_bd_tlm_port, implement_xphy_cores
config_ip_cache, export_ip_user_files, export_simulation,
make_bd_intf_pins_external, make_bd_pins_external, place_design,
report_pipeline_analysis, report_qor_suggestions, report_timing,
report_timing_summary, report_utilization, update_hw_firmware,
validate_bd_design, write_bd_tcl, write_sdf
04/04/2018 v2018.1
commit_hw_hbm, create_gui_custom_command,
create_gui_custom_command_arg, create_port_on_reconfigurable_module,
create_rqs_run, current_dashboard, generate_platform, get_dashboards,
get_gui_custom_command_args, get_gui_custom_commands, get_hw_hbms,
refresh_hw_hbm, refresh_meminit, remove_gui_custom_command_args,
remove_gui_custom_commands, write_ip_tcl
check_timing, config_ip_cache, create_hw_axi_txn, create_slack_histogram,
create_waiver, delete_waivers, get_files, get_filesets, get_pblocks,
get_reconfig_modules, get_runs, get_waivers, group_path, log_wave,
open_hw_target, opt_design, phys_opt_design, pr_verify, program_hw_devices,
read_checkpoint, refresh_hw_device, refresh_hw_server, refresh_hw_target,
report_bus_skew, report_carry_chains, report_cdc, report_clock_interaction,
report_compile_order, report_debug_core, report_design_analysis, report_drc,
report_exceptions, report_methodology, report_pulse_width, report_route_status,
report_timing, report_timing_summary, report_utilization, report_waivers,
route_design, synth_design, upgrade_ip, write_bd_tcl, write_checkpoint,
write_dsa_rom, write_waivers, write_xdc, xsim
Commands Added in 2018.3
Commands Modified in 2018.3
Commands Added in 2018.2
Commands Modified in 2018.2
Commands Added in 2018.1
Commands Modified in 2018.1
UG835 (v2018.3) December 5, 2018
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Introduction
Chapter 1
Overview of Tcl Capabilities in Vivado
The Tool Command Language (Tcl) is the scripting language integrated in the Vivado® tool
environment. Tcl is a standard language in the semiconductor industry for application
programming interfaces, and is used by Synopsys® Design Constraints (SDC).
SDC is the mechanism for communicating timing constraints for FPGA synthesis tools from
Synopsys Synplify as well as other vendors, and is a timing constraint industry standard;
consequently, the Tcl infrastructure is a “Best Practice” for scripting language.
Tcl lets you perform interactive queries to design tools in addition to executing automated
scripts. Tcl offers the ability to “ask” questions interactively of design databases, particularly
around tool and design settings and state. Examples are: querying specific timing analysis
reporting commands live, applying incremental constraints, and performing queries immediately
after to verify expected behavior without re-running any tool steps.
The following sections describe some of the basic capabilities of Tcl with Vivado.
Note: This manual is not a comprehensive reference for the Tcl language. It is a reference to the specific
capabilities of the Vivado Design Suite Tcl shell, and provides reference to additional Tcl programming
resources.
Launching the Vivado Design Suite
You can launch the Vivado Design Suite and run the tools using different methods depending on
your preference. For example, you can choose a Tcl script-based compilation style method in
which you manage sources and the design process yourself, also known as Non-Project Mode.
Alternatively, you can use a project-based method to automatically manage your design process
and design data using projects and project states, also known as Project Mode. Either of these
methods can be run using a Tcl scripted batch mode or run interactively in the Vivado IDE. For
more information on the different design flow modes, see the Vivado Design Suite User Guide:
Design Flows Overview (UG892).
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Chapter 1: Introduction
Tcl Shell Mode
If you prefer to work directly with Tcl commands, you can interact with your design using Tcl
commands with one of the following methods:
• Enter individual Tcl commands in the Vivado Design Suite Tcl shell outside of the Vivado IDE.
• Enter individual Tcl commands in the Tcl Console at the bottom of the Vivado IDE.
• Run Tcl scripts from the Vivado Design Suite Tcl shell.
• Run Tcl scripts from the Vivado IDE.
Use the following command to invoke the Vivado Design Suite Tcl shell either at the Linux
command prompt or within a Windows Command Prompt window:
vivado -mode tcl
TIP: On Windows, you can also select Start → All Programs → Xilinx Design Tools → Vivado yyyy.x →
Vivado yyyy.x Tcl Shell, where “yyyy.x” is the installed version of Vivado.
For more information about using Tcl and Tcl scripting, see the Vivado Design Suite User Guide:
Using the Tcl Scripting Capabilities (UG894). For a step-by-step tutorial that shows how to use Tcl
in the Vivado tool, see the Vivado Design Suite Tutorial: Design Flows Overview (UG888).
Tcl Batch Mode
You can use the Vivado tools in batch mode by supplying a Tcl script when invoking the tool. Use
the following command either at the Linux command prompt or within a Windows Command
Prompt window:
vivado -mode batch -source
The Vivado Design Suite Tcl shell will open, run the specified Tcl script, and exit when the script
completes. In batch mode, you can queue up a series of Tcl scripts to process a number of
designs overnight through synthesis, simulation, and implementation, and review the results on
the following morning.
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Chapter 1: Introduction
Vivado IDE Mode
You can launch the Vivado Design Suite and run the tools using different methods depending on
your preference. For example, you can choose a Tcl script-based compilation style method in
which you manage sources and the design process yourself, also known as Non-Project Mode.
Alternatively, you can use a project-based method to automatically manage your design process
and design data using projects and project states, also known as Project Mode. Either of these
methods can be run using a Tcl scripted batch mode or run interactively in the Vivado IDE. For
more information on the different design flow modes, see the Vivado Design Suite User Guide:
Design Flows Overview (UG892).
If you prefer to work in a GUI, you can launch the Vivado IDE from Windows or Linux. For more
information on the Vivado IDE, see the Vivado Design Suite User Guide: Using the Vivado IDE
(UG893).
Launch the Vivado IDE from your working directory. By default the Vivado journal and log files,
and any generated report files, are written to the directory from which the Vivado tool is
launched. This makes it easier to locate the project file, log files, and journal files, which are
written to the launch directory.
In the Windows OS, select Start → All Programs → Xilinx Design Tools → Vivado yyyy.x → Vivado
yyyy.x Tcl Shell, where “yyyy.x” is the installed version of Vivado.
TIP: You can also double-click the Vivado IDE shortcut icon on your Windows desktop.
In the Linux OS, enter the following command at the command prompt:
vivado -or- vivado -mode gui
If you need help, with the Vivado tool command line executable, type:
vivado -help
If you are running the Vivado tool from the Vivado Design Suite Tcl shell, you can open the
Vivado IDE directly from the Tcl shell by using the start_gui command.
From the Vivado IDE, you can close the Vivado IDE and return to a Vivado Tcl shell by using the
stop_gui command.
Tcl Journal Files
When you invoke the Vivado tool, it writes the vivado.log file to record the various
commands and operations performed during the design session. The Vivado tool also writes a file
called vivado.jou which is a journal of just the Tcl commands run during the session. The
journal file can be used as a source to create new Tcl scripts.
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Chapter 1: Introduction
Note: Backup versions of the journal file, named vivado_.backup.jou, are written to save the
details of prior runs whenever the Vivado tool is launched. The is a unique identifier that allow the
tool to create and store multiple backup versions of the log and journal files.
Tcl Help
The Tcl help command provides information related to the supported Tcl commands.
• help – Returns a list of Tcl command categories.
help
Command categories are groups of commands performing a specific function, like File I/O for
instance.
• help -category category – Returns a list of commands found in the specified category.
help -category object
This example returns the list of Tcl commands for handling objects.
• help pattern – Returns a list of commands that match the specified search pattern. This
form can be used to quickly locate a specific command from a group of commands.
help get_*
This example returns the list of Tcl commands beginning with get_.
• help command – Provides detailed information related to the specified command.
help get_cells
This example returns specific information of the get_cells command.
• help -args command – Provides an abbreviated help text for the specified command,
including the command syntax and a brief description of each argument.
help -args get_cells
• help -syntax command – Reports the command syntax for the specified command.
help -syntax get_cells
Scripting in Tcl
Tcl Initialization Scripts
TIP: The following describes where you can place Vivado_init.tcl scripts if you would like to
customize Vivado on startup. No Vivado_init.tcl scripts are provided in the Vivado release by
default.
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Chapter 1: Introduction
When you start the Vivado tool, it looks for a Tcl initialization script in three different locations,
each one overriding the last one found:
1. Enterprise: In the software installation directory, installdir/Vivado/version/
scripts/Vivado_init.tcl
2. Vivado Version: In a local user directory, for a specific version of the Vivado Design Suite:
• For Windows 7: %APPDATA%/Xilinx/Vivado/version/Vivado_init.tcl
• For Linux: $HOME/.Xilinx/Vivado/version/Vivado_init.tcl
3. Vivado User: In a local user directory, for the general Vivado Design Suite:
• For Windows 7: %APPDATA%/Xilinx/Vivado/Vivado_init.tcl
• For Linux: $HOME/.Xilinx/Vivado/Vivado_init.tcl
Where:
• installdir is the installation directory where the Vivado Design Suite is installed.
If Vivado_init.tcl exists, in one or all of these locations, the Vivado tool sources this file, in
the order described above.
• The Vivado_init.tcl file in the installation directory allows a company or design group to
support a common initialization script for all users. Anyone starting the Vivado tool from that
installation location sources the enterprise Vivado_init.tcl script.
• A user's Vivado_init.tcl file in the home directory allows each user to specify additional
commands, or to override commands from the software installation to meet their specific
design requirements.
• No Vivado_init.tcl file is provided with the Vivado Design Suite installation. You must
create the Vivado_init.tcl file and place it in either the installation directory, or your
home directory, as discussed to meet your specific needs.
TIP: Other tools in the Vivado Design Suite also support initialization scripts in the following form:
tool_init.tcl, where tool can include Vivado, vivado_lab, xsim, and xelab.
The Vivado_init.tcl file is a standard Tcl command file that can contain any valid Tcl
command supported by the Vivado tool. You can also source another Tcl script file from within
Vivado_init.tcl by adding the following statement:
source path_to_file/file_name.tcl
Note: You can also specify the -init option when launching the Vivado Design Suite from the command
line. Type vivado -help for more information.
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Chapter 1: Introduction
Sourcing a Tcl Script
A Tcl script can be sourced from either one of the command-line options or from the GUI. Within
the Vivado Integrated Design Environment (IDE) you can source a Tcl script from Tools → Run Tcl
Script.
You can source a Tcl script from a Tcl command-line option:
source file_name
When you invoke a Tcl script from the Vivado IDE, a progress bar is displayed and all operations
in the IDE are blocked until the scripts completes.
There is no way to interrupt script execution during run time; consequently, standard OS
methods of killing a process must be used to force interruption of the tool. If the process is killed,
you lose any work done since your last save.
Typing help source in the Tcl console will provide additional information regarding the
source command.
Using Tcl.pre and Tcl.post Hook Scripts
Tcl Hook scripts allow you to run custom Tcl scripts prior to (tcl.pre) and after (tcl.post)
synthesis and implementation design runs, or any of the implementation steps. Whenever you
launch a run, the Vivado tool uses a predefined Tcl script which executes a design flow based on
the selected strategy. Tcl Hook scripts let you customize the standard flow, with pre-processors
or post-processors, such as for generating custom reports. The Tcl Hook script must be a
standard Tcl script.
Every step in the design flow has a pre- and post-hook capability. Common examples are:
• Custom reports: timing, power, utilization, or any user-defined tcl report.
• Temporary parameters for workarounds.
• Over-constraining timing constraints for portions of the flow.
• Multiple iterations of stages (e.g. multiple calls to phys_opt_design).
• Modifications to netlist, constraint, or device programming.
IMPORTANT! Relative paths within the tcl.pre and tcl.post scripts are relative to the appropriate run
directory of the project they are applied to: //. You
can use the DIRECTORY property of the current project or current run to define the relative paths in
your Tcl hook scripts:
get_property DIRECTORY [current_project] get_property DIRECTORY
[current_run]
For more information on defining Tcl Hook scripts, refer to the Vivado Design Suite User Guide:
Using Tcl Scripting (UG894).
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