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GV7601 SDI解码芯片 DATASHEET.pdf
Key Features
Applications
Description
1. Pin Out
1.1 Pin Assignment
1.2 Pin Descriptions
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 Recommended Operating Conditions
2.3 DC Electrical Characteristics
2.4 AC Electrical Characteristics
3. Input/Output Circuits
4. Detailed Description
4.1 Functional Overview
4.2 Serial Digital Input
4.3 Serial Digital Output
4.4 Serial Digital Reclocker
4.4.1 Reclocker PLL Loop Bandwidth
4.5 External Crystal/Reference Clock
4.6 Lock Detect
4.6.1 Asynchronous Lock
4.6.2 Signal Interruption
4.7 Video Functionality
4.7.1 Standard Definition Video Output Formats
4.7.2 High Definition Video Output Formats
4.7.3 Descrambling and Word Alignment
4.8 Parallel Video Data Outputs DOUT[19:0] and DOUT[9:0]
4.8.1 Parallel Data Bus Buffers
4.8.2 Parallel Output in Video Mode
4.8.3 Parallel Output in ASI Mode
4.8.4 Parallel Output In Data-Through Mode
4.8.5 Parallel Output Clock (PCLK)
4.8.6 DDR Parallel Clock Timing
4.9 Timing Signal Generator
4.10 Programmable Multi-function Outputs
4.11 H:V:F Timing Signal Generation
4.11.1 CEA-861 Timing Generation
4.12 Automatic Video Standards Detection
4.13 EDH Detection
4.13.1 EDH Packet Detection
4.13.2 EDH Flag Detection
4.14 Video Signal Error Detection & Indication
4.14.1 TRS Error Detection
4.14.2 Line Based CRC Error Detection
4.14.3 EDH CRC Error Detection
4.14.4 HD Line Number Error Detection
4.15 Ancillary Data Detection & Indication
4.15.1 Programmable Ancillary Data Detection
4.15.2 Ancillary Data Checksum Error
4.16 Video Error Correction
4.16.1 TRS Correction & Insertion
4.16.2 Line Based CRC Correction & Insertion
4.16.3 Line Number Error Correction & Insertion
4.16.4 Ancillary Data Checksum Error Correction & Insertion
4.16.5 EDH CRC Correction & Insertion
4.16.6 Illegal Word Remapping
4.16.7 TRS and Ancillary Data Preamble Remapping
4.16.8 Ancillary Data Extraction
4.17 Audio De-embedder
4.17.1 Serial Audio Data I/O Signals
4.17.2 Serial Audio Data Format Support
4.17.3 Audio Processing
4.17.4 Error Reporting
4.18 Gennum Serial Peripheral Interface
4.18.1 Command Word Description
4.18.2 Data Read or Write Access
4.18.3 GSPI Timing
4.19 Host Interface Register Maps
4.19.1 Video Core Registers
4.19.2 SD Audio Core
4.19.3 HD Audio Core Registers
4.20 JTAG Test Operation
4.21 Device Power-up
4.22 Device Reset
4.23 Standby Mode
5. References & Relevant Standards
6. Package & Ordering Information
6.1 Package Dimensions
6.2 Packaging Data
6.3 Marking Diagram
6.4 Solder Reflow Profiles
6.5 Ordering Information
GV7601 Aviia™ Receiver Data Sheet
Key Features
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SD 525i and 625i
Serial digital video receiver for standard and high
definition component video:
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• HD 720p 24, 25, 30, 50 and 60
• HD 1080i 50, 60
• HD 1080p 24, 25, 30, 50 and 60
Supports 8-bit, 10-bit or 12-bit component digital
video:
• RGB or YCbCr 4:4:4 sampled
• YCbCr 4:2:2 or 4:2:0 sampled
Integrated cable equalizer for long reach cable
performance
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230m typical HD performance over high-quality 75Ω
coaxial cable (Belden 1694A or equivalent)
160m typical HD performance over RG59 or
equivalent 75Ω coaxial cable
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Serial digital loop-though output
Integrated audio de-embedder for the extraction of up
to 8 channels of 48kHz digital audio
Supports IEC 13818-1 compliant transport streams
over the Asynchronous Serial Interface (ASI)
• Automatic selection between SD/HD component video
and ASI input data
• Ancillary (ANC) data detection and extraction
• User selectable processing features, including:
•
Timing Reference Signal (TRS) error detection and
correction
Line number and CRC error detection and correction
Illegal video code word re-mapping
• ANC data checksum error detection and correction
• Programmable ANC data detection
•
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4-wire Gennum Serial Peripheral Interface (GSPI) for
external host command and control
JTAG test interface
1.2V core and 3.3V analog voltage power supplies
1.8V or 3.3V selectable digital I/O power supply
Small footprint 100-BGA (11mm x 11mm)
Low power operation, typically 570mW at HD
Pb-free and RoHS compliant
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Applications
• Digital video recorders (DVR)
• Video servers
• Video mixers and switchers
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• Video framegrabbers
• Camcorders
• Video monitors & displays
Image capture devices
Description
The GV7601 is a serial digital video receiver for standard
and high definition component video, operating at
270Mb/s, 1.485Gb/s and 2.97Gb/s data rates. With
integrated cable equalizer technology, the GV7601 is
capable of receiving digital video over 75Ω coaxial cable at
lengths up to 460m for standard definition video, and up to
230m for high definition. This provides a complete receive
solution for the transmission of both interlaced and
progressive component digital video, up to 1920 x 1080, in
coaxial cable-based video systems.
Using the GV7601 with the complete Aviia™ receiver
reference design, it is possible to implement an all-digital,
bi-directional multimedia interface over coax. This
interface allows both DC power and a bi-directional,
half-duplex, auxiliary data interface to be carried over the
same single, robust and cost effective coaxial cable as the
high-speed serial digital video. The GV7601 also provides a
re-timed serial digital output for video loop-through
applications.
The GV7601 includes a broad range of user-selectable
processing features, such as Timing Reference Signal (TRS)
error detection and extraction, illegal code word
re-mapping, and ancillary data packet extraction. The
content of ancillary data packets, embedded by an Aviia
transmitter, can be extracted and retrieved via the host
interface. Device configuration and status reporting is
accomplished via the Gennum Serial Peripheral Interface
(GSPI). Alternatively, many processing features and
GV7601 Aviia™ Receiver
Data Sheet
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operational modes can be configured directly through
external pin settings.
The device can output both 8-bit, 10-bit and 12-bit video
data, for RGB or YCbCr 4:4:4, and YCbCr 4:2:2 or 4:2:0. A
configurable 20-bit wide parallel digital video output bus is
provided, with associated pixel clock and timing signal
outputs. The GV7601 supports ITU-R BT.656 SD formats,
and HD formats conforming to ITU-R BT.709 and BT.1120-6
for 1125-line formats, and SMPTE 296M for 750-line
formats. The device may also be configured to output
CEA-861 timing.
The GV7601 audio de-embedding function allows the up to
8 channels of serial digital audio within the ancillary data
space of the video data stream to be extracted. The audio
output signal formats supported by the device include
AES/EBU for professional applications, S/PDIF, and I2S.
16-bit, 20-bit and 24-bit audio formats are supported at
48kHz synchronous-to-video for SD video formats and
48kHz synchronous or asynchronous for HD formats.
Additional audio processing features include: individual
channel extraction, audio group selection, group
replacement, channel swapping and audio channel status
extraction.
The GV7601 also supports an Asynchronous Serial
Interface (ASI) 270Mb/s input, carrying compressed audio
and video transport streams, conforming to IEC 13818-1.
Transport stream data is output from the device at a
synchronous 27MHz clock rate. The device will
automatically deserialize and 8b/10b decode the data.
Packaged in a space saving 100-BGA, the GV7601 is ideal
for designs where high-density component placement is
required. Typically requiring only 570mW power, the
device can be used as a high bandwidth alternative to
analog composite or component video interfaces, providing
a high quality, all-digital, long reach video receive solution.
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Crystal
Buffer/
Oscillator
Data
Re-timer
Serial to
Parallel
Conversion
Serial Video
Descrambler,
Word Alignment
& Flywheel
ASI Sync Detect,
Word Alignment &
8b/10b Decode
Audio
De-embedder
and
Audio Clock
Generation
MCLK
ACLK
WCLK
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
Error
Detection,
ANC Data
Extraction
TRS, Line
Number, CRC
and EDH
Insertion
Video/Data
Buffer
DOUT[19:0]
PCLK
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Host Interface &
JTAG Test
I/O Control
STAT[5:0]
AGC
AGC
SDI
SDI
SDO_EN
SDO
SDO
RECLK_EN
Cable
Equalizer
Output
Buffer &
Mux
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Figure A: GV7601 Block Diagram
GV7601 Aviia™ Receiver
Data Sheet
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Revision History
Version
ECR
Date
Changes and / or Modifications
4
3
2
1
0
152345
August 2009
Modified Key Features, Description, Table 2-3,
Table 2-4 and Table 4-1.
152159
June 2009
151833
May 2009
151651
April 2009
Modified Section 4.11.1.1, Section 4.12,
Section 4.17.4, Section 4.19, and Table 4-33.
Added Figure 4-64.
Changed 6.3 Marking Diagram.
Re-ordered the DOUT[19:10] & DOUT[9:0] in
Table 1-1 to reflect the pin names.
Changed Figure 4-41.
Changed DOUT[18_10] and DOUT[9:0] pin
descriptions.
Changed 4.16.8 Ancillary Data Extraction and
its registers.
151484
February 2009
New document.
Contents
Key Features........................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
1. Pin Out...............................................................................................................................................................9
1.1 Pin Assignment ..................................................................................................................................9
1.2 Pin Descriptions ................................................................................................................................9
2. Electrical Characteristics ......................................................................................................................... 16
2.1 Absolute Maximum Ratings ....................................................................................................... 16
2.2 Recommended Operating Conditions .................................................................................... 16
2.3 DC Electrical Characteristics ..................................................................................................... 17
2.4 AC Electrical Characteristics ..................................................................................................... 19
3. Input/Output Circuits ............................................................................................................................... 28
4. Detailed Description.................................................................................................................................. 32
4.1 Functional Overview .................................................................................................................... 32
4.2 Serial Digital Input ........................................................................................................................ 32
4.3 Serial Digital Output ..................................................................................................................... 33
4.4 Serial Digital Reclocker ............................................................................................................... 33
4.4.1 Reclocker PLL Loop Bandwidth.................................................................................... 34
4.5 External Crystal/Reference Clock ........................................................................................... 34
4.6 Lock Detect ...................................................................................................................................... 35
4.6.1 Asynchronous Lock .......................................................................................................... 36
4.6.2 Signal Interruption............................................................................................................ 36
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4.7 Video Functionality ...................................................................................................................... 37
4.7.1 Standard Definition Video Output Formats ............................................................. 37
4.7.2 High Definition Video Output Formats...................................................................... 40
4.7.3 Descrambling and Word Alignment ........................................................................... 51
4.8 Parallel Video Data Outputs DOUT[19:0] and DOUT[9:0] ................................................ 51
4.8.1 Parallel Data Bus Buffers................................................................................................. 51
4.8.2 Parallel Output in Video Mode ..................................................................................... 55
4.8.3 Parallel Output in ASI Mode .......................................................................................... 55
4.8.4 Parallel Output In Data-Through Mode ..................................................................... 56
4.8.5 Parallel Output Clock (PCLK)......................................................................................... 56
4.8.6 DDR Parallel Clock Timing............................................................................................. 57
4.9 Timing Signal Generator ............................................................................................................. 58
4.10 Programmable Multi-function Outputs ............................................................................... 59
4.11 H:V:F Timing Signal Generation ............................................................................................ 60
4.11.1 CEA-861 Timing Generation ....................................................................................... 62
4.12 Automatic Video Standards Detection ................................................................................ 73
4.13 EDH Detection .............................................................................................................................. 75
4.13.1 EDH Packet Detection ................................................................................................... 76
4.13.2 EDH Flag Detection ........................................................................................................ 76
4.14 Video Signal Error Detection & Indication ......................................................................... 77
4.14.1 TRS Error Detection........................................................................................................ 78
4.14.2 Line Based CRC Error Detection ................................................................................ 78
4.14.3 EDH CRC Error Detection............................................................................................. 79
4.14.4 HD Line Number Error Detection .............................................................................. 79
4.15 Ancillary Data Detection & Indication ................................................................................. 79
4.15.1 Programmable Ancillary Data Detection................................................................ 82
4.15.2 Ancillary Data Checksum Error ................................................................................. 82
4.16 Video Error Correction .............................................................................................................. 83
4.16.1 TRS Correction & Insertion........................................................................................... 84
4.16.2 Line Based CRC Correction & Insertion ................................................................... 84
4.16.3 Line Number Error Correction & Insertion ............................................................. 85
4.16.4 Ancillary Data Checksum Error Correction & Insertion .................................... 85
4.16.5 EDH CRC Correction & Insertion ............................................................................... 85
4.16.6 Illegal Word Remapping............................................................................................... 85
4.16.7 TRS and Ancillary Data Preamble Remapping...................................................... 86
4.16.8 Ancillary Data Extraction............................................................................................. 86
4.17 Audio De-embedder ................................................................................................................... 91
4.17.1 Serial Audio Data I/O Signals...................................................................................... 91
4.17.2 Serial Audio Data Format Support ............................................................................ 93
4.17.3 Audio Processing............................................................................................................. 97
4.17.4 Error Reporting ..............................................................................................................101
4.18 Gennum Serial Peripheral Interface ...................................................................................102
4.18.1 Command Word Description ....................................................................................102
4.18.2 Data Read or Write Access.........................................................................................103
4.18.3 GSPI Timing.....................................................................................................................104
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4.19 Host Interface Register Maps ................................................................................................106
4.19.1 Video Core Registers....................................................................................................106
4.19.2 SD Audio Core................................................................................................................113
4.19.3 HD Audio Core Registers............................................................................................125
4.20 JTAG Test Operation ................................................................................................................137
4.21 Device Power-up .......................................................................................................................139
4.22 Device Reset ................................................................................................................................139
4.23 Standby Mode ............................................................................................................................139
5. References & Relevant Standards .......................................................................................................140
6. Package & Ordering Information ........................................................................................................141
6.1 Package Dimensions ...................................................................................................................141
6.2 Packaging Data .............................................................................................................................142
6.3 Marking Diagram .........................................................................................................................142
6.4 Solder Reflow Profiles ................................................................................................................143
6.5 Ordering Information .................................................................................................................143
GV7601 Aviia™ Receiver
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List of Tables
Table 1-1: Pin Descriptions ............................................................................................................................ 9
Table 2-1: Absolute Maximum Ratings................................................................................................... 16
Table 2-2: Recommended Operating Conditions................................................................................ 16
Table 2-3: DC Electrical Characteristics ................................................................................................. 17
Table 2-4: AC Electrical Characteristics ................................................................................................. 19
Table 4-1: Typical Cable Length Performance ..................................................................................... 32
Table 4-2: Serial Digital Output................................................................................................................. 33
Table 4-3: PLL Loop Bandwidth ................................................................................................................ 34
Table 4-4: Input Clock Requirements...................................................................................................... 35
Table 4-5: Lock Detect Conditions............................................................................................................ 36
Table 4-6: 525/60Hz Format....................................................................................................................... 37
Table 4-7: 625/50Hz Format....................................................................................................................... 39
Table 4-8: 1080-line Interlaced Horizontal Timing ............................................................................ 41
Table 4-9: 1080-line Progressive Horizontal Timing.......................................................................... 43
Table 4-10: 720p Horizontal Timing ........................................................................................................ 43
Table 4-11: Full HD 1080-line and 720-line Progressive Image Formats.................................... 44
Table 4-12: 1080p Y'C'BC'R 4:2:0 & 4:2:2 10-bit Bit Structure Mapping........................................ 45
Table 4-13: 1080p R'G'B' or Y'C'BC'R 4:4:4 10-bit Bit Structure Mapping ..................................... 46
Table 4-14: 1080p R'G'B' or Y'C'BC'R 4:4:4 12-bit Bit Structure Mapping ..................................... 48
Table 4-15: 1080p Y'C'BC'R 4:2:2 12-bit Bit Structure Mapping ...................................................... 49
Table 4-16: 720p R'G'B' or Y'C'BC'R 4:4:4 10-bit Bit Structure Mapping........................................ 51
Table 4-17: GV7601 Output Video Data Format Selections ............................................................ 54
Table 4-18: GV7601 PCLK Output Rates ................................................................................................ 56
Table 4-19: Output Signals Available on Programmable Multi-Function Pins ......................... 59
Table 4-20: Supported CEA-861 Formats .............................................................................................. 62
Table 4-21: Supported Video Standard Codes ..................................................................................... 74
Table 4-22: Video Error Status Register and Error Disable Mask Bits .......................................... 78
Table 4-23: PROC_DISABLE Register Bits.............................................................................................. 84
Table 4-24: Serial Audio Pin Descriptions ............................................................................................. 91
Table 4-25: Audio Output Formats........................................................................................................... 93
Table 4-26: Audio Data Packet Detect Register ................................................................................... 95
Table 4-27: Audio Group DID Host Interface Settings....................................................................... 96
Table 4-28: Audio Data and Control Packet DID Setting Register................................................. 96
Table 4-29: Audio Channel Mapping Codes ......................................................................................... 98
Table 4-30: Audio Sample Word Lengths .............................................................................................. 98
Table 4-31: Audio Channel Status Information Registers .............................................................. 100
Table 4-31: Audio Channel Status Block for Regenerate Mode Default Settings ................... 100
Table 4-32: Audio Mute Control Bits ..................................................................................................... 101
Table 4-34: GV7601 GSPI Electrical Characteristics ........................................................................ 105
Table 4-33: Video Core Configuration and Status Registers.......................................................... 106
Table 4-34: SD Audio Core Configuration and Status Registers................................................... 113
Table 4-35: HD Audio Core Configuration and Status Registers.................................................. 125
Table 4-36: Ancillary Data Extraction Memory Access Registers ............................................... 137
Table 6-1: Packaging Data......................................................................................................................... 142
GV7601 Aviia™ Receiver
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List of Figures
Figure A: GV7601 Block Diagram ................................................................................................................2
Figure 3-1: Digital Input Pin with Schmitt Trigger (20BIT/10BIT, AUDIO_EN, CS_TMS,
PROC_EN, JTAG_EN, RECLK_EN, RESET, SCLK_TCK, SDIN_TDI, SDO_EN, STANDBY,
861_EN) ............................................................................................................................................................. 28
Figure 3-2: Bidirectional Digital Input/Output Pin - Configured to Output unless in
Reset Mode. (ACLK, MCLK, AOUT1/2, AOUT3/4, AOUT5/6, AOUT7/8, ASI, 656_BYPASS,
WCLK) ................................................................................................................................................................ 28
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength. ....... 29
Figure 3-4: XTAL1/XTAL2/XTAL_OUT ................................................................................................... 29
Figure 3-5: VBG .............................................................................................................................................. 30
Figure 3-6: LB_CONT .................................................................................................................................... 30
Figure 3-7: Loop Filter (LF) .......................................................................................................................... 30
Figure 3-8: Serial Input Equivalent Circuit ............................................................................................ 31
Figure 3-9: SDO/SDO .................................................................................................................................... 31
Figure 4-1: 27MHz Clock Sources ............................................................................................................ 35
Figure 4-2: Data transmitting with blanking, 525/60Hz ................................................................... 38
Figure 4-3: Multiplexing 10-bit 4:2:2 YCbCr data for 525 lines at 60Hz ..................................... 38
Figure 4-4: Data transmitting with blanking, 625/50Hz ................................................................... 39
Figure 4-5: Multiplexing 10-bit 4:2:2 YCbCr data for 625 lines at 50Hz ..................................... 39
Figure 4-6: Field Timing Relationship for 1080-line Interlaced Systems .................................... 40
Figure 4-7: Multiplexed Luma and Chroma Over One Video Line - 1080i ................................ 40
Figure 4-8: Luma Stream Over One Video Line - 1080i .................................................................... 41
Figure 4-9: Chroma Stream Over One Video Line - 1080i ............................................................... 41
Figure 4-10: Frame Timing Relationship For 1080-line Progressive Systems ........................... 42
Figure 4-11: Multiplexed Luma and Chroma Over One Video Line - 1080p ............................. 42
Figure 4-12: Luma Stream Over One Video Line - 1080p ................................................................ 42
Figure 4-13: Chroma Stream Over One Video Line - 1080p ............................................................ 42
Figure 4-14: 720p Digital Vertical Timing ............................................................................................. 43
Figure 4-15: Aviia 20-bit Mapping Structure for 1920 x 1080 50/60Hz Progressive
4:2:0 & 4:2:2 (Y‘C‘BC‘R) 8/10-bit Signals .................................................................................................. 45
Figure 4-16: Aviia 20-bit Mapping Structure for 1920 x 1080 24/25/30Hz Progressive
4:4:4 (R‘G‘B‘) 8/10-bit Signals ..................................................................................................................... 46
Figure 4-17: Aviia 20-bit Mapping Structure for 1920 x 1080 24/25/30Hz Progressive
4:4:4 (R‘G‘B‘ or Y‘C‘BC‘R) 12-bit Signals ................................................................................................... 47
Figure 4-18: Aviia 20-bit Mapping Structure for 1920 x 1080 24/25/30Hz Progressive
4:2:2 (Y‘C‘BC‘R) 12-bit Signals ..................................................................................................................... 48
Figure 4-19: Aviia 20-bit Mapping Structure for 1280 x 720 24/25/30/25/60Hz Progressive
4:4:4 (R‘G‘B‘ or Y‘C‘BC‘R) 8/10-bit Signals ............................................................................................... 50
Figure 4-20: PCLK to Data and Control Signal Output Timing - SDR Mode 1 ............................ 52
Figure 4-21: PCLK to Data and Control Signal Output Timing - SDR Mode 2 ............................ 53
Figure 4-22: PCLK to Data and Control Signal Output Timing - DDR Mode .............................. 54
Figure 4-23: DDR Video Interface ............................................................................................................ 57
Figure 4-24: Delay Adjustment Ranges .................................................................................................. 58
Figure 4-25: H:V:F Output Timing - Full HD 20-bit Output Mode ................................................. 60
Figure 4-26: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 60
Figure 4-27: H:V:F Output Timing - HD & Full HD 10-bit Output Mode ..................................... 61
Figure 4-28: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 61
Figure 4-29: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 61
Figure 4-30: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 63
Figure 4-31: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 64
Figure 4-32: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6 & 7) .................. 65
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Figure 4-33: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 66
Figure 4-34: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 67
Figure 4-35: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 68
Figure 4-36: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 69
Figure 4-37: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 70
Figure 4-38: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 71
Figure 4-39: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 72
Figure 4-40: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 73
Figure 4-41: Ancillary Data Packets ........................................................................................................ 80
Figure 4-42: Y/1ANC and C/2ANC Signal Timing - HD 20-bit ........................................................ 81
Figure 4-43: Y/1ANC and C/2ANC Signal Timing - HD 10-bit ........................................................ 81
Figure 4-44: Y/1ANC and C/2ANC Signal Timing - SD 20-bit ......................................................... 82
Figure 4-45: Y/1ANC and C/2ANC Signal Timing - SD 10-bit ......................................................... 82
Figure 4-46: Ancillary Data Extraction - Step A .................................................................................. 87
Figure 4-47: Ancillary Data Extraction - Step B ................................................................................... 88
Figure 4-48: Ancillary Data Extraction - Step C .................................................................................. 89
Figure 4-49: Ancillary Data Extraction - Step D .................................................................................. 90
Figure 4-50: ACLK to Data and WCLK Signal Output Timing ......................................................... 92
Figure 4-51: I2S Audio Output Format .................................................................................................... 93
Figure 4-52: AES/EBU or S/PDIF Audio Output Format ................................................................... 93
Figure 4-53: Serial Audio, Left Justified, MSB First ............................................................................. 94
Figure 4-54: Serial Audio, Left Justified, LSB First .............................................................................. 94
Figure 4-55: Serial Audio, Right Justified, MSB First .......................................................................... 94
Figure 4-56: Serial Audio, Right Justified, LSB First ........................................................................... 94
Figure 4-57: AES/EBU or S/PDIF Audio Output to Bit Clock Timing ............................................ 94
Figure 4-58: ECC 24-bit Array and Examples ...................................................................................... 97
Figure 4-59: GSPI Application Interface Connection ......................................................................102
Figure 4-60: Command Word Format ...................................................................................................102
Figure 4-61: Data Word Format ..............................................................................................................103
Figure 4-62: Write Mode ............................................................................................................................104
Figure 4-63: Read Mode .............................................................................................................................104
Figure 4-64: GV7601 GSPI Timing Delays ...........................................................................................105
Figure 4-65: In-Circuit JTAG ....................................................................................................................138
Figure 4-66: System JTAG .........................................................................................................................138
Figure 4-67: Reset Pulse .............................................................................................................................139
Figure 6-1: GV7601 Package Dimensions ...........................................................................................141
Figure 6-2: GV7601 Marking Diagram .................................................................................................142
Figure 6-3: Pb-free Solder reflow Profile .............................................................................................143
GV7601 Aviia™ Receiver
Data Sheet
52155 - 4
August 2009
8 of 147
Proprietary & Confidential
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