第1页 / 共175页
第2页 / 共175页
第3页 / 共175页
第4页 / 共175页
第5页 / 共175页
第6页 / 共175页
第7页 / 共175页
第8页 / 共175页
MIPI Alliance Standard for Display Serial Interface V2.0.pdf
Figures
Tables
Release History
1 Introduction
1.1 Scope
1.2 Purpose
2 Terminology (Informative)
2.1 Use of Special Terms
2.2 Number Radix
2.3 Definitions
2.4 Abbreviations
2.5 Acronyms
3 References
3.1 Display Bus Interface Standard for Parallel Signaling (DBI-2)
3.2 Display Pixel Interface Standard for Parallel Signaling (DPI-2)
3.3 MIPI Alliance Specification for Display Command Set (DCS)
3.4 (Blank Section)
3.5 Physical Layer Definition for DSI
3.5.1 MIPI Alliance Specification for D-PHY (D-PHY)
3.5.2 MIPI Alliance Specification for C-PHY (C-PHY)
3.6 MIPI Alliance Specification for Stereoscopic Display Formats (SDF)
4 DSI-2 Introduction
4.1 DSI Layer Definitions
4.2 Command and Video Modes
4.2.1 Command Mode
4.2.2 Video Mode Operation
4.2.3 Virtual Channel Capability
5 DSI Physical Layer
5.1 DSI Physical Layer for D Option
5.1.1 D-PHY Data Flow Control
5.1.2 D-PHY Bidirectionality and Low Power Signaling Policy
5.1.3 D-PHY Command Mode Interfaces
5.1.4 D-PHY Video Mode Interfaces
5.1.5 D-PHY Bidirectional Control Mechanism
5.1.6 D-PHY Clock Management
5.1.6.1 D-PHY Clock Requirements
5.1.6.2 D-PHY Clock Power and Timing
5.1.7 D-PHY System Power-Up and Initialization
5.2 DSI Physical Layer for C Option
5.2.1 C-PHY Data Flow Control
5.2.2 C-PHY Bidirectionality and Low Power Signaling Policy
5.2.3 C-PHY Command Mode Interfaces
5.2.4 C-PHY Video Mode Interfaces
5.2.5 C-PHY Bidirectional Control Mechanism
5.2.6 C-PHY Clock Management
5.2.6.1 C-PHY Clock Requirements
5.2.7 C-PHY System Power-Up and Initialization
5.3 Allowed Physical Layers in DSI-2
6 Multi-Lane Distribution and Merging
6.1 Multi-Lane Interoperability
6.1.1 D Option: Multi-Lane Distribution and Merging
6.1.1.1 D-PHY Multi-Lane Interoperability and Lane-Number Mismatch
6.1.1.2 D-PHY Clock Considerations with Multi-Lane
6.1.1.3 D-PHY Bidirectionality and Multi-Lane Capability
6.1.1.4 D-PHY SoT and EoT in Multi-Lane Configurations
6.1.2 C Option: Multi-Lane Distribution and Merging
6.1.2.1 C-PHY Multi-Lane Interoperability and Lane-Number Mismatch
6.1.2.2 C-PHY Clock Considerations with Multi-Lane
6.1.2.3 C-PHY Bidirectionality and Multi-Lane Capability
6.1.2.4 C-PHY SoT and EoT in Multi-Lane Configurations
6.2 Multi-DSI Receiver Configuration with DSI Sub-Links
6.2.1 Architecture for a Multi-DSI Receiver Configuration
6.2.2 Lane Mapping for a Multi-DSI Receiver Configuration
6.2.2.1 D Option Lane Mapping
6.2.2.2 C Option Lane Mapping
6.2.3 Video Mode Lane Timing for a DSI Sub-Link
6.2.3.1 Command Mode Use with DSI Sub-Links in a Multi-DSI Receiver Configuration (Informative)
7 Low-Level Protocol Errors and Contention
7.1 Low-Level Protocol Errors
7.1.1 SoT Error
7.1.2 SoT Sync Error
7.1.3 EoT Sync Error
7.1.4 Escape Mode Entry Command Error
7.1.5 LP Transmission Sync Error
7.1.6 False Control Error
7.2 Contention Detection and Recovery
7.2.1 Contention Detection in LP Mode
7.2.2 Contention Recovery Using Timers
7.2.2.1 Summary of Required Contention Recovery Timers
7.2.2.2 HS RX Timeout (HRX_TO) in Peripheral
7.2.2.3 HS TX Timeout (HTX_TO) in Host Processor
7.2.2.4 LP TX-Peripheral Timeout (LTX-P_TO)
7.2.2.5 LP-RX Host Processor Timeout (LRX-H_TO)
7.3 Additional Timers
7.3.1 Turnaround Acknowledge Timeout (TA_TO)
7.3.2 Peripheral Reset Timeout (PR_TO)
7.3.3 Peripheral Response Timeout (PRESP_TO)
7.4 Acknowledge and Error Reporting Mechanism
8 DSI Protocol
8.1 Multiple Packets per Transmission
8.1.1 D Option: Multiple Packets per Transmission
8.1.2 C Option: Multiple Packets per Transmission
8.2 Packet Composition
8.2.1 D Option: Packet Composition
8.2.2 C Option: Packet Composition
8.3 Endian Policy
8.3.1 D Option: Endian Policy
C Option: Endian Policy
8.4 General Packet Structure
8.4.1 D Option: General Packet Structure
8.4.1.1 D-PHY Long Packet Format
8.4.1.2 D-PHY Short Packet Format
8.4.2 C Option: General Packet Structure
8.4.2.1 C-PHY Long Packet Format in High Speed Mode
8.4.2.2 C-PHY Short Packet Format in High Speed Mode
8.4.2.3 C-PHY Long Packet Format in Escape Mode
8.4.2.4 C-PHY Short Packet Format in Escape Mode
8.5 Common Packet Elements
8.5.1 Data Identifier Byte
8.5.1.1 Virtual Channel Identifier – VC field, DI[7:6]
8.5.1.2 Data Type Field DT[5:0]
8.5.2 Error Correction Code
8.5.3 C Option: Packet Header Checksum
8.5.4 C Option: SSDC
8.5.5 C Option: SSS
8.6 Interleaved Data Streams
8.6.1 Interleaved Data Streams and Bidirectionality
8.7 Processor to Peripheral Direction (Processor-Sourced) Packet Data Types
8.7.1 Processor-sourced Data Type Summary
8.7.2 Frame Synchronized Transactions
8.8 Processor-to-Peripheral Transactions – Detailed Format Description
8.8.1 Sync Event (H Start, H End, V Start, V End), Data Type = XX 0001 (0xX1)
8.8.1.1 Sync Event Payloads
8.8.1.2 Stereoscopic Display Control in Video Mode (3D Control)
8.8.2 EoTp, Data Type = 00 1000 (0x08)
8.8.3 Color Mode Off Command, Data Type = 00 0010 (0x02)
8.8.4 Color Mode On Command, Data Type = 01 0010 (0x12)
8.8.5 Shutdown Peripheral Command, Data Type = 10 0010 (0x22)
8.8.6 Turn On Peripheral Command, Data Type = 11 0010 (0x32)
8.8.7 Generic Short WRITE Packet with 0, 1, or 2 Parameters, Data Types = 00 0011 (0x03), 01 0011 (0x13), 10 0011 (0x23), Respectively
8.8.8 Generic READ Request with 0, 1, or 2 Parameters, Data Types = 00 0100 (0x04), 01 0100 (0x14), 10 0100(0x24), Respectively
8.8.9 DCS Commands
8.8.9.1 DCS Short Write Command, 0 or 1 Parameter, Data Types = 00 0101 (0x05), 01 0101 (0x15), Respectively
8.8.9.2 DCS Read Request, No Parameters, Data Type = 00 0110 (0x06)
8.8.9.3 DCS Long Write / write_LUT Command, Data Type = 11 1001 (0x39)
8.8.10 Set Maximum Return Packet Size, Data Type = 11 0111 (0x37)
8.8.11 Null Packet (Long), Data Type = 00 1001 (0x09)
8.8.12 Blanking Packet (Long), Data Type = 01 1001 (0x19)
8.8.13 Generic Long Write, Data Type = 10 1001 (0x29)
8.8.14 Loosely Packed Pixel Stream, 20-bit YCbCr 4:2:2 Format, Data Type = 00 1100 (0x0C)
8.8.15 Packed Pixel Stream, 24-bit YCbCr 4:2:2 Format, Data Type = 01 1100 (0x1C)
8.8.16 Packed Pixel Stream, 16-bit YCbCr 4:2:2 Format, Data Type = 10 1100 (0x2C)
8.8.17 Packed Pixel Stream, 30-bit Format, Long Packet, Data Type = 00 1101 (0x0D)
8.8.18 Packed Pixel Stream, 36-bit Format, Long Packet, Data Type = 01 1101 (0x1D)
8.8.19 Packed Pixel Stream, 12-bit YCbCr 4:2:0 Format, Data Type = 11 1101 (0x3D)
8.8.20 Packed Pixel Stream, 16-bit Format, Long Packet, Data Type 00 1110 (0x0E)
8.8.21 Packed Pixel Stream, 18-bit Format, Long Packet, Data Type = 01 1110 (0x1E)
8.8.22 Pixel Stream, 18-bit Format in Three Bytes, Long Packet, Data Type = 10 1110 (0x2E)
8.8.23 Packed Pixel Stream, 24-bit Format, Long Packet, Data Type = 11 1110 (0x3E)
8.8.24 Compressed Pixel Stream, Long Packet, Data Type = 00 1011 (0x0B)
8.8.25 Compression Mode Command, Data Type = 00 0111 (0x07)
8.8.26 Picture Parameter Set (0x0A)
8.8.27 Execute Queue (0x16)
8.8.28 DO NOT USE and Reserved Data Types
8.8.29 Scrambling Mode Command (0x27)
8.9 Peripheral-to-Processor (Reverse Direction) LP Transmissions
8.9.1 Packet Structure for Peripheral-to-Processor LP Transmissions
8.9.2 System Requirements for ECC and Checksum and Packet Format
8.9.3 Appropriate Responses to Commands and ACK Requests
8.9.4 Format of Acknowledge and Error Report and Read Response Data Types
8.9.5 Error Reporting Format
8.9.5.1 D Option: Error Reporting Format
8.9.5.2 C Option: Error Reporting Format
8.10 Peripheral-to-Processor Transactions – Detailed Format Description
8.10.1 Acknowledge and Error Report, Data Type 00 0010 (0x02)
8.10.2 Generic Short Read Response, 1 or 2 Bytes, Data Types = 01 0001 or 01 0010, Respectively
8.10.3 Generic Long Read Response with Optional Payload Checksum, Data Type = 01 1010 (0x1A)
8.10.4 DCS Long Read Response with Optional Payload Checksum, Data Type 01 1100 (0x1C)
8.10.5 DCS Short Read Response, 1 or 2 Bytes, Data Types = 10 0001 or 10 0010, Respectively
8.10.6 Multiple Transmissions and Error Reporting
8.10.7 Clearing Error Bits
8.11 Video Mode Interface Timing
8.11.1 Transmission Packet Sequences
8.11.2 Non-Burst Mode with Sync Pulses
8.11.3 Non-Burst Mode with Sync Events
8.11.4 Burst Mode
8.11.5 Parameters
8.12 TE Signaling in DSI
8.13 DSI with Display Stream Compression
8.13.1 Compression Transport Requirements
8.13.2 Transport Buffer Model (Informative)
8.13.3 Compression with Video Modes
8.13.4 Compression-Related Parameters
8.13.5 Display Stream Compression with Command Mode
8.14 Data Scrambling
9 Error-Correcting Code (ECC), Payload Checksum, and Packet Header Checksum
9.1 Packet Header Error Detection/Correction
9.1.1 D Option: Packet Header Error Detection/Correction
9.1.2 C Option: Escape Mode Packet Header Error Detection/Correction
9.1.3 C Option: High Speed Mode Packet Header Error Detection/Correction
9.2 Hamming Code Theory
9.3 Hamming-Modified Code Applied to DSI Packet Headers
9.4 ECC Generation on the Transmitter
9.5 Applying ECC on the Receiver
9.6 Payload Checksum Generation for Long Packet Payloads
9.7 Checksum Generation for Reconstructed Image Test Mode
10 Compliance, Interoperability, and Optional Capabilities
10.1 Display Resolutions
10.2 Pixel Formats
10.2.1 Video Mode
10.2.2 Command Mode
10.3 Number of Lanes
10.4 Maximum Lane Frequency
10.5 Bidirectional Communication
10.6 ECC and Checksum Capabilities
10.6.1 D Option: ECC and Checksum Capabilities
10.6.2 C Option: SSDC, ECC, and Checksum Capabilities
10.7 Display Architecture
10.8 Multiple Peripheral Support
10.9 EoTp Support and Interoperability
Annex A Contention Detection and Recovery Mechanisms (Informative)
A.1 PHY Detected Contention
A.1.1 Protocol Response to PHY Detected Faults
Annex B Checksum Generation Examples (Informative)
B.1 Payload Checksum Generation Example
B.2 C-PHY Packet Header Checksum Example
Annex C Interlaced Video Transmission Sourcing
Annex D Profile for DSI Transport for VESA Display Stream Compression
D.1 Profile Normative Requirements
D.1.1 Encoder Instantiations
D.1.2 Decoder Instantiations
D.1.3 Horizontal Slice Size
D.1.4 Vertical Slice Size
D.1.5 DSC Parameter Minimum Requirements
D.1.6 PPS Requirements
D.2 Implementation Guidelines (Informative)
D.2.1 Vertical Slice Size
D.2.2 DSC Guidelines
Annex E Differences Between DSI-2 Devices Supporting D-PHY and C-PHY (Informative)
Annex F Continuous Clock Mode Support With C-PHY
Specification for
Display Serial Interface 2
(DSI-2SM)
Version 1.0 – MIPI Board Adopted 14 January 2016
This document is a MIPI Specification. MIPI member companies’ rights and obligations apply to this
Specification as defined in the MIPI Membership Agreement and MIPI Bylaws.
* NOTE TO IMPLEMENTERS *
The MIPI Alliance Display Working Group calls your attention to a normative error in Figure 42. We expect this error
to be corrected in the near future with an updated Specification.
Specifically, the Figure erroneously shows a “Sync Symbol Sequence (SSS)” immediately following a “Start of
Transmission (SoT)” event. This SSS is expected to be removed in the forthcoming Specification update.
Copyright 2005–2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
This page intentionally left blank.
Copyright 2005–2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
Specification for
Display Serial Interface 2
(DSI-2SM)
Version 1.0
17 November 2015
MIPI Board Adopted 14 January 2016
This document is a MIPI Specification. MIPI member companies’ rights and obligations apply to
this Specification as defined in the MIPI Membership Agreement and MIPI Bylaws.
Further technical changes to this document are expected as work continues in the Display Working
Group.
Copyright © 2005-2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
Specification for DSI-2
Version 1.0
17-Nov-2015
NOTICE OF DISCLAIMER
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled
by any of the authors or developers of this material or MIPI®. The material contained herein is provided on
an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS
AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all
other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any)
implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or
completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence.
All materials contained herein are protected by copyright laws, and may not be reproduced, republished,
distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior
written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related
trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and
cannot be used without its express prior written permission.
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD
TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY
AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR
MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS
OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT,
TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER
AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR
NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is
further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the
contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;
and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance
with the contents of this Document. The use or implementation of the contents of this Document may involve
or require the use of intellectual property rights (“IPR”) including (but not limited to) patents, patent
applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not
make any search or investigation for IPR, nor does MIPI require or request the disclosure of any IPR or
claims of IPR as respects the contents of this Document or otherwise.
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:
MIPI Alliance, Inc.
c/o IEEE-ISTO
445 Hoes Lane
Piscataway, NJ 08854
Attn: Board Secretary
ii
Copyright © 2005-2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
Version 1.0
17-Nov-2015
Specification for DSI-2
1.1
1.2
Contents
.................................................................................................................................. viii
Figures
Tables
..................................................................................................................................... xi
Release History ............................................................................................................................ xii
Development History ................................................................................................................... xii
Introduction ............................................................................................................................. 1
1
Scope .................................................................................................................................. 1
Purpose .............................................................................................................................. 1
2 Terminology (Informative) ..................................................................................................... 2
2.1 Use of Special Terms ......................................................................................................... 2
2.2 Number Radix .................................................................................................................... 2
2.3 Definitions ......................................................................................................................... 2
2.4 Abbreviations ..................................................................................................................... 4
2.5 Acronyms ........................................................................................................................... 4
3 References ................................................................................................................................ 7
3.1 Display Bus Interface Standard for Parallel Signaling (DBI-2) ........................................ 8
3.2 Display Pixel Interface Standard for Parallel Signaling (DPI-2) ....................................... 8
3.3 MIPI Alliance Specification for Display Command Set (DCS) ........................................ 8
(Blank Section) .................................................................................................................. 9
3.4
3.5
Physical Layer Definition for DSI ..................................................................................... 9
3.5.1 MIPI Alliance Specification for D-PHY (D-PHY) ................................................................... 9
3.5.2 MIPI Alliance Specification for C-PHY (C-PHY) ................................................................... 9
3.6 MIPI Alliance Specification for Stereoscopic Display Formats (SDF) ............................. 9
4 DSI-2 Introduction ................................................................................................................ 10
4.1 DSI Layer Definitions ...................................................................................................... 12
4.2 Command and Video Modes ........................................................................................... 13
4.2.1
Command Mode ..................................................................................................................... 13
Video Mode Operation ........................................................................................................... 13
4.2.2
4.2.3
Virtual Channel Capability ..................................................................................................... 13
5 DSI Physical Layer ................................................................................................................ 15
5.1 DSI Physical Layer for D Option .................................................................................... 15
D-PHY Data Flow Control ..................................................................................................... 15
5.1.1
D-PHY Bidirectionality and Low Power Signaling Policy .................................................... 15
5.1.2
5.1.3
D-PHY Command Mode Interfaces ....................................................................................... 16
D-PHY Video Mode Interfaces .............................................................................................. 16
5.1.4
D-PHY Bidirectional Control Mechanism ............................................................................. 16
5.1.5
5.1.6
D-PHY Clock Management .................................................................................................... 17
5.1.7
D-PHY System Power-Up and Initialization .......................................................................... 18
Copyright © 2005-2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
iii
Specification for DSI-2
Version 1.0
17-Nov-2015
5.2 DSI Physical Layer for C Option ..................................................................................... 20
C-PHY Data Flow Control ..................................................................................................... 20
5.2.1
5.2.2
C-PHY Bidirectionality and Low Power Signaling Policy ..................................................... 20
C-PHY Command Mode Interfaces ........................................................................................ 21
5.2.3
C-PHY Video Mode Interfaces .............................................................................................. 21
5.2.4
C-PHY Bidirectional Control Mechanism .............................................................................. 21
5.2.5
5.2.6
C-PHY Clock Management .................................................................................................... 21
5.2.7
C-PHY System Power-Up and Initialization .......................................................................... 22
5.3 Allowed Physical Layers in DSI-2 .................................................................................. 24
6 Multi-Lane Distribution and Merging ................................................................................ 25
6.1 Multi-Lane Interoperability ............................................................................................. 25
D Option: Multi-Lane Distribution and Merging ................................................................... 25
6.1.1
6.1.2
C Option: Multi-Lane Distribution and Merging .................................................................... 29
6.2 Multi-DSI Receiver Configuration with DSI Sub-Links ................................................. 34
Architecture for a Multi-DSI Receiver Configuration ............................................................ 34
6.2.1
Lane Mapping for a Multi-DSI Receiver Configuration ........................................................ 39
6.2.2
6.2.3
Video Mode Lane Timing for a DSI Sub-Link ....................................................................... 43
7 Low-Level Protocol Errors and Contention ....................................................................... 45
7.1 Low-Level Protocol Errors .............................................................................................. 45
7.1.1
SoT Error ................................................................................................................................ 46
SoT Sync Error ....................................................................................................................... 46
7.1.2
EoT Sync Error ....................................................................................................................... 46
7.1.3
Escape Mode Entry Command Error ...................................................................................... 47
7.1.4
7.1.5
LP Transmission Sync Error ................................................................................................... 47
7.1.6
False Control Error ................................................................................................................. 48
7.2 Contention Detection and Recovery ................................................................................ 49
7.2.1
Contention Detection in LP Mode .......................................................................................... 49
7.2.2
Contention Recovery Using Timers ....................................................................................... 49
7.3 Additional Timers ............................................................................................................ 52
Turnaround Acknowledge Timeout (TA_TO)........................................................................ 52
7.3.1
7.3.2
Peripheral Reset Timeout (PR_TO) ........................................................................................ 53
7.3.3
Peripheral Response Timeout (PRESP_TO) .......................................................................... 53
7.4 Acknowledge and Error Reporting Mechanism .............................................................. 54
8 DSI Protocol ........................................................................................................................... 55
8.1 Multiple Packets per Transmission .................................................................................. 55
D Option: Multiple Packets per Transmission ........................................................................ 55
8.1.1
8.1.2
C Option: Multiple Packets per Transmission ........................................................................ 57
Packet Composition ......................................................................................................... 58
8.2
D Option: Packet Composition ............................................................................................... 58
8.2.1
8.2.2
C Option: Packet Composition ............................................................................................... 58
8.3 Endian Policy ................................................................................................................... 59
D Option: Endian Policy ......................................................................................................... 59
8.3.1
8.3.2
C Option: Endian Policy ......................................................................................................... 59
iv
Copyright © 2005-2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
Version 1.0
17-Nov-2015
Specification for DSI-2
8.4 General Packet Structure ................................................................................................. 61
D Option: General Packet Structure ....................................................................................... 61
8.4.1
8.4.2
C Option: General Packet Structure........................................................................................ 63
8.5 Common Packet Elements ............................................................................................... 72
Data Identifier Byte ................................................................................................................ 72
8.5.1
Error Correction Code ............................................................................................................ 72
8.5.2
8.5.3
C Option: Packet Header Checksum ...................................................................................... 73
C Option: SSDC ..................................................................................................................... 73
8.5.4
C Option: SSS ......................................................................................................................... 73
8.5.5
8.6
Interleaved Data Streams ................................................................................................. 74
Interleaved Data Streams and Bidirectionality ....................................................................... 74
8.6.1
Processor to Peripheral Direction (Processor-Sourced) Packet Data Types .................... 75
8.7
Processor-sourced Data Type Summary ................................................................................. 75
8.7.1
8.7.2
Frame Synchronized Transactions .......................................................................................... 76
Processor-to-Peripheral Transactions – Detailed Format Description ............................. 78
8.8
Sync Event (H Start, H End, V Start, V End), Data Type = XX 0001 (0xX1) ....................... 78
8.8.1
8.8.2
EoTp, Data Type = 00 1000 (0x08) ........................................................................................ 80
Color Mode Off Command, Data Type = 00 0010 (0x02) ..................................................... 80
8.8.3
Color Mode On Command, Data Type = 01 0010 (0x12) ...................................................... 80
8.8.4
Shutdown Peripheral Command, Data Type = 10 0010 (0x22) .............................................. 81
8.8.5
8.8.6
Turn On Peripheral Command, Data Type = 11 0010 (0x32) ................................................ 81
8.8.7
Generic Short WRITE Packet with 0, 1, or 2 Parameters,
Data Types = 00 0011 (0x03), 01 0011 (0x13), 10 0011 (0x23), Respectively ................ 81
Data Types = 00 0100 (0x04), 01 0100 (0x14), 10 0100(0x24), Respectively ................. 81
DCS Commands ..................................................................................................................... 82
8.8.9
8.8.10
Set Maximum Return Packet Size, Data Type = 11 0111 (0x37) ........................................... 83
8.8.11 Null Packet (Long), Data Type = 00 1001 (0x09) .................................................................. 83
8.8.12 Blanking Packet (Long), Data Type = 01 1001 (0x19) .......................................................... 83
8.8.13 Generic Long Write, Data Type = 10 1001 (0x29) ................................................................. 83
8.8.14 Loosely Packed Pixel Stream, 20-bit YCbCr 4:2:2 Format, Data Type = 00 1100 (0x0C) .... 84
8.8.15
Packed Pixel Stream, 24-bit YCbCr 4:2:2 Format, Data Type = 01 1100 (0x1C) .................. 85
Packed Pixel Stream, 16-bit YCbCr 4:2:2 Format, Data Type = 10 1100 (0x2C) .................. 86
8.8.16
Packed Pixel Stream, 30-bit Format, Long Packet, Data Type = 00 1101 (0x0D) ................. 87
8.8.17
8.8.18
Packed Pixel Stream, 36-bit Format, Long Packet, Data Type = 01 1101 (0x1D) ................. 88
Packed Pixel Stream, 12-bit YCbCr 4:2:0 Format, Data Type = 11 1101 (0x3D) ................. 89
8.8.19
Packed Pixel Stream, 16-bit Format, Long Packet, Data Type 00 1110 (0x0E) ..................... 90
8.8.20
Packed Pixel Stream, 18-bit Format, Long Packet, Data Type = 01 1110 (0x1E) ................. 91
8.8.21
8.8.22
Pixel Stream, 18-bit Format in Three Bytes, Long Packet, Data Type = 10 1110 (0x2E) ...... 92
8.8.23
Packed Pixel Stream, 24-bit Format, Long Packet, Data Type = 11 1110 (0x3E) ................. 93
8.8.24 Compressed Pixel Stream, Long Packet, Data Type = 00 1011 (0x0B) ................................. 94
8.8.25 Compression Mode Command, Data Type = 00 0111 (0x07) ................................................ 96
8.8.26
Picture Parameter Set (0x0A) ................................................................................................. 97
8.8.27 Execute Queue (0x16) ............................................................................................................ 97
8.8.8
Generic READ Request with 0, 1, or 2 Parameters,
Copyright © 2005-2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
v
Specification for DSI-2
Version 1.0
17-Nov-2015
8.8.28 DO NOT USE and Reserved Data Types ............................................................................... 97
Scrambling Mode Command (0x27) ...................................................................................... 98
8.8.29
8.9
Peripheral-to-Processor (Reverse Direction) LP Transmissions ..................................... 99
Packet Structure for Peripheral-to-Processor LP Transmissions ............................................ 99
8.9.1
System Requirements for ECC and Checksum and Packet Format ...................................... 100
8.9.2
Appropriate Responses to Commands and ACK Requests .................................................. 100
8.9.3
8.9.4
Format of Acknowledge and Error Report and Read Response Data Types ........................ 102
8.9.5
Error Reporting Format ........................................................................................................ 103
8.10 Peripheral-to-Processor Transactions – Detailed Format Description ........................... 106
8.10.1 Acknowledge and Error Report, Data Type 00 0010 (0x02) ................................................ 107
8.10.2 Generic Short Read Response, 1 or 2 Bytes,
Data Types = 01 0001 or 01 0010, Respectively ............................................................ 107
8.10.3 Generic Long Read Response with Optional Payload Checksum,
Data Type = 01 1010 (0x1A) .......................................................................................... 107
8.10.4 DCS Long Read Response with Optional Payload Checksum,
Data Type 01 1100 (0x1C) ............................................................................................. 108
8.10.5 DCS Short Read Response, 1 or 2 Bytes,
Data Types = 10 0001 or 10 0010, Respectively ............................................................ 108
8.10.6 Multiple Transmissions and Error Reporting ....................................................................... 108
8.10.7 Clearing Error Bits................................................................................................................ 108
8.11 Video Mode Interface Timing ....................................................................................... 109
8.11.1 Transmission Packet Sequences ........................................................................................... 109
8.11.2 Non-Burst Mode with Sync Pulses ....................................................................................... 111
8.11.3 Non-Burst Mode with Sync Events ...................................................................................... 112
8.11.4 Burst Mode ........................................................................................................................... 113
8.11.5
Parameters ............................................................................................................................ 114
8.12 TE Signaling in DSI ....................................................................................................... 115
8.13 DSI with Display Stream Compression ......................................................................... 116
8.13.1 Compression Transport Requirements.................................................................................. 116
8.13.2 Transport Buffer Model (Informative) ................................................................................. 116
8.13.3 Compression with Video Modes .......................................................................................... 116
8.13.4 Compression-Related Parameters ......................................................................................... 116
8.13.5 Display Stream Compression with Command Mode ............................................................ 117
8.14 Data Scrambling ............................................................................................................ 118
9 Error-Correcting Code (ECC), Payload Checksum, and Packet Header Checksum ... 123
Packet Header Error Detection/Correction .................................................................... 123
9.1
D Option: Packet Header Error Detection/Correction .......................................................... 123
9.1.1
C Option: Escape Mode Packet Header Error Detection/Correction .................................... 123
9.1.2
9.1.3
C Option: High Speed Mode Packet Header Error Detection/Correction ............................ 124
9.2 Hamming Code Theory ................................................................................................. 126
9.3 Hamming-modified Code Applied to DSI Packet Headers ........................................... 127
9.4 ECC Generation on the Transmitter .............................................................................. 131
9.5 Applying ECC on the Receiver ..................................................................................... 132
9.6
Payload Checksum Generation for Long Packet Payloads ............................................ 133
vi
Copyright © 2005-2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
相关推荐
2023年江西萍乡中考道德与法治真题及答案.doc
2012年重庆南川中考生物真题及答案.doc
2013年江西师范大学地理学综合及文艺理论基础考研真题.doc
2020年四川甘孜小升初语文真题及答案I卷.doc
2020年注册岩土工程师专业基础考试真题及答案.doc
2023-2024学年福建省厦门市九年级上学期数学月考试题及答案.doc
2021-2022学年辽宁省沈阳市大东区九年级上学期语文期末试题及答案.doc
2022-2023学年北京东城区初三第一学期物理期末试卷及答案.doc
2018上半年江西教师资格初中地理学科知识与教学能力真题及答案.doc
2012年河北国家公务员申论考试真题及答案-省级.doc
2020-2021学年江苏省扬州市江都区邵樊片九年级上学期数学第一次质量检测试题及答案.doc
2022下半年黑龙江教师资格证中学综合素质真题及答案.doc
