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2018年最新版 IEEE Standard VHDL Analog and Mixed-Signal Extensions.pdf
IEEE Std 1076.1-2017 Front cover
Title page
Important Notices and Disclaimers Concerning IEEE Standards Documents
Participants
Introduction
Contents
1. Overview
1.1 Scope
1.2 Purpose
1.3 Structure and terminology of this standard
1.3.1 General
1.3.2 Syntactic description
1.3.3 Semantic description
1.3.4 Front matter, examples, notes, references, and annexes
1.3.5 Incorporation of Property Specification Language
2. Normative references
3. Design entities and configurations
3.1 General
3.2 Entity declarations
3.2.1 General
3.2.2 Entity header
3.2.3 Entity declarative part
3.2.4 Entity statement part
3.3 Architecture bodies
3.3.1 General
3.3.2 Architecture declarative part
3.3.3 Architecture statement part
3.4 Configuration declarations
3.4.1 General
3.4.2 Block configuration
3.4.3 Component configuration
4. Subprograms and packages
4.1 General
4.2 Subprogram declarations
4.2.1 General
4.2.2 Formal parameters
4.2.2.1 Formal parameter lists
4.2.2.2 Constant and variable parameters
4.2.2.3 Signal parameters
4.2.2.4 File parameters
4.3 Subprogram bodies
4.4 Subprogram instantiation declarations
4.5 Subprogram overloading
4.5.1 General
4.5.2 Operator overloading
4.5.3 Signatures
4.6 Resolution functions
4.7 Package declarations
4.8 Package bodies
4.9 Package instantiation declarations
4.10 Conformance rules
5. Types and natures
5.1 General
5.2 Scalar types
5.2.1 General
5.2.2 Enumeration types
5.2.2.1 General
5.2.2.2 Predefined enumeration types
5.2.3 Integer types
5.2.3.1 General
5.2.3.2 Predefined integer types
5.2.4 Physical types
5.2.4.1 General
5.2.4.2 Predefined physical types
5.2.5 Floating-point types
5.2.5.1 General
5.2.5.2 Predefined floating-point types
5.2.6 Predefined operations on scalar types
5.3 Composite types
5.3.1 General
5.3.2 Array types
5.3.2.1 General
5.3.2.2 Index constraints and discrete ranges
5.3.2.3 Predefined array types
5.3.2.4 Predefined operations on array types
5.3.3 Record types
5.4 Access types
5.4.1 General
5.4.2 Incomplete type declarations
5.4.3 Allocation and deallocation of objects
5.5 File types
5.5.1 General
5.5.2 File operations
5.6 Protected types
5.6.1 Protected type definitions
5.6.2 Protected type declarations
5.6.3 Protected type bodies
5.7 String representations
5.8 Natures
5.8.1 General
5.8.2 Scalar natures
5.8.3 Composite natures
5.8.3.1 General
5.8.3.2 Array natures
5.8.3.3 Record natures
6. Declarations
6.1 General
6.2 Type declarations
6.3 Subtype declarations
6.4 Objects
6.4.1 General
6.4.2 Object declarations
6.4.2.1 General
6.4.2.2 Constant declarations
6.4.2.3 Signal declarations
6.4.2.4 Variable declarations
6.4.2.5 File declarations
6.4.2.6 Terminal declarations
6.4.2.7 Quantity declarations
6.5 Interface declarations
6.5.1 General
6.5.2 Interface object declarations
6.5.3 Interface type and interface nature declarations
6.5.3.1 Interface type declarations
6.5.3.2 Interface nature declarations
6.5.4 Interface subprogram declarations
6.5.5 Interface package declarations
6.5.6 Interface lists
6.5.6.1 General
6.5.6.2 Generic clauses
6.5.6.3 Port clauses
6.5.7 Association lists
6.5.7.1 General
6.5.7.2 Generic map aspects
6.5.7.3 Port map aspects
6.6 Alias declarations
6.6.1 General
6.6.2 Object aliases
6.6.3 Nonobject aliases
6.7 Attribute declarations
6.8 Component declarations
6.9 Group template declarations
6.10 Group declarations
6.11 Nature and subnature declarations
6.12 PSL clock declarations
7. Specifications
7.1 General
7.2 Attribute specification
7.3 Configuration specification
7.3.1 General
7.3.2 Binding indication
7.3.2.1 General
7.3.2.2 Entity aspect
7.3.3 Default binding indication
7.3.4 Verification unit binding indication
7.4 Disconnection specification
7.5 Step limit specification
8. Names
8.1 General
8.2 Simple names
8.3 Selected names
8.4 Indexed names
8.5 Slice names
8.6 Attribute names
8.7 External names
9. Expressions
9.1 General
9.2 Operators
9.2.1 General
9.2.2 Logical operators
9.2.3 Relational operators
9.2.4 Shift operators
9.2.5 Adding operators
9.2.6 Sign operators
9.2.7 Multiplying operators
9.2.8 Miscellaneous operators
9.2.9 Condition operator
9.3 Operands
9.3.1 General
9.3.2 Literals
9.3.3 Aggregates
9.3.3.1 General
9.3.3.2 Record aggregates
9.3.3.3 Array aggregates
9.3.4 Function calls
9.3.5 Qualified expressions
9.3.6 Type conversions
9.3.7 Allocators
9.4 Static expressions
9.4.1 General
9.4.2 Locally static primaries
9.4.3 Globally static primaries
9.5 Universal expressions
9.6 Linear forms
10 Sequential statements
10.1 General
10.2 Wait statement
10.3 Assertion statement
10.4 Report statement
10.5 Signal assignment statement
10.5.1 General
10.5.2 Simple signal assignments
10.5.2.1 General
10.5.2.2 Executing a simple assignment statement
10.5.3 Conditional signal assignments
10.5.4 Selected signal assignments
10.6 Variable assignment statement
10.6.1 General
10.6.2 Simple variable assignments
10.6.2.1 General
10.6.2.2 Composite variable assignments
10.6.3 Conditional variable assignments
10.6.4 Selected variable assignments
10.7 Procedure call statement
10.8 If statement
10.9 Case statement
10.10 Loop statement
10.11 Next statement
10.12 Exit statement
10.13 Return statement
10.14 Null statement
10.15 Break statement
11. Architecture statements
11.1 General
11.2 Block statement
11.3 Process statement
11.4 Concurrent procedure call statements
11.5 Concurrent assertion statements
11.6 Concurrent signal assignment statements
11.7 Component instantiation statements
11.7.1 General
11.7.2 Instantiation of a component
11.7.3 Instantiation of a design entity
11.8 Generate statements
11.9 Concurrent break statement
11.10 Simple simultaneous statement
11.11 Simultaneous if statement
11.12 Simultaneous case statement
11.13 Simultaneous procedural statement
11.14 Simultaneous null statement
12. Scope and visibility
12.1 Declarative region
12.2 Scope of declarations
12.3 Visibility
12.4 Use clauses
12.5 The context of overload resolution
13. Design units and their analysis
13.1 Design units
13.2 Design libraries
13.3 Context declarations
13.4 Context clauses
13.5 Order of analysis
14. Elaboration and execution
14.1 General
14.2 Elaboration of a design hierarchy
14.3 Elaboration of a block, package, or subprogram header
14.3.1 General
14.3.2 Generic clause
14.3.3 Generic map aspect
14.3.3.1 General
14.3.3.2 Association elements for generic constants
14.3.3.3 Association elements for generic types and natures
14.3.3.4 Association elements for generic subprograms
14.3.3.5 Association elements for generic packages
14.3.4 Port clause
14.3.5 Port map aspect
14.4 Elaboration of a declarative part
14.4.1 General
14.4.2 Elaboration of a declaration
14.4.2.1 General
14.4.2.2 Subprogram declarations, bodies, and instantiations
14.4.2.3 Type declarations
14.4.2.4 Subtype declarations
14.4.2.5 Object declarations
14.4.2.6 Alias declarations
14.4.2.7 Attribute declarations
14.4.2.8 Component declarations
14.4.2.9 Packages
14.4.2.10 Nature and subnature declarations
14.4.3 Elaboration of a specification
14.4.3.1 General
14.4.3.2 Attribute specifications
14.4.3.3 Configuration specifications
14.4.3.4 Disconnection specifications
14.4.3.5 Step limit specifications
14.5 Elaboration of a statement part
14.5.1 General
14.5.2 Block statements
14.5.3 Generate statements
14.5.4 Component instantiation statements
14.5.5 Other concurrent statements
14.5.6 Simultaneous statements
14.6 Dynamic elaboration
14.7 Execution of a model
14.7.1 General
14.7.2 Drivers
14.7.3 Propagation of signal values
14.7.3.1 General
14.7.3.2 Driving values
14.7.3.3 Effective values
14.7.3.4 Signal update
14.7.4 Updating implicit signals
14.7.5 Model execution
14.7.5.1 General
14.7.5.2 Initialization
14.7.5.3 Simulation cycle
14.7.6 Augmentation sets
14.7.6.1 General
14.7.6.2 Quiescent state augmentation set
14.7.6.3 Time domain augmentation set
14.7.6.4 Discontinuity augmentation set
14.7.6.5 Frequency domain augmentation set
14.7.6.6 Noise augmentation set
14.7.7 Analog solver
14.7.7.1 General
14.7.7.2 Application of the break set
14.8 Time and the analog solver
14.9 Frequency and noise calculation
15. Lexical elements
15.1 General
15.2 Character set
15.3 Lexical elements, separators, and delimiters
15.4 Identifiers
15.4.1 General
15.4.2 Basic identifiers
15.4.3 Extended identifiers
15.5 Abstract literals
15.5.1 General
15.5.2 Decimal literals
15.5.3 Based literals
15.6 Character literals
15.7 String literals
15.8 Bit string literals
15.9 Comments
15.10 Reserved words
15.11 Tool directives
16. Predefined language environment
16.1 General
16.2 Predefined attributes
16.2.1 General
16.2.2 Predefined attributes of types and objects
16.2.3 Predefined attributes of arrays
16.2.4 Predefined attributes of signals
16.2.5 Predefined attributes of named entities
16.2.6 Predefined analog and mixed-signal attributes
16.3 Package STANDARD
16.4 Package TEXTIO
16.5 Standard environment package
16.6 Standard mathematical packages
16.7 Standard multivalue logic package
16.8 Standard synthesis packages
16.8.1 Overview
16.8.1.1 Scope
16.8.1.2 Terminology
16.8.2 Interpretation of the standard logic types
16.8.2.1 General
16.8.2.2 The STD_LOGIC_1164 values
16.8.2.3 Static constant values
16.8.2.4 Interpretation of logic values
16.8.3 The STD_MATCH function and predefined matching relational operators
16.8.4 Signal edge detection
16.8.5 Packages for arithmetic using bit and standard logic values
16.8.5.1 General
16.8.5.2 Allowable modifications
16.8.5.3 Compatibility with previous editions of IEEE Std 1076
16.8.5.4 The package texts
16.9 Standard synthesis context declarations
16.10 Fixed-point package
16.11 Floating-point package
16.12 Standard packages for multiple energy domain support
16.12.1 Scope
16.12.2 Organization of the packages
16.12.3 The package texts
17. VHDL Procedural Interface overview
17.1 General
17.2 Organization of the interface
17.2.1 General
17.2.2 VHPI naming conventions
17.3 Capability sets
17.4 Handles
17.4.1 General
17.4.2 Handle creation
17.4.3 Handle release
17.4.4 Handle comparison
17.4.5 Validity of handles
18. VHPI access functions
18.1 General
18.2 Information access functions
18.2.1 General
18.2.2 One-to-one association traversal
18.2.3 One-to-many association traversal
18.3 Property access functions
18.3.1 General
18.3.2 Integer and Boolean property access function
18.3.3 String property access function
18.3.4 Real property access function
18.3.5 Physical property access function
18.4 Access by name function
19. VHPI information model
19.1 General
19.2 Formal notation
19.2.1 General
19.2.2 Machine-readable information model
19.3 Class inheritance hierarchy
19.4 Name properties
19.4.1 General
19.4.2 Implicit labels of statements
19.4.2.1 General
19.4.2.2 Implicit labels of loop statements
19.4.2.3 Implicit labels of concurrent statements
19.4.3 The Name and CaseName properties
19.4.4 The SignatureName property
19.4.5 The UnitName property
19.4.6 The DefName and DefCaseName properties
19.4.7 The FullName and FullCaseName properties
19.4.8 The PathName and InstanceName properties
19.5 The stdUninstantiated package
19.6 The stdHierarchy package
19.7 The stdTypes package
19.8 The stdExpr package
19.9 The stdSpec package
19.10 The stdSubprograms package
19.11 The stdStmts package
19.12 The stdConnectivity package
19.12.1 Class diagrams
19.12.2 Contributors, loads, and simulated nets
19.12.2.1 General
19.12.2.2 Local contributors
19.12.2.3 Local loads
19.12.2.4 Simulated nets
19.13 The stdCallbacks package
19.14 The stdEngine package
19.15 The stdForeign package
19.16 The stdMeta package
19.17 The stdTool package
19.18 Application contexts
20. VHPI tool execution
20.1 General
20.2 Registration phase
20.2.1 General
20.2.2 Registration using a tabular registry
20.2.3 Registration using registration functions
20.2.4 Foreign attribute for foreign models
20.2.4.1 General
20.2.4.2 Standard indirect binding
20.2.4.3 Standard direct binding
20.3 Analysis phase
20.4 Elaboration phase
20.4.1 General
20.4.2 Dynamic elaboration
20.5 Initialization phase
20.6 Simulation phase
20.7 Save phase
20.8 Restart phase
20.9 Reset phase
20.10 Termination phase
21. VHPI callbacks
21.1 General
21.2 Callback functions
21.2.1 General
21.2.2 Registering callbacks
21.2.3 Enabling and disabling callbacks
21.2.4 Removing callbacks
21.2.5 Callback information
21.2.6 Execution of callbacks
21.3 Callback reasons
21.3.1 General
21.3.2 Object callbacks
21.3.2.1 General
21.3.2.2 vhpiCbValueChange
21.3.2.3 vhpiCbForce
21.3.2.4 vhpiCbRelease
21.3.2.5 vhpiCbTransaction
21.3.3 Foreign model callbacks
21.3.3.1 General
21.3.3.2 vhpiCbTimeOut and vhpiCbRepTimeOut
21.3.3.3 vhpiCbSensitivity
21.3.4 Statement callbacks
21.3.4.1 General
21.3.4.2 vhpiCbStmt
21.3.4.3 vhpiCbResume
21.3.4.4 vhpiCbSuspend
21.3.4.5 vhpiCbStartOfSubpCall
21.3.4.6 vhpiCbEndOfSubpCall
21.3.5 Time callbacks
21.3.5.1 General
21.3.5.2 vhpiCbAfterDelay and vhpiCbRepAfterDelay
21.3.6 Simulation phase callbacks
21.3.6.1 General
21.3.6.2 vhpiCbNextTimeStep and vhpiCbRepNextTimeStep
21.3.6.3 vhpiCbStartOfNextCycle and vhpiCbRepStartOfNextCycle
21.3.6.4 vhpiCbStartOfProcesses and vhpiCbRepStartOfProcesses
21.3.6.5 vhpiCbEndOfProcesses and vhpiCbRepEndOfProcesses
21.3.6.6 vhpiCbLastKnownDeltaCycle and vhpiCbRepLastKnownDeltaCycle
21.3.6.7 vhpiCbStartOfPostponed and vhpiCbRepStartOfPostponed
21.3.6.8 vhpiCbEndOfTimeStep and vhpiCbRepEndOfTimeStep
21.3.7 Action callbacks
21.3.7.1 General
21.3.7.2 vhpiCbStartOfTool and vhpiCbEndOfTool
21.3.7.3 vhpiCbStartOfAnalysis and vhpiCbEndOfAnalysis
21.3.7.4 vhpiCbStartOfElaboration and vhpiCbEndOfElaboration
21.3.7.5 vhpiCbStartOfInitialization and vhpiCbEndOfInitialization
21.3.7.6 vhpiCbStartOfSimulation and vhpiCbEndOfSimulation
21.3.7.7 vhpiCbQuiescense
21.3.7.8 vhpiCbEnterInteractive
21.3.7.9 vhpiCbExitInteractive
21.3.7.10 vhpiCbSigInterrupt
21.3.8 Save, restart, and reset callbacks
21.3.8.1 General
21.3.8.2 vhpiCbStartOfSave and vhpiCbEndOfSave
21.3.8.3 vhpiCbStartOfRestart and vhpiCbEndOfRestart
21.3.8.4 vhpiCbStartOfReset and vhpiCbEndOfReset
22. VHPI value access and update
22.1 General
22.2 Value structures and types
22.2.1 General
22.2.2 vhpiEnumT and vhpiSmallEnumT
22.2.3 vhpiIntT and vhpiLongIntT
22.2.4 vhpiCharT
22.2.5 vhpiRealT
22.2.6 vhpiPhysT and vhpiSmallPhysT
22.2.7 vhpiTimeT
22.2.8 vhpiValueT
22.3 Reading object values
22.4 Formatting values
22.5 Updating object values
22.5.1 General
22.5.2 Updating an object of class variable
22.5.3 Updating an object of class signal
22.5.4 Updating an object of class driver
22.5.5 Updating an object of class funcCall
22.6 Scheduling transactions on drivers
23. VHPI function reference
23.1 General
23.2 vhpi_assert
23.3 vhpi_check_error
23.4 vhpi_compare_handles
23.5 vhpi_control
23.6 vhpi_create
23.7 vhpi_disable_cb
23.8 vhpi_enable_cb
23.9 vhpi_format_value
23.10 vhpi_get
23.11 vhpi_get_cb_info
23.12 vhpi_get_data
23.13 vhpi_get_foreignf_info
23.14 vhpi_get_next_time
23.15 vhpi_get_phys
23.16 vhpi_get_real
23.17 vhpi_get_str
23.18 vhpi_get_time
23.19 vhpi_get_value
23.20 vhpi_handle
23.21 vhpi_handle_by_index
23.22 vhpi_handle_by_name
23.23 vhpi_is_printable
23.24 vhpi_iterator
23.25 vhpi_printf
23.26 vhpi_protected_call
23.27 vhpi_put_data
23.28 vhpi_put_value
23.29 vhpi_register_cb
23.30 vhpi_register_foreignf
23.31 vhpi_release_handle
23.32 vhpi_remove_cb
23.33 vhpi_scan
23.34 vhpi_schedule_transaction
23.35 vhpi_vprintf
24. Standard tool directives
24.1 Protect tool directives
24.1.1 General
24.1.2 Protect directives
24.1.2.1 Protect begin directive
24.1.2.2 Protect end directive
24.1.2.3 Protect begin protected directive
24.1.2.4 Protect end protected directive
24.1.2.5 Protect author directive
24.1.2.6 Protect author info directive
24.1.2.7 Protect encrypt agent directive
24.1.2.8 Protect encrypt agent info directive
24.1.2.9 Protect key keyowner directive
24.1.2.10 Protect key keyname directive
24.1.2.11 Protect key method directive
24.1.2.12 Protect key block directive
24.1.2.13 Protect data keyowner directive
24.1.2.14 Protect data keyname directive
24.1.2.15 Protect data method directive
24.1.2.16 Protect data block directive
24.1.2.17 Protect digest keyowner directive
24.1.2.18 Protect digest keyname directive
24.1.2.19 Protect digest key method directive
24.1.2.20 Protect digest method directive
24.1.2.21 Protect digest block directive
24.1.2.22 Protect encoding directive
24.1.2.23 Protect viewport directive
24.1.2.24 Protect license directives
24.1.2.25 Protect comment directive
24.1.3 Encoding, encryption, and digest methods
24.1.3.1 Encoding methods
24.1.3.2 Encryption methods
24.1.3.3 Digest methods
24.1.4 Encryption envelopes
24.1.4.1 General
24.1.4.2 Encrypt key specifications
24.1.4.3 Encrypt data specifications
24.1.4.4 Encrypt digest specifications
24.1.5 Decryption envelopes
24.1.5.1 General
24.1.5.2 Decrypt key blocks
24.1.5.3 Decrypt data blocks
24.1.5.4 Decrypt digest blocks
24.1.6 Protection requirements for decryption tools
Annex A (informative) Description of accompanying files
Annex B (informative) VHPI header file
Annex C (informative) Syntax summary
Annex D (informative) Potentially nonportable constructs
Annex E (informative) Changes from IEEE Std 1076.1-2007
Annex F (informative) Features under consideration for removal
Annex G (informative) Guide to use of standard packages
Annex H (informative) Guide to use of protect directives
Annex I (informative) Glossary
Annex J (informative) Bibliography
Index
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Z
Back cover
IEEE Standard VHDL Analog and
Mixed-Signal Extensions
IEEE Computer Society
Design Automation Standards Committee
Sponsored by the
IEEE
3 Park Avenue
New York, NY 10016-5997
USA
IEEE Std 1076.1™-2017
(Revision of
IEEE Std 1076.1-2007)
Authorized licensed use limited to: TUFTS UNIV. Downloaded on February 19,2018 at 15:00:10 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1076.1™-2017
(Revision of
IEEE Std 1076.1-2007)
IEEE Standard VHDL Analog and
Mixed-Signal Extensions
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
Approved 28 September 2017
IEEE-SA Standards Board
Authorized licensed use limited to: TUFTS UNIV. Downloaded on February 19,2018 at 15:00:10 UTC from IEEE Xplore. Restrictions apply.
Copyrights and Permissions
The editing and technical work done on the 2008 revision of IEEE Std 1076™, which forms the
basis for this standard, was done in collaboration between the Accellera VHDL Technical
Subcommittee and the IEEE VHDL Analysis and Screening Committee (VASG). Accellera has
donated all of its work and copyrights back to the IEEE.
Material in 24.1 titled “Protect Tool Directives” is derived from the document titled “A Mechanism
for VHDL Source Protection” © 2003, Cadence Design Systems Inc. Used, modified, and reprinted
by permission of Cadence Design Systems Inc.
The packages FIXED_GENERIC PKG, FIXED_PKG, FLOAT_GENERIC_PKG, FLOAT_PKG, and
FIXED_FLOAT_TYPES were modified and used with permission from Eastman Kodak Company
© 2006. Material in Annex G titled “Using the fixed-point package” (G.4) and “Using the
floating-point package” (G.5) is derived from the documents titled “Fixed Point Package User’s
Guide” and “Floating Point Package User’s Guide” by Eastman Kodak Company © 2006. Used,
modified, and reprinted by permission of Eastman Kodak Company.
Abstract: The IEEE 1076.1 language, a hardware description language for the description and the
simulation of analog, digital, and mixed-signal systems, is defined in this standard. The language,
also informally known as VHDL-AMS, is built on IEEE Std 1076-2008 (VHDL) and extends it with
additions and changes to provide capabilities of writing and simulating analog and mixed-signal
models.
Keywords: analog design, computer, computer languages, hardware design, IEEE 1076™,
IEEE 1076.1™, mixed-signal design, VHDL
The Institute of Electrical and Electronics Engineers, Inc.
3 Park Avenue, New York, NY 10016-5997, USA
Copyright © 2017 by The Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published 26 January 2018. Printed in the United States of America.
IEEE is a registered trademark in the U.S. Patent & Trademark Office, owned by The Institute of
Electrical and Electronics Engineers, Incorporated.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
Print:
PDF:
ISBN 978-1-5044-4267-1
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Participants
At the time of approval of this standard, the IEEE 1076.1 Working Group had the following membership:
Ernst Christen, Chair
Zhichao Deng, Vice Chair
Joachim Haase, Secretary
Alain Vachoux, Technical Editor
Vipin Ahuja
Kenneth Bakalar
David Bishop
Tom Kazmierski
Enrique Reyes-Archundia
John Shields
David W. Smith
Mark Zwolinski
Work on this standard was divided among several committees. The following committee members
contributed to this revision, in addition to the Working Group members:
Peter Ashenden
Brian Mulvaney
Arpad Muranyi
Subramanian Sivaramakrishnan
Thuy Tran
Yaseen Zaidi
The following members of the individual balloting committee voted on this standard. Balloters may have
voted for approval, disapproval, or abstention.
Ernst Christen
Zhichao Deng
Randall Groves
Joachim Haase
Werner Hoelzl
Joseph Hupcey
Noriyuki Ikeuchi
Piotr Karocki
Stanley Krolikoski
Haobo Lai
Lieven Lemiengre
Jim Lewis
Genichi Tanaka
John Vergis
When the IEEE-SA Standards Board approved this standard on 28 September 2017, it had the following
membership:
Jean-Philippe Faure, Chair
Gary Hoffman, Vice Chair
John D. Kulick, Past Chair
Konstantinos Karachalios, Secretary
Chuck Adams
Masayuki Ariyoshi
Ted Burse
Stephen Dukes
Doug Edwards
J. Travis Griffith
Michael Janezic
*Member Emeritus
Thomas Koshy
Joseph L. Koepfinger*
Kevin Lu
Daleep Mohla
Damir Novosel
Ronald C. Petersen
Annette D. Reilly
Robby Robson
Dorothy Stanley
Adrian Stephens
Mehmet Ulema
Phil Wennblom
Howard Wolfman
Yu Yuan
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Introduction
This introduction is not part of IEEE Std 1076.1-2017, IEEE Standard VHDL Analog and Mixed-Signal Extensions.
The IEEE 1076.1 language, informally known as VHDL-AMS, is a superset of IEEE Std 1076-2008
(VHDL) that provides capabilities for describing and simulating analog and mixed-signal systems with
conservative and nonconservative semantics for the analog portion of the system.1 The language supports
modeling at many abstraction levels in electrical and nonelectrical energy domains for lumped systems that
can be described by ordinary differential equations and algebraic equations. The language does not specify
any particular technique to solve the equations, but it rather defines the results that must be achieved. The
solution of the equations may include discontinuities. Interaction between the digital part of a model and its
analog part is supported in a flexible and efficient manner. Finally, support for frequency domain
small-signal and noise simulation is provided.
The extension of VHDL to support analog and mixed-signal systems began in 1989, as part of the second
revision of IEEE Std 1076 targeted for a 1993 release. A large number of requirements to support analog and
mixed-signal systems were submitted, and it soon became apparent that the complexity of the topic required
the formation of a separate working group. The design of the IEEE 1076.1 language formally began in 1993,
when the IEEE 1076.1 Working Group was formed under the auspices of the Design Automation Standards
Committee of the IEEE Computer Society, under Project Authorization Request (PAR) 1076.1. Its charter
was to extend the IEEE 1076 (VHDL) language to support the requirements for the description and
simulation of analog and mixed-signal systems. The IEEE 1076.1 Working Group approved the draft
standard in June 1997. The first release of the draft of IEEE Std 1076.1-1999 was approved by the IEEE
Standards Board on 18 March 1999.
The 2017 revision includes changes made to IEEE Std 1076 since the publication of IEEE Std 1076.1-2007,
as well as additions to the language. See the Annex E for a list of changes from the 2007 release.
The IEEE 1076.1 Working Group will continue to maintain the IEEE 1076.1 language.2
1Information on references can be found in Clause 2.
2Information on these efforts may be found at the following URL: http://www.eda-twiki.org/vhdl-ams.
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