VITA46.4 PCIE.pdf-资料库

PCI Express Signal Mapping for VITA 46 (VPX) VITA 46.4-200x Draft 0.3 August 20, 2007 This draft standard is being prepared by the VITA Standards Organization (VSO) and is unapproved. Do not specify or claim conformance to this draft standard VSO is a Public Domain Administrator of this draft standard and guards the contents from change except by sanctioned meetings of the working group under due process. VITA Standards Organization PO. Box 19658 Fountain Hills, AZ 85269 Ph: 480-837-7486 URL: http://www.vita.com Page 1 of 17 Do not specify or claim conformance to this document VITA 46.4-200x/D0.3

Table of Contents 1 3 2.1 2.2 2.2.1 2.2.2 1.1 1.2 1.3 1.4 Introduction................................................................................................................. 5 Objective............................................................................................................. 5 PCI Express Technology Overview.................................................................... 5 Terminology........................................................................................................ 6 References........................................................................................................... 8 2 VITA 46.4 Compliance............................................................................................... 9 General Requirements for VITA 46.4 compliance............................................. 9 Connectors Pin Mapping..................................................................................... 9 P0, P2, P3 P4, P5 and P6 Connector Signal Mapping ................................ 9 P1 - Connector Signal Mapping.................................................................. 9 Link Configuration............................................................................................ 11 Glyphs............................................................................................................... 12 Alignment and Keying...................................................................................... 12 Payload Module Requirements for VITA46.4 compliance ...................................... 13 3U Module Specific Requirements................................................................... 13 6U Module Specific Requirements................................................................... 13 4 Backplane Specific Requirements for VITA46.4 compliance.................................. 13 Electrical Budgets ..................................................................................................... 14 5 AC Coupling Capacitors................................................................................... 14 Impedance......................................................................................................... 14 Insertion Loss.................................................................................................... 14 Jitter................................................................................................................... 15 Lane-to-Lane Skew........................................................................................... 16 Intra-Pair Skew ................................................................................................. 16 Signal Routing Recommendations............................................................................ 17 5.1 5.2 5.3 5.4 5.5 5.6 2.3 2.4 2.5 3.1 3.2 6 Page 2 of 17 Do not specify or claim conformance to this document VITA 46.4-200x/D0.3

Attendee (alphabetical by last name) Randy Banton Rodger Bird David Compston Stewart Dewar Gerard Drewek Steve Edwards Val Gueorguiev Greg Griffith Mike Gust Mike Hasenfratz Melissa Heckman Dean Holman Richard Jaenicke Aaron Kaiway Emil Kheyfets Jing Kwok Andreas Lenkisch Michael Monroe André Moorma Gene Palmer Gerry Palmer Elwood Parsons Bob Patterson Doug Patterson David Pepper Brian Rach Andy Reddig Jim Robles John Rynearson Jeff Smith Andrew Spence Ivan Straznicky Eran Strod Bob Sullivan Bruce Thomas Dan Toohey Bob Whyms Randy White Company Mercury Boeing Radstone CWCEC-Ottawa GD-AIS CWCEC-Leesburg Aitech Tyco Mercury Northrop Grumman Bustronic Mercury Mercury Spectrum Signal CWCEC-S Clarita CWCEC-Ottawa Pentair/Schroff Bustronic Corp. Rockwell Radstone DRS Tactical Systems Foxconn Tyco Aitech GE Fanuc Rockwell TEK Microsystems Boeing VITA GHz Systems Inc. Amphenol CWCEC-Ottawa Mercury Hybricon CWCEC-S Clarita Mercury Northrop Grumman CWCEC-Ottawa TASK GROOP At the time this standard was competed, task group membership included: Page 3 of 17 Do not specify or claim conformance to this document VITA 46.4-200x/D0.3

Comments, Corrections, or Additions Comments, corrections, or additions to this proposed standard may be forwarded to: Val Gueorguiev, Draft Editor Aitech Defense Systems Inc. 9301 Oakdale Avenue Chatsworth, CA 91311 (818) 350-6814 EMAIL: vgueorguiev@rugged.com VSO and Other Standards Information about other standards being developed by VSO as well as VME Product Directories, VME Handbooks, and general information about the VME market is available from the VITA office listed on the front cover. Draft Summary This is draft 02of this standard. The original content of this draft standard was presented and agreed upon at the xxx VSO meeting. See the draft history for a summary list of the major changes made to each draft. Draft History Draft No. 0.1 Date 02/20/2006 0.2 0.3 05/06/2006 08/20/2007 Comments & Major Changes/Updates Preliminary Draft Removed 2X PCI Express Links from Table 4. Updated Section 5 per recommendations provided by Brian Rach. Update per minutes from the VPX meeting in Vancouver 18, 19-Jul-2007. Issues to be resolved 1 2 3 Page 4 of 17 Do not specify or claim conformance to this document VITA 46.4-200x/D0.3

1 Introduction The VITA 46 standard regulates the standardization of switched serial interconnects for VME bus applications, with specific concern taken to allow deployment in ruggedized environments. The VITA 46.0 base standard defines the physical features of VITA 46 components. The VITA 46.4 standard is a subset of VITA 46 standard and defines the implementation of PCI Express, high speed serial interconnect interface within VITA 46.0 form factor constraints. 1.1 Objective The objectives of this document are: - To assign 16 PCI Express Lanes over the data links defined in VITA 46.0. - To recommend signal mapping for 32 PCI Express Lanes over the data links defined in VITA 46.0. - To define requirements and constraints for the implementation of PCI Express Physical Layer in VITA 46.0 environment. To define auxiliary signals necessary to implement PCI Express interface in a system environment. - The guidelines and design rules defined in this standard are intended to be consistent with the applicable sections of the PCI Express Specification. It is expected that VITA 46.4 products will comply with PCI Express Transaction, Data Link and Physical Layer Specifications in order to maximize interoperability with other PCI Express hardware and software products. 1.2 PCI Express Technology Overview. PCI Express provides signaling architecture supporting high-speed serial communication and allows a smooth transition from PCI to a faster, more scalable interconnect technology. PCI Express defines three logical layers: the Transaction Layer, the Data Link Layer and the Physical Layer. The Transaction Layer and the Data Link Layer generate, transmit and receive data packets. The Physical Layer converts the information into appropriate serialized format and transmits it across the PCI Express Link. The PCI Express fabric is composed of point-to-point Links that interconnect the components of the fabric – Endpoint, Root Complex, Switch and Bridge. The First Generation of PCI Express Technology defines a signaling rate of 2.5 Gigabit/second /Lane and uses encoding scheme supporting embedded data clock. PCI Express Technology develops on the foundation of the PCI architecture and provides complete backwards compatibility and interoperability with the existing PCI software, ensuring successful migration path at system level and broad industry support. Page 5 of 17 Do not specify or claim conformance to this document VITA 46.4-200x/D0.3

1.3 Terminology Specification Key Words To avoid confusion and to make very clear what the requirements for compliance are, many of the paragraphs in this standard are labeled with keywords that indicate the type of information they contain. These keywords are listed below: Rule Recommendation Suggestion Permission Observation Any text not labeled with one of these keywords should be interpreted as descriptive in nature. These will be written in either a descriptive or a narrative style. The keywords are used as follows: Rule .: Rules form the basic framework of this draft standard. They are sometimes expressed in text form and sometimes in the form of figures, tables or drawings. All rules shall be followed to ensure compatibility between board and backplane designs. All rules use the "shall" or "shall not" words to emphasize the importance of the rule. The "shall" or "shall not" words are reserved exclusively for stating rules in this draft standard and are not used for any other purpose. Recommendation .: Wherever a recommendation appears, designers would be wise to take the advice given. Doing otherwise might result in poor performance or awkward problems. Recommendations found in this standard are based on experience and are provided to designers to speed their traversal of the learning curve. All recommendations use the "should" or "should not" words to emphasize the importance of the recommendation. The "should" or "should not" words are reserved exclusively for stating recommendations in this draft standard and are not used for any other purpose. Permission .: In some cases a rule does not specifically prohibit a certain design approach, but the reader might be left wondering whether that approach might violate the spirit of the rule or whether it might lead to some subtle problem. Permissions reassure the reader that a certain approach is acceptable and will cause no problems. All permissions use the "may" words to emphasize the importance of the permission. The lower-case "may" words are reserved exclusively for stating permissions in this draft standard and are not used for any other purpose. Observation .: Observations do not offer any specific advice. They usually follow naturally from what has just been discussed. They spell out the implications of certain rules and bring attention to things that might otherwise be overlooked. They also give the rationale behind certain rules so that the reader understands why the rule must be followed. Page 6 of 17 Do not specify or claim conformance to this document VITA 46.4-200x/D0.3

VITA 46 Definitions The following terms may be used within the body of the specification. In this context, they have the following meanings: 5x2 wafers- A single-ended wafer providing five signal contacts and two ground contacts Air cooled – a plug-in module which is intended to have heat removed by transfer to an air stream flowing over the module Chassis Ground – See Safety Ground. Conduction cooled – a plug-in module which is intended to have heat removed by transfer to the chassis through mechanical contact with a chassis component Dedicated System – A system designed for a single use or application; not available to general users. Such a system will usually embody a feature which precludes full compliance with this standard. Differential Wafer - A pair of wafers designed for the connection of high speed (up to 5 GBaud) signaling intended for use with differential pair signals, such as LVDS. ESD – Electrostatic discharge. Ground – Unless otherwise specified the term Ground means logic ground or signal ground, not safety ground. Also referred to as RF Ground. See Safety Ground and RF Ground. MultiGig RT2 7-Row – A family of connectors, or their equivalent, used in VITA 46 systems for high speed interconnections. Power Wafer – A wafer providing two contacts which are intended to be used to supply prime power to a plug-in module. PS Module – A plug-in module which provides an allocation of differential connectors in addition to an allocation of single ended connectors, suitable for implementation of both serial fabric and parallel bus interconnection in the same module. Thus Parallel Serial (PS) to indicate the combination. RF Ground - A distributed low impedance common reference between plug-in module circuitry/shields and other electrical equipment (rack, other plug-in modules, and power sources). See Safety Ground and Ground. Safety Ground - Plug-in module features that ensure hazardous voltages are not present on accessible hardware under single fault conditions. See Ground and RF Ground. SS Module – A plug-in module which provides differential connectors in all connector locations, suitable for serial fabric or high speed I/O interconnections. Thus Serial Serial (SS) to indicate fabric connections are the only connections anticipated to be used. VME Board – A plug-in module that complies with the ANSI/VITA-1.1, VME64 Extensions standard. Vs – Notation representing Prime Power from the system to the plug-in module. VXS – a VMEbus Switched Serial (VITA-41) payload module PCI Express Definitions Endpoint – A device with a Type 00h configuration space header. Lane – A set of differential signal pairs – one pair for transmission, one pair for reception. Link – A collection of two ports and their interconnecting Lanes. Dual simplex communication path between two components. Page 7 of 17 Do not specify or claim conformance to this document VITA 46.4-200x/D0.3

Packet – A fundamental unit of information transfer consisting of header that, in some cases, is followed by data payload. Root Complex – An entity that includes a Host Bridge and one or more Root Ports. 1.4 References The following publications are used in conjunction with this standard. In the event that one of these standards is revised, the revised standard should be used unless it conflicts with this standard. The following standards are available from the VMEbus International Trade Association. http://www.vita.com ANSI/VITA 1-2002 American National Standard for VME64 ANSI/VITA 1.1-1997 American National Standard for VME64 Extensions ANSI/VITA 46.0 - 2005-46.0 Advanced Module Format for Fabric Based systems The following are available from their respective maintainers: IEEE 1101.1-1998, IEEE Standards for Mechanical Core Specifications for Microcomputers Using IEC 603-2 Connectors IEEE 1101.2-1992 IEEE Standard for Mechanical Core Specifications for Conduction-Cooled Eurocards PCI Express Base Specification Page 8 of 17 Do not specify or claim conformance to this document VITA 46.4-200x/D0.3

资料库

VITA46.4 PCIE.pdf

相关推荐

开发技术

热门标签

最新资料