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OV480 Hardware Application Guide.pdf

发布时间：2022-06-08 发布人：admin 分类：说明书 资料大小：0.38M 资料格式：pdf 举报 版权申诉
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    OV480 OV480 Hardware Application Guide Revision 1.2c Last Modified August 2, 2013 1 Introduction This document will cover various details on the system hardware application aspect of OV480. OV480 is a companion ASIC to OV7955 and OV10635 automotive sensors. Its primary function is wide-angle fisheye distortion and perspective correction. The following parts are needed to put together a minimal functioning OV480 system: 2 Power Figure 1. Power Connections 2.1 Rails OV480 requires 2 power rails: 3.3V I/O and 1.2V core voltage. A 1.2V linear regulator is available on-chip to provide the core power. VRIAC and VRIB pins supplies power to internal regulator, brownout module, and PLLs. Even if the internal regulator is not used, power should still be connected to these pins. 2.2 Noise PLLVDD and DACVDD supply analog circuitry. PLLVDD can be shared with CVDD, and • OV7955 or OV10635 sensor • OV480 companion ASIC • SPI Serial flash • 3.3V supply I2C EEPROM is optional for storing run-time information. DACVDD can share power with PVDD. However if the rails are noisy, additional filtering and/or decoupling may be needed for better performance. 2.3 Power Dissipation When using internal linear regulator, pay attention to power dissipation and thermal resistance figures. θJA Typ Max Unit 50.5 Description °C/W Thermal resistance Junction-to-air 0m/s 1.2V core consumption 3.3V I/O consumption Junction temperature Ambient temperature 128 mA 34.8 mA 125 °C °C 105 ICVDD IPVDD TJunc TAmb The thermal resistance value is for a 4-layer 25x50x1.6mm (1x2in) FR4 PCB. If using internal linear regulator, you must also include the power dissipated across the regulator. If the maximum junction temperature will be exceeded based on your operating condition, external switching regulator is recommended. 1 OmniVision Confidential
    3 I/O pins The following I/O pins are tri-stated by default when unused: GPIO[6:0] DVP output pins These can be left floating when unused. 4 Part Selection 4.1 Crystal Crystal should be 50ppm with 18pF load capacitance. The evaluation board may operate from two possible crystal frequencies. Frequency 27.000MHz 24.545454MHz Fox Electronics 507-24.545454-1 Recommended for NTSC TV output Manufacturer’s part # Abracon ABM8-27.000MHz Notes ܫ௢௨௧ = ܦ௜௡ × ESRmin 0.5Ω 0.3Ω 0.1Ω 0.05Ω For NTSC TV output, we recommend using 24.545454MHz square-pixel frequency. 4.2 Capacitors Decoupling capacitors should be ceramic-type. The evaluation board uses 100µF, 22µF, and a few 0.1µF for both 1.2V and 3.3V rails. For smaller capacitor values here is the guideline. Cap 0.47µF 1.0µF 2.2µF 4.7µF 4.3 Resistors 4.3.1 DAC Based on measured DAC output, simulation data, the bandgap register 0x7FEE should be set to 0x08, resulting in Vref =1.18V. With this Vref, the TV encoder requires a 1542Ω trimming resistor on CVBSREF pin (A6) to drive accurate levels onto a 75Ω load. We recommend a 1% 1.54KΩ resistor for this. When using 1.54KΩ, the following are the expected levels: 10-bit DAC 16 240 800 (V) 0.020 0.306 1.022 Current (mA) Voltage 0.27 4.08 13.60 -40 0 100 R2 R3 45K 25K 5K 3.00 40K 25K 5K 2.80 R1 Vthre 42.5K 25K 5K 2.90 IRE For double-terminated applications with 75Ω on both ends of the cable, a 768Ω resistor is needed. The equation for DAC output is: ܸ௥௘௙ ܴ௧௥௜௠ × ܭ Where Vref = 1.18V and K = 45 (measured). Din is the input to the DAC, 0~1023, and Rtrim is the external current setting resistor. The DAC has a maximum sustained current output of 40mA. This means the minimum Rtrim is ~560Ω. Maximum practical Rtrim is 10KΩ before the curve starts losing linearity. 4.3.2 Brown-out The brown-out detection circuit requires 3 resistors with 1% accuracy to set the high and low threshold levels. Three pre-calculated combinations are provided in the following table: When the main 3.3V rail is < Vthre, the brown- out circuit will kick in to reset the chip, and won’t release until the power is > Vrel. Vrel Vhyst 3.16 0.16 3.05 0.15 2.95 0.15 1023 140 17.30 1.306 2 OmniVision Confidential
    When not using brownout circuit, BON_PDI should be pulled up. VMON and VMONLO can float, but better to be grounded. 4.4 Reset An RC reset circuit is sufficient to properly power-on reset the chip. For reliable operation, RESETN should be asserted > 100us after power-stable. By this time the oscillator should be up and running. A good rule of thumb is to use RC time constant of 1~10ms. 4.5 Flash The requirement for SPI serial flash is: 1) >= 10MHz operation 2) 3-byte (24-bit) addressing. 3) Standard SPI flash read command 0x03 @ 10MHz This covers flash sizes ranging from 512kbit to 128mbit. Flash that can run faster > 50MHz and supports fast read command 0x0B is preferable. 5 In-system programming It may be necessary to program the SPI flash after mounting on the PCB. OV480 supports in-system- programming of SPI flash by tri-stating its SPI bus. This can be done either of two ways: 1) First is to pull the TP pin high while holding TMODE low. The TP pin is normally pulled low with a 10KΩ resistor. 2) Second is to disable SPI master output enable by programming a register through I2C interface. Register 0x0305 bit0 is the tri-state control. When the bit is high, SPI bus is tri-stated. The diagram below shows recommended connection between OV480, SPI flash, and in-system programmer. The series resistors are there to help prevent damage and other problems caused by signal contention. A weak pull-up on flash SSn and a weak pull-down on SCLK is recommended if there’s a chance of prolonged tri-state condition on these lines while the flash is powered. This will prevent accidental toggling, although in practice we rarely see any detrimental effects if the resistors are left out. Figure 2. ISP with SPI flash Ω K 0 1 Ω K 0 1 Ω K 0 1 p r o g r a m m e r I n - s y s t e m 3 OmniVision Confidential
    6 Layout A 4-layer PCB with full ground plane is the minimum recommended stacking scheme. It is beneficial both for layout and heat dissipation. Unless absolutely necessary to solve power noise problems, ground layer should be a single contiguous plane. Plane carving should be on the power layer only. Pay particular attention to high-speed signals crossing planes. If ground plane is carved, high-speed signals should NEVER cross the ground planes. 4 OmniVision Confidential
    7 Schematics 1 L1 100U 2 J1 VPOOL LV = 4.0 to 6.0V VDD 2 1 2 1 2 1 2 D1 C1 0.1U 1 2 1 1 2 Main Power Switch PMOSFET 3 2 C2 0.1U 1 Q1 2 1 3 2 C4 470P1 3 1 2 R6 10K 1 + 2 1 C7 100U 2 2 10K S1 2 1 1 U45 1 2 4 R9 C10 1.0U 1 3 2 1 2 3 4 7SZ74 CLK D Q GND VCC PRE RST Q 8 7 6 5 U5 Power On/Off Control 2 1 1 2 R8 470K C9 0.1U SVDD VDD 21 3 4 8 7 6 5 C14 0.1U 1 + 2 2 C15 100U 1 C13 22U 21 3 4 8 7 6 5 C16 0.1U C12 22U 2 1 D33V 1 2 1 VOUT = 2.35V x 2.5 x RDIVIDER R1 100K VDD R3 127K 1 2 3 4 LMZ10500 EN VREF VCON VIN FB PGND SGND VOUT 8 7 6 5 2 2 2 1 Vout = 3.3~4.3V U1 1 2 1 VDD R2 100K VDD SWSV 2 C3 470P1 R4 25.5K 2 2 1 VOUT = 2.35V x 2.5 x RDIVIDER 1 2 3 4 LMZ10500 EN VREF VCON VIN FB PGND SGND VOUT 8 7 6 5 U2 150K R5 C5 22U May not achieve > 3.6V, have to test C6 22U SW33V 2 R20 0 1 D33V Power selectors and measurement points SW12V SWSV 1 SVDD 2 D12V 2 JUMPPAD T25 3 VDD 2 C8 470P1 JUMPPAD T26 1 3 LDO12V 1 2 1 2 VOUT = 2.35V x 2.5 x RDIVIDER R7 100K VDD R10 127K 2 1 C11 22U 1 2 3 4 LMZ10500 EN VREF VCON VIN FB PGND SGND VOUT 8 7 6 5 U3 VDD SW12V VDD SW33V T1 MTNG HOLE T2 MTNG HOLE 1 1 Standard opening dia for M3 screws (0.125") VDD SWSV D33V 2 R11 2 R12 2 R13 1 1.5K 1 2 2 820 820 1 2 1 D2 1 D3 1 D4 Green Orange Orange VDD SWSV SW33V SW12V LDO12V 1 1 1 1 1 P1 P1 P1 P1 P1 T3 T5 T8 T10 T22 T4 T6 T9 T11 T21 P1 P1 P1 P1 P1 1 1 1 1 1 1 + 2 2 C17 100U 1 C18 22U 21 3 4 21 3 4 1 1 C21 0.1U 1 C22 0.1U 1 C23 0.1U C24 0.1U 8 7 6 5 C19 0.1U 8 7 6 5 2 C20 0.1U 2 2 2 D12V 1 + 2 2 C26 100U 1 C25 22U 21 3 4 8 7 6 5 C27 0.1U 1 1 C29 0.1U 1 C30 0.1U 1 C31 0.1U C32 0.1U 2 2 2 2 Title Size H_D[9:0] H_HREF H_VSY NC H_PCLK H_SDA H_SCL H_XCLK SP_MOSI SP_MISO SP_SCK SP_CS# RESET# RSTBTN S_D[9:0] S_HREF S_VSYNC S_PCLK S_SDA S_SCL S_XCLK GPIO[7:0] E_SCL E_SCL CVP POWER Custom Document Number Rev B Date: Monday , July 09, 2012 Sheet 2 of 4 5 OmniVision Confidential
    TMODE RESET# XO XI 1542 for 75 ohm 771 for 37.5 ohm 2 R14 1542 1 CVP 1 CVNCVN CVNCVN 1 P1 T13 TESTPAD 2 R16 75 D33V D12V U6B DACVDD PLLVDD PVDD1 PVDD2 PVDD3 PVDD4 PVDD5 CVDD4 CVDD3 CVDD2 CVDD1 B7 B4 F5 G6 F4 C7 H6 D5 D6 G4 F6 PVSS1 PVSS2 PVSS3 PVSS4 CVSS4 CVSS3 CVSS2 CVSS1 DACVSS VRGND2 VRGND1 PLLVSS A1 J1 A9 J9 E4 E6 G5 E5 B8 C2 C1 B3 D33V 1 2 1 VMON VMONLO 2 1 2 R15 45K R17 25K R18 5K R1A shoud use 16K, 10K, 2K R1B should use 45K, 25K, 5K Power Good T23 TESTPAD P1 1 BON 2 R19 1 2 820 1 D5 H_HREF H_VSY NC H_BLANK H_PCLK 1 P1 T14 TESTPAD XO 2 R50 1M 1 XI Y 1 1 4 2 27MHz 3 2 C44 18P 1 2 C43 18P 1 H_D[9:0] H_HREF H_VSYNC H_PCLK H_SDA H_SCL H_XCLK SP_MOSI SP_MISO SP_SCK SP_CS# RESET# RSTBTN S_D[9:0] S_HREF S_VSY NC S_PCLK S_SDA S_SCL S_XCLK GPIO[7:0] E_SCL E_SDA CVP Title Size A OV480 Document Number OV480 Date: Monday , June 03, 2013 Sheet 3 of 4 Rev B C33 1.0U 1 2 LDO12V D33V S_SDA S_SCL E_SDA E_SCL H_SDA H_SCL SP_MOSI SP_MISO SP_SCK SP_CS# S_D2 S_D3 S_D4 S_D5 S_D6 S_D7 S_D8 S_D9 LDO U6A B2 B1 A4 A3 A2 VROE VROCD VROAB VRIB VRIAC SCCB E3 F3 SM0_SDA SM0_SCL E9 SM1_SDA F8 SM1_SCL B5 SS_SDA C6 SS_SCL D7 C9 B9 C8 J2 J3 J4 H4 H2 H3 G3 G1 MOSI MISO SCK SSN SPI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 SNR_IN S_HREF S_VSY NC S_PCLK S_XCLK F2 G2 HREFI F1 E1 VSY NCI PLCKI CCLK TMODE RESETN XO XI SYS TV OUT CVBSREF CVBS CVBSN BON VMON VMONLO TP BON_PDI GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 T U O _ P V D HREFO VSY NCO BLANKO PCLKO J8 H1 D1 D2 A6 A7 A8 C4 A5 C3 G7 E2 E8 D8 D9 E7 C5 D4 D3 J7 J6 J5 H5 H8 H7 G8 H9 F7 F9 B6 G9 BON VMON VMONLO TP BON_PDI GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 H_D2 H_D3 H_D4 H_D5 H_D6 H_D7 H_D8 H_D9 TP = ISP when TMODE = LO D33V 2 1 3 4 TMODE TP 1 2 4 3 2 1 3 4 R47 10K S18 R38 1K D33V 1 3 JUMPPAD T24 BON_PDI 2 Pull up to disable brownout circuit 6 OmniVision Confidential
    TESTPAD T15 1 P 1 S_D2 S_D4 S_D6 S_D8 S_PWDN S_SDA S_SCL S_XCLK 2 R23 2 R25 2 R27 33 1 1 33 1 33 D33V 2 1 3 4 ECO R48 2.7K H_D2 H_D4 H_D6 H_D8 H_SDA H_SCL 2 R29 2 R31 33 1 1 33 S_D3 S_D5 S_D7 S_D9 SVDD H_D3 H_D5 H_D7 H_D9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 J5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 J8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 D33V 1 2 R37 10K D33V M_CS# M_MISO 1 2 3 4 M25P16 CS SO WP GND VCC HOLD SCK SI 8 7 6 5 U9 D33V M_SCK M_MOSI I2C inter-bus connections Only 1 set of I2C pullups exist and is done as ECO for A_SDA/A_SCL If R43 or R44 are removed, the disconnected I2C busses will need their own pull-ups H_SDA H_SCL 2 1 3 4 A_SDA A_SCL 3 4 2 1 S_SDA S_SCL 1 2 R40 10K 2 R30 2 R32 2 R34 33 33 33 1 1 1 H_HREF H_VSYNC H_PCLK D33V 21 34 R35 2.7K E_SCL E_SDA D33V 1 2 3 4 .24LC128 A0 A1 A2 GND VCC WP SCL SDA 8 7 6 5 U7 D33V 2 R39 1K 1 2 2 R41 2 S8 1 1 1 10K C35 1.0U 1 2 RSTBTN D33V RESET# 6 5 4 6 V 4 1 2 3 1 G 3 U10 R43 33 33 R44 Aardvark cable Soft-isolation between Aardvark and OV480 to SPI flash HEADER 5X1 SP_MOSI SP_MISO SP_SCK SP_CS# 5 6 7 8 4 3 2 1 M_MOSI M_MISO M_SCK M_CS# 5 6 7 8 4 3 2 1 A_MOSI A_MISO A_SCLK A_SS R45 33 R46 33 1 2 3 4 5 1 2 3 4 5 J11 A_SCL A_SDA A_MISO A_SCLK A_SS 1 3 5 7 9 1 3 5 7 9 J12 2 4 6 8 10 2 4 6 8 10 A_MOSI Title Size 2 R24 2 R26 2 R28 33 33 33 1 1 1 S_HREF S_VSY NC S_PCLK D33V HEADER 4X1 H_SDA H_SCL S_SDA S_SCL E_SDA E_SCL 1 2 3 4 1 2 3 1 2 3 1 2 3 4 J6 1 2 3 J7 1 2 3 J9 D33V R51 10K R52 10K R53 10K 2 2 2 1 1 1 GPIO0 GPIO1 GPIO2 1 1 1 2 2 2 1 1 1 2 2 2 S3 S4 S5 1 1 1 2 2 2 C34 0.1U C45 0.1U C46 0.1U H_D[9:0] H_HREF H_VSY NC H_PCLK H_SDA H_SCL H_XCLK SP_MOSI SP_MISO SP_SCK SP_CS# RESET# RSTBTN S_D[9:0] S_HREF S_VSYNC S_PCLK S_SDA S_SCL S_XCLK GPIO[7:0] E_SCL E_SDA CVP Flex cable HEADER 8X1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 J13 D33V GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 RSTBTN 10 9 8 7 6 5 4 3 2 1 J14 10 9 8 7 6 5 4 3 2 1 FPC TV Output CVP 1 Optional 75ohm R42 NM 2 2 1 L2 1 1.8U 2 1 C36 2 22P 2 C37 270P C38 330P1 J10 2 1 RCA JACK Pi filter recommended for sampling-type digital receivers to prevent aliasing I/O Document Number Custom Rev B Date: Monday , June 03, 2013 Sheet 4 of 4 7 OmniVision Confidential
    BVDD BTN0 BTN1 BTN2 BTN3 BTN4 BTN5 BTN6 BTN7 1 1 2 3 4 5 6 7 8 9 10 FPC 1 2 3 4 5 6 7 8 9 10 J15 7 8 5 6 3 4 1 2 BVDD R60 10K R59 10K R58 10K R61 10K R57 10K R54 10K R55 10K R56 10K 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 P1 T16 TESTPAD S9 S11 S13 S15 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 BTN0 BTN1 BTN2 BTN3 BTN4 BTN5 BTN6 BTN7 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 S10 S12 S14 S16 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 Offboard Buttons C52 0.1U MVDD HEADER 4X1 C53 0.1U C51 0.1U C54 0.1U MVDD M_SDA M_SCL 1 2 3 4 1 2 3 4 J17 MVDD R62 10K 1 2 1 2 M_RST C39 1.0U 2 R49 10K 1 C2CK 2 2 S17 1 1 1 1 C41 0.1U C42 4.7U 2 2 Offboard MCU 1 2 3 4 5 C8051 RST/C2CK P0/VREF GND VDD VREGIN P1/C2D P2/X1 P3/X2 P4/TX P5/RX U11 10 9 8 7 6 1 P1 TESTPAD T18 C50 0.1U C47 0.1U C49 0.1U C48 0.1U OFFBOARD C2D M_SCL M_SDA TXD RXD T17 TESTPAD P1 T19 TESTPAD P1 1 1 C2D C2CK M_SDA M_SCL M_RST TXD RXD MVDD 1 2 3 4 5 6 7 8 9 10 FPC 1 2 3 4 5 6 7 8 9 10 J16 Title Size Custom Document Number Rev A Date: Tuesday , July 24, 2012 Sheet 5 of 5 8 Revision History 1.0: First release 1.1: Style change 24.54MHz Crystal information Updated to characterized power consumption data 1.2: Add notes on VRIB/VRIAC inputs Updated DAC trimming resistor parameters 8 OmniVision Confidential
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