8383 - Behavioral 15:39:59 08/06/2010 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity coder is Port ( sel : in STD_LOGIC_VECTOR (7 downto 0); sck : out std_logic; seg : out std_logic_vector(7 downto 0)); end coder; architecture Behavioral of coder is signal a : std_logic:='1'; begin sck<=a; seg <= "00111111" "00000110" when when sel(0) = '1' else sel(1) = '1' else "01011011" "01001111" "01100110" sel(2) = '1' else when when sel(3) = '1' else when sel(4) = '1' else 

"01101101" "01111101" "00000111" "ZZZZZZZZ"; when when when sel(5) = '1' else sel(6) = '1' else sel(7) = '1' else end Behavioral;