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ARM Architecture Reference Manual for ARMv8-A.pdf
ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
Contents
Preface
About this manual
Using this manual
Part A, Introduction and Architecture Overview
Part B, The AArch64 Application Level Architecture
Part C, The A64 Instruction Set
Part D, The AArch64 System Level Architecture
Part E, The AArch32 Application Level Architecture
Part F, The AArch32 Instruction Sets
Part G, The AArch32 System Level Architecture
Part H, External Debug
Part I, Memory-mapped Components of the ARMv8 Architecture
Part J, Architectural Pseudocode
Part K, Appendixes
Conventions
Typographic conventions
Signals
Numbers
Pseudocode descriptions
Assembler syntax descriptions
Additional reading
ARM publications
Other publications
Feedback
Feedback on this manual
Part A: ARMv8 Architecture Introduction and Overview
A1: Introduction to the ARMv8 Architecture
A1.1 About the ARM architecture
A1.2 Architecture profiles
A1.2.1 Debug architecture version
A1.3 ARMv8 architectural concepts
A1.3.1 Execution state
A1.3.2 The ARM instruction sets
A1.3.3 System registers
The ARM Generic Interrupt Controller System registers
A1.3.4 ARMv8 Debug
A1.4 Supported data types
A1.4.1 Vector formats
Vector formats in AArch64 state
Vector formats in AArch32 state
A1.4.2 Half-precision floating-point formats
A1.4.3 Single-precision floating-point format
A1.4.4 Double-precision floating-point format
A1.4.5 Fixed-point format
A1.4.6 Conversion between floating-point and fixed-point values
A1.4.7 Polynomial arithmetic over {0, 1}
Pseudocode description of polynomial multiplication
A1.5 Floating-point and Advanced SIMD support
A1.5.1 Instruction support
A1.5.2 Floating-point standards, and terminology
A1.5.3 ARM standard floating-point input and output values
A1.5.4 Flush-to-zero
A1.5.5 NaN handling and the Default NaN
A1.6 Cryptographic Extension
A1.7 The ARM memory model
Part B: The AArch64 Application Level Architecture
B1: The AArch64 Application Level Programmers’ Model
B1.1 About the Application level programmers’ model
B1.2 Registers in AArch64 Execution state
B1.2.1 Registers in AArch64 state
Pseudocode description of registers in AArch64 state
B1.2.2 Process state, PSTATE
Accessing PSTATE fields at EL0
B1.2.3 System registers
Performance Monitors support
B1.3 Software control features and EL0
B1.3.1 Exception handling
B1.3.2 Wait for Interrupt and Wait for Event
B1.3.3 The YIELD instruction
B1.3.4 Application level cache management
B1.3.5 Debug events
B2: The AArch64 Application Level Memory Model
B2.1 Address space
B2.2 Memory type overview
B2.3 Caches and memory hierarchy
B2.3.1 Introduction to caches
B2.3.2 Memory hierarchy
The cacheability and shareability memory attributes
B2.3.3 Application level cache instructions
B2.3.4 Implication of caches for the application programmer
Data coherency issues
Synchronization and coherency issues between data and instruction accesses
B2.3.5 Preloading caches
B2.4 Alignment support
B2.4.1 Instruction alignment
B2.4.2 Alignment of data accesses
B2.4.3 Unaligned data access restrictions
B2.5 Endian support
B2.5.1 General description of endianness in the ARM architecture
B2.5.2 Instruction endianness
B2.5.3 Data endianness
Instructions to reverse bytes in a general-purpose register or a SIMD and floating-point register
Endianness in SIMD operations
B2.6 Atomicity in the ARM architecture
B2.6.1 Requirements for single-copy atomicity
B2.6.2 Properties of single-copy atomic accesses
B2.6.3 Multi-copy atomicity
B2.6.4 Requirements for multi-copy atomicity
B2.6.5 Concurrent modification and execution of instructions
B2.7 Memory ordering
B2.7.1 Observability and completion
Completion of side-effects of accesses to Device memory
B2.7.2 Ordering requirements
Address dependencies and order
B2.7.3 Memory barriers
Instruction Synchronization Barrier (ISB)
Data Memory Barrier (DMB)
Data Synchronization Barrier (DSB)
Shareability and access limitations on the data barrier operations
Load-Acquire, Store-Release
B2.7.4 Summary of the memory ordering rules
Terms used in the summary of the memory ordering rules
B2.8 Memory types and attributes
B2.8.1 Normal memory
Shareable Normal memory
Non-shareable Normal memory
Write-Through Cacheable, Write-Back Cacheable and Non-cacheable Normal memory
Multi-register loads and stores that access Normal memory
B2.8.2 Device memory
Gathering
Reordering
Early Write Acknowledgement
Multi-register loads and stores that access Device memory
B2.8.3 Memory access restrictions
B2.9 Mismatched memory attributes
B2.10 Synchronization and semaphores
B2.10.1 Exclusive access instructions and Non-shareable memory locations
Changes to the local monitor state resulting from speculative execution
B2.10.2 Exclusive access instructions and Shareable memory locations
Operation of the global monitor
B2.10.3 Marking and the size of the marked memory block
B2.10.4 Context switch support
B2.10.5 Load-Exclusive and Store-Exclusive instruction usage restrictions
CONSTRAINED UNPREDICTABLE behavior when Load-Exclusive/Store-Exclusive access a different number of registers
B2.10.6 Use of WFE and SEV instructions by spin-locks
Part C: The AArch64 Instruction Set
C1: The A64 Instruction Set
C1.1 Introduction
C1.2 Structure of the A64 assembler language
C1.2.1 Common syntax terms
C1.2.2 Instruction Mnemonics
C1.2.3 Condition Code
C1.2.4 Register names
General-purpose register file and the stack pointer
SIMD and floating-point register file
SIMD and floating-point scalar register names
SIMD vector register names
SIMD vector element names
C1.3 Address generation
C1.3.1 Register indexed addressing
C1.3.2 PC-relative addressing
C1.3.3 Load/Store addressing modes
Address calculation
C1.4 Instruction aliases
C2: About the A64 Instruction Descriptions
C2.1 Understanding the A64 instruction descriptions
C2.1.1 The title
C2.1.2 An introduction to the instruction
C2.1.3 The instruction encoding or encodings
C2.1.4 Any alias conditions, if applicable
C2.1.5 A list of the assembler symbols for the instruction
C2.1.6 Pseudocode describing how the instruction operates
C2.1.7 Notes, if applicable
C2.2 Conventions used in AArch64 instruction and System register descriptions
C2.2.1 Fixed values in AArch64 instruction and System register descriptions
C3: A64 Instruction Set Overview
C3.1 Branches, Exception generating, and System instructions
C3.1.1 Conditional branch
C3.1.2 Unconditional branch (immediate)
C3.1.3 Unconditional branch (register)
C3.1.4 Exception generation and return
Exception generating
Exception return
Debug state
C3.1.5 System register instructions
C3.1.6 System instructions
C3.1.7 Hint instructions
C3.1.8 Barriers and CLREX instructions
C3.2 Loads and stores
C3.2.1 Load/Store register
C3.2.2 Load/Store register (unscaled offset)
C3.2.3 Load/Store Pair
C3.2.4 Load/Store Non-temporal Pair
C3.2.5 Load/Store Unprivileged
C3.2.6 Load-Exclusive/Store-Exclusive
C3.2.7 Load-Acquire/Store-Release
C3.2.8 Load/Store scalar SIMD and floating-point
Load/Store scalar SIMD and floating-point register
Load/Store scalar SIMD and floating-point register (unscaled offset)
Load/Store SIMD and Floating-point register pair
Load/Store SIMD and Floating-point Non-temporal pair
C3.2.9 Load/Store Vector
Load/Store structures
Load single structure and replicate
C3.2.10 Prefetch memory
C3.3 Data processing - immediate
C3.3.1 Arithmetic (immediate)
C3.3.2 Logical (immediate)
C3.3.3 Move (wide immediate)
C3.3.4 Move (immediate)
C3.3.5 PC-relative address calculation
C3.3.6 Bitfield move
C3.3.7 Bitfield insert and extract
C3.3.8 Extract register
C3.3.9 Shift (immediate)
C3.3.10 Sign-extend and Zero-extend
C3.4 Data processing - register
C3.4.1 Arithmetic (shifted register)
C3.4.2 Arithmetic (extended register)
C3.4.3 Arithmetic with carry
C3.4.4 Logical (shifted register)
C3.4.5 Move (register)
C3.4.6 Shift (register)
C3.4.7 Multiply and divide
Multiply
Divide
C3.4.8 CRC32
C3.4.9 Bit operation
C3.4.10 Conditional select
C3.4.11 Conditional comparison
C3.5 Data processing - SIMD and floating-point
C3.5.1 Common features of SIMD instructions
C3.5.2 Floating-point move (register)
C3.5.3 Floating-point move (immediate)
C3.5.4 Floating-point conversion
Convert floating-point precision
Convert between floating-point and integer or fixed-point
C3.5.5 Floating-point round to integral
C3.5.6 Floating-point multiply-add
C3.5.7 Floating-point arithmetic (one source)
C3.5.8 Floating-point arithmetic (two sources)
C3.5.9 Floating-point minimum and maximum
C3.5.10 Floating-point comparison
C3.5.11 Floating-point conditional select
C3.5.12 SIMD move
C3.5.13 SIMD arithmetic
C3.5.14 SIMD compare
C3.5.15 SIMD widening and narrowing arithmetic
C3.5.16 SIMD unary arithmetic
C3.5.17 SIMD by element arithmetic
C3.5.18 SIMD permute
C3.5.19 SIMD immediate
C3.5.20 SIMD shift (immediate)
C3.5.21 SIMD floating-point and integer conversion
C3.5.22 SIMD reduce (across vector lanes)
C3.5.23 SIMD pairwise arithmetic
C3.5.24 SIMD table lookup
C3.5.25 The Cryptographic Extensions
C4: A64 Instruction Set Encoding
C4.1 A64 instruction index by encoding
C4.2 Data processing - immediate
C4.2.1 Add/subtract (immediate)
C4.2.2 Bitfield
C4.2.3 Extract
C4.2.4 Logical (immediate)
C4.2.5 Move wide (immediate)
C4.2.6 PC-rel. addressing
C4.3 Branches, exception generating and system instructions
C4.3.1 Compare & branch (immediate)
C4.3.2 Conditional branch (immediate)
C4.3.3 Exception generation
C4.3.4 System
C4.3.5 Test & branch (immediate)
C4.3.6 Unconditional branch (immediate)
C4.3.7 Unconditional branch (register)
C4.4 Loads and stores
C4.4.1 Advanced SIMD load/store multiple structures
C4.4.2 Advanced SIMD load/store multiple structures (post-indexed)
C4.4.3 Advanced SIMD load/store single structure
C4.4.4 Advanced SIMD load/store single structure (post-indexed)
C4.4.5 Load register (literal)
C4.4.6 Load/store exclusive
C4.4.7 Load/store no-allocate pair (offset)
C4.4.8 Load/store register (immediate post-indexed)
C4.4.9 Load/store register (immediate pre-indexed)
C4.4.10 Load/store register (register offset)
C4.4.11 Load/store register (unprivileged)
C4.4.12 Load/store register (unscaled immediate)
C4.4.13 Load/store register (unsigned immediate)
C4.4.14 Load/store register pair (offset)
C4.4.15 Load/store register pair (post-indexed)
C4.4.16 Load/store register pair (pre-indexed)
C4.5 Data processing - register
C4.5.1 Add/subtract (extended register)
C4.5.2 Add/subtract (shifted register)
C4.5.3 Add/subtract (with carry)
C4.5.4 Conditional compare (immediate)
C4.5.5 Conditional compare (register)
C4.5.6 Conditional select
C4.5.7 Data-processing (1 source)
C4.5.8 Data-processing (2 source)
C4.5.9 Data-processing (3 source)
C4.5.10 Logical (shifted register)
C4.6 Data processing - SIMD and floating point
C4.6.1 Advanced SIMD across lanes
C4.6.2 Advanced SIMD copy
C4.6.3 Advanced SIMD extract
C4.6.4 Advanced SIMD modified immediate
C4.6.5 Advanced SIMD permute
C4.6.6 Advanced SIMD scalar copy
C4.6.7 Advanced SIMD scalar pairwise
C4.6.8 Advanced SIMD scalar shift by immediate
C4.6.9 Advanced SIMD scalar three different
C4.6.10 Advanced SIMD scalar three same
C4.6.11 Advanced SIMD scalar two-register miscellaneous
C4.6.12 Advanced SIMD scalar x indexed element
C4.6.13 Advanced SIMD shift by immediate
C4.6.14 Advanced SIMD table lookup
C4.6.15 Advanced SIMD three different
C4.6.16 Advanced SIMD three same
C4.6.17 Advanced SIMD two-register miscellaneous
C4.6.18 Advanced SIMD vector x indexed element
C4.6.19 Cryptographic AES
C4.6.20 Cryptographic three-register SHA
C4.6.21 Cryptographic two-register SHA
C4.6.22 Floating-point compare
C4.6.23 Floating-point conditional compare
C4.6.24 Floating-point conditional select
C4.6.25 Floating-point data-processing (1 source)
C4.6.26 Floating-point data-processing (2 source)
C4.6.27 Floating-point data-processing (3 source)
C4.6.28 Floating-point immediate
C4.6.29 Conversion between floating-point and fixed-point
C4.6.30 Conversion between floating-point and integer
C5: The A64 System Instruction Class
C5.1 The System instruction class encoding space
C5.1.1 Principles of the System instruction class encoding
System register width
C5.1.2 System instruction class encoding overview
UNDEFINED behaviors
C5.1.3 op0==0b00, architectural hints, barriers and CLREX, and PSTATE access
Architectural hint instructions
Barriers and CLREX
Instructions for accessing the PSTATE fields
C5.1.4 op0==0b01, cache maintenance, TLB maintenance, and address translation instructions
Cache maintenance instructions, and data cache zero
Address translation instructions
TLB maintenance instructions
Reserved encoding space for IMPLEMENTATION DEFINED instructions
C5.1.5 op0==0b10, Moves to and from debug and trace System registers
Instructions for accessing debug System registers
C5.1.6 op0==0b11, Moves to and from non-debug System registers and Special-purpose registers
Instructions for accessing non-debug System registers
Instructions for accessing Special-purpose registers
Reserved encodings for IMPLEMENTATION DEFINED registers
C5.2 Special-purpose registers
C5.2.1 CurrentEL, Current Exception Level
Field descriptions
Accessing the CurrentEL:
C5.2.2 DAIF, Interrupt Mask Bits
Field descriptions
Accessing the DAIF:
C5.2.3 DLR_EL0, Debug Link Register
Field descriptions
Accessing the DLR_EL0:
C5.2.4 DSPSR_EL0, Debug Saved Program Status Register
Field descriptions
Accessing the DSPSR_EL0:
C5.2.5 ELR_EL1, Exception Link Register (EL1)
Field descriptions
Accessing the ELR_EL1:
C5.2.6 ELR_EL2, Exception Link Register (EL2)
Field descriptions
Accessing the ELR_EL2:
C5.2.7 ELR_EL3, Exception Link Register (EL3)
Field descriptions
Accessing the ELR_EL3:
C5.2.8 FPCR, Floating-point Control Register
Field descriptions
Accessing the FPCR:
C5.2.9 FPSR, Floating-point Status Register
Field descriptions
Accessing the FPSR:
C5.2.10 NZCV, Condition Flags
Field descriptions
Accessing the NZCV:
C5.2.11 SP_EL0, Stack Pointer (EL0)
Field descriptions
Accessing the SP_EL0:
C5.2.12 SP_EL1, Stack Pointer (EL1)
Field descriptions
Accessing the SP_EL1:
C5.2.13 SP_EL2, Stack Pointer (EL2)
Field descriptions
Accessing the SP_EL2:
C5.2.14 SP_EL3, Stack Pointer (EL3)
Field descriptions
C5.2.15 SPSel, Stack Pointer Select
Field descriptions
Accessing the SPSel:
C5.2.16 SPSR_abt, Saved Program Status Register (Abort mode)
Field descriptions
Accessing the SPSR_abt:
C5.2.17 SPSR_EL1, Saved Program Status Register (EL1)
Field descriptions
Accessing the SPSR_EL1:
C5.2.18 SPSR_EL2, Saved Program Status Register (EL2)
Field descriptions
Accessing the SPSR_EL2:
C5.2.19 SPSR_EL3, Saved Program Status Register (EL3)
Field descriptions
Accessing the SPSR_EL3:
C5.2.20 SPSR_fiq, Saved Program Status Register (FIQ mode)
Field descriptions
Accessing the SPSR_fiq:
C5.2.21 SPSR_irq, Saved Program Status Register (IRQ mode)
Field descriptions
Accessing the SPSR_irq:
C5.2.22 SPSR_und, Saved Program Status Register (Undefined mode)
Field descriptions
Accessing the SPSR_und:
C5.3 A64 system instructions for cache maintenance
C5.3.1 DC CISW, Data or unified Cache line Clean and Invalidate by Set/Way
Field descriptions
Performing the DC CISW operation:
C5.3.2 DC CIVAC, Data or unified Cache line Clean and Invalidate by VA to PoC
Field descriptions
Performing the DC CIVAC operation:
C5.3.3 DC CSW, Data or unified Cache line Clean by Set/Way
Field descriptions
Performing the DC CSW operation:
C5.3.4 DC CVAC, Data or unified Cache line Clean by VA to PoC
Field descriptions
Performing the DC CVAC operation:
C5.3.5 DC CVAU, Data or unified Cache line Clean by VA to PoU
Field descriptions
Performing the DC CVAU operation:
C5.3.6 DC ISW, Data or unified Cache line Invalidate by Set/Way
Field descriptions
Performing the DC ISW operation:
C5.3.7 DC IVAC, Data or unified Cache line Invalidate by VA to PoC
Field descriptions
Performing the DC IVAC operation:
C5.3.8 DC ZVA, Data Cache Zero by VA
Field descriptions
Performing the DC ZVA operation:
C5.3.9 IC IALLU, Instruction Cache Invalidate All to PoU
Field descriptions
Performing the IC IALLU operation:
C5.3.10 IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
Field descriptions
Performing the IC IALLUIS operation:
C5.3.11 IC IVAU, Instruction Cache line Invalidate by VA to PoU
Field descriptions
Performing the IC IVAU operation:
C5.4 A64 system instructions for address translation
C5.4.1 AT S12E0R, Address Translate Stages 1 and 2 EL0 Read
Field descriptions
Performing the AT S12E0R operation:
C5.4.2 AT S12E0W, Address Translate Stages 1 and 2 EL0 Write
Field descriptions
Performing the AT S12E0W operation:
C5.4.3 AT S12E1R, Address Translate Stages 1 and 2 EL1 Read
Field descriptions
Performing the AT S12E1R operation:
C5.4.4 AT S12E1W, Address Translate Stages 1 and 2 EL1 Write
Field descriptions
Performing the AT S12E1W operation:
C5.4.5 AT S1E0R, Address Translate Stage 1 EL0 Read
Field descriptions
Performing the AT S1E0R operation:
C5.4.6 AT S1E0W, Address Translate Stage 1 EL0 Write
Field descriptions
Performing the AT S1E0W operation:
C5.4.7 AT S1E1R, Address Translate Stage 1 EL1 Read
Field descriptions
Performing the AT S1E1R operation:
C5.4.8 AT S1E1W, Address Translate Stage 1 EL1 Write
Field descriptions
Performing the AT S1E1W operation:
C5.4.9 AT S1E2R, Address Translate Stage 1 EL2 Read
Field descriptions
Performing the AT S1E2R operation:
C5.4.10 AT S1E2W, Address Translate Stage 1 EL2 Write
Field descriptions
Performing the AT S1E2W operation:
C5.4.11 AT S1E3R, Address Translate Stage 1 EL3 Read
Field descriptions
Performing the AT S1E3R operation:
C5.4.12 AT S1E3W, Address Translate Stage 1 EL3 Write
Field descriptions
Performing the AT S1E3W operation:
C5.5 A64 system instructions for TLB maintenance
C5.5.1 TLBI ALLE1, TLB Invalidate All, EL1
Field descriptions
Performing the TLBI ALLE1 operation:
C5.5.2 TLBI ALLE1IS, TLB Invalidate All, EL1, Inner Shareable
Field descriptions
Performing the TLBI ALLE1IS operation:
C5.5.3 TLBI ALLE2, TLB Invalidate All, EL2
Field descriptions
Performing the TLBI ALLE2 operation:
C5.5.4 TLBI ALLE2IS, TLB Invalidate All, EL2, Inner Shareable
Field descriptions
Performing the TLBI ALLE2IS operation:
C5.5.5 TLBI ALLE3, TLB Invalidate All, EL3
Field descriptions
Performing the TLBI ALLE3 operation:
C5.5.6 TLBI ALLE3IS, TLB Invalidate All, EL3, Inner Shareable
Field descriptions
Performing the TLBI ALLE3IS operation:
C5.5.7 TLBI ASIDE1, TLB Invalidate by ASID, EL1
Field descriptions
Performing the TLBI ASIDE1 operation:
C5.5.8 TLBI ASIDE1IS, TLB Invalidate by ASID, EL1, Inner Shareable
Field descriptions
Performing the TLBI ASIDE1IS operation:
C5.5.9 TLBI IPAS2E1, TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
Field descriptions
Performing the TLBI IPAS2E1 operation:
C5.5.10 TLBI IPAS2E1IS, TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
Field descriptions
Performing the TLBI IPAS2E1IS operation:
C5.5.11 TLBI IPAS2LE1, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
Field descriptions
Performing the TLBI IPAS2LE1 operation:
C5.5.12 TLBI IPAS2LE1IS, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
Field descriptions
Performing the TLBI IPAS2LE1IS operation:
C5.5.13 TLBI VAAE1, TLB Invalidate by VA, All ASID, EL1
Field descriptions
Performing the TLBI VAAE1 operation:
C5.5.14 TLBI VAAE1IS, TLB Invalidate by VA, All ASID, EL1, Inner Shareable
Field descriptions
Performing the TLBI VAAE1IS operation:
C5.5.15 TLBI VAALE1, TLB Invalidate by VA, All ASID, Last level, EL1
Field descriptions
Performing the TLBI VAALE1 operation:
C5.5.16 TLBI VAALE1IS, TLB Invalidate by VA, All ASID, EL1, Inner Shareable
Field descriptions
Performing the TLBI VAALE1IS operation:
C5.5.17 TLBI VAE1, TLB Invalidate by VA, EL1
Field descriptions
Performing the TLBI VAE1 operation:
C5.5.18 TLBI VAE1IS, TLB Invalidate by VA, EL1, Inner Shareable
Field descriptions
Performing the TLBI VAE1IS operation:
C5.5.19 TLBI VAE2, TLB Invalidate by VA, EL2
Field descriptions
Performing the TLBI VAE2 operation:
C5.5.20 TLBI VAE2IS, TLB Invalidate by VA, EL2, Inner Shareable
Field descriptions
Performing the TLBI VAE2IS operation:
C5.5.21 TLBI VAE3, TLB Invalidate by VA, EL3
Field descriptions
Performing the TLBI VAE3 operation:
C5.5.22 TLBI VAE3IS, TLB Invalidate by VA, EL3, Inner Shareable
Field descriptions
Performing the TLBI VAE3IS operation:
C5.5.23 TLBI VALE1, TLB Invalidate by VA, Last level, EL1
Field descriptions
Performing the TLBI VALE1 operation:
C5.5.24 TLBI VALE1IS, TLB Invalidate by VA, Last level, EL1, Inner Shareable
Field descriptions
Performing the TLBI VALE1IS operation:
C5.5.25 TLBI VALE2, TLB Invalidate by VA, Last level, EL2
Field descriptions
Performing the TLBI VALE2 operation:
C5.5.26 TLBI VALE2IS, TLB Invalidate by VA, Last level, EL2, Inner Shareable
Field descriptions
Performing the TLBI VALE2IS operation:
C5.5.27 TLBI VALE3, TLB Invalidate by VA, Last level, EL3
Field descriptions
Performing the TLBI VALE3 operation:
C5.5.28 TLBI VALE3IS, TLB Invalidate by VA, Last level, EL3, Inner Shareable
Field descriptions
Performing the TLBI VALE3IS operation:
C5.5.29 TLBI VMALLE1, TLB Invalidate by VMID, All at stage 1, EL1
Field descriptions
Performing the TLBI VMALLE1 operation:
C5.5.30 TLBI VMALLE1IS, TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable
Field descriptions
Performing the TLBI VMALLE1IS operation:
C5.5.31 TLBI VMALLS12E1, TLB Invalidate by VMID, All at Stage 1 and 2, EL1
Field descriptions
Performing the TLBI VMALLS12E1 operation:
C5.5.32 TLBI VMALLS12E1IS, TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable
Field descriptions
Performing the TLBI VMALLS12E1IS operation:
C6: A64 Base Instruction Descriptions
C6.1 Introduction
C6.2 Register size
C6.3 Use of the PC
C6.4 Use of the stack pointer
C6.5 Condition flags and related instructions
C6.6 Alphabetical list of instructions
C6.6.1 ADC
Assembler symbols
Operation
C6.6.2 ADCS
Assembler symbols
Operation
C6.6.3 ADD (extended register)
Assembler symbols
Operation
C6.6.4 ADD (immediate)
Alias conditions
Assembler symbols
Operation
C6.6.5 ADD (shifted register)
Assembler symbols
Operation
C6.6.6 ADDS (extended register)
Alias conditions
Assembler symbols
Operation
C6.6.7 ADDS (immediate)
Alias conditions
Assembler symbols
Operation
C6.6.8 ADDS (shifted register)
Alias conditions
Assembler symbols
Operation
C6.6.9 ADR
Assembler symbols
Operation
C6.6.10 ADRP
Assembler symbols
Operation
C6.6.11 AND (immediate)
Assembler symbols
Operation
C6.6.12 AND (shifted register)
Assembler symbols
Operation
C6.6.13 ANDS (immediate)
Alias conditions
Assembler symbols
Operation
C6.6.14 ANDS (shifted register)
Alias conditions
Assembler symbols
Operation
C6.6.15 ASR (register)
Assembler symbols
Operation
C6.6.16 ASR (immediate)
Assembler symbols
Operation
C6.6.17 ASRV
Assembler symbols
Operation
C6.6.18 AT
Assembler symbols
Operation
C6.6.19 B.cond
Assembler symbols
Operation
C6.6.20 B
Assembler symbols
Operation
C6.6.21 BFI
Assembler symbols
Operation
C6.6.22 BFM
Alias conditions
Assembler symbols
Operation
C6.6.23 BFXIL
Assembler symbols
Operation
C6.6.24 BIC (shifted register)
Assembler symbols
Operation
C6.6.25 BICS (shifted register)
Assembler symbols
Operation
C6.6.26 BL
Assembler symbols
Operation
C6.6.27 BLR
Assembler symbols
Operation
C6.6.28 BR
Assembler symbols
Operation
C6.6.29 BRK
Assembler symbols
Operation
C6.6.30 CBNZ
Assembler symbols
Operation
C6.6.31 CBZ
Assembler symbols
Operation
C6.6.32 CCMN (immediate)
Assembler symbols
Operation
C6.6.33 CCMN (register)
Assembler symbols
Operation
C6.6.34 CCMP (immediate)
Assembler symbols
Operation
C6.6.35 CCMP (register)
Assembler symbols
Operation
C6.6.36 CINC
Assembler symbols
Operation
C6.6.37 CINV
Assembler symbols
Operation
C6.6.38 CLREX
Assembler symbols
Operation
C6.6.39 CLS
Assembler symbols
Operation
C6.6.40 CLZ
Assembler symbols
Operation
C6.6.41 CMN (extended register)
Assembler symbols
Operation
C6.6.42 CMN (immediate)
Assembler symbols
Operation
C6.6.43 CMN (shifted register)
Assembler symbols
Operation
C6.6.44 CMP (extended register)
Assembler symbols
Operation
C6.6.45 CMP (immediate)
Assembler symbols
Operation
C6.6.46 CMP (shifted register)
Assembler symbols
Operation
C6.6.47 CNEG
Assembler symbols
Operation
C6.6.48 CRC32B, CRC32H, CRC32W, CRC32X
Assembler symbols
Operation
C6.6.49 CRC32CB, CRC32CH, CRC32CW, CRC32CX
Assembler symbols
Operation
C6.6.50 CSEL
Assembler symbols
Operation
C6.6.51 CSET
Assembler symbols
Operation
C6.6.52 CSETM
Assembler symbols
Operation
C6.6.53 CSINC
Alias conditions
Assembler symbols
Operation
C6.6.54 CSINV
Alias conditions
Assembler symbols
Operation
C6.6.55 CSNEG
Alias conditions
Assembler symbols
Operation
C6.6.56 DC
Assembler symbols
Operation
C6.6.57 DCPS1
Assembler symbols
Operation
C6.6.58 DCPS2
Assembler symbols
Operation
C6.6.59 DCPS3
Assembler symbols
Operation
C6.6.60 DMB
Assembler symbols
Operation
C6.6.61 DRPS
Operation
C6.6.62 DSB
Assembler symbols
Operation
C6.6.63 EON (shifted register)
Assembler symbols
Operation
C6.6.64 EOR (immediate)
Assembler symbols
Operation
C6.6.65 EOR (shifted register)
Assembler symbols
Operation
C6.6.66 ERET
Operation
C6.6.67 EXTR
Alias conditions
Assembler symbols
Operation
C6.6.68 HINT
Assembler symbols
C6.6.69 HLT
Assembler symbols
Operation
C6.6.70 HVC
Assembler symbols
Operation
C6.6.71 IC
Assembler symbols
Operation
C6.6.72 ISB
Assembler symbols
Operation
C6.6.73 LDAR
Assembler symbols
Operation
C6.6.74 LDARB
Assembler symbols
Operation
C6.6.75 LDARH
Assembler symbols
Operation
C6.6.76 LDAXP
Notes for all encodings
Assembler symbols
Operation
C6.6.77 LDAXR
Assembler symbols
Operation
C6.6.78 LDAXRB
Assembler symbols
Operation
C6.6.79 LDAXRH
Assembler symbols
Operation
C6.6.80 LDNP
Assembler symbols
Shared decode for all encodings
Operation
C6.6.81 LDP
Post-index
Pre-index
Signed offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.82 LDPSW
Post-index
Pre-index
Signed offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.83 LDR (immediate)
Post-index
Pre-index
Unsigned offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.84 LDR (literal)
Assembler symbols
Operation
C6.6.85 LDR (register)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.86 LDRB (immediate)
Post-index
Pre-index
Unsigned offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.87 LDRB (register)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.88 LDRH (immediate)
Post-index
Pre-index
Unsigned offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.89 LDRH (register)
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation
C6.6.90 LDRSB (immediate)
Post-index
Pre-index
Unsigned offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.91 LDRSB (register)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.92 LDRSH (immediate)
Post-index
Pre-index
Unsigned offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.93 LDRSH (register)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.94 LDRSW (immediate)
Post-index
Pre-index
Unsigned offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.95 LDRSW (literal)
Assembler symbols
Operation
C6.6.96 LDRSW (register)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.97 LDTR
Assembler symbols
Shared decode for all encodings
Operation
C6.6.98 LDTRB
Assembler symbols
Shared decode for all encodings
Operation
C6.6.99 LDTRH
Assembler symbols
Shared decode for all encodings
Operation
C6.6.100 LDTRSB
Assembler symbols
Shared decode for all encodings
Operation
C6.6.101 LDTRSH
Assembler symbols
Shared decode for all encodings
Operation
C6.6.102 LDTRSW
Assembler symbols
Shared decode for all encodings
Operation
C6.6.103 LDUR
Assembler symbols
Shared decode for all encodings
Operation
C6.6.104 LDURB
Assembler symbols
Shared decode for all encodings
Operation
C6.6.105 LDURH
Assembler symbols
Shared decode for all encodings
Operation
C6.6.106 LDURSB
Assembler symbols
Shared decode for all encodings
Operation
C6.6.107 LDURSH
Assembler symbols
Shared decode for all encodings
Operation
C6.6.108 LDURSW
Assembler symbols
Shared decode for all encodings
Operation
C6.6.109 LDXP
Notes for all encodings
Assembler symbols
Operation
C6.6.110 LDXR
Assembler symbols
Operation
C6.6.111 LDXRB
Assembler symbols
Operation
C6.6.112 LDXRH
Assembler symbols
Operation
C6.6.113 LSL (register)
Assembler symbols
Operation
C6.6.114 LSL (immediate)
Assembler symbols
Operation
C6.6.115 LSLV
Assembler symbols
Operation
C6.6.116 LSR (register)
Assembler symbols
Operation
C6.6.117 LSR (immediate)
Assembler symbols
Operation
C6.6.118 LSRV
Assembler symbols
Operation
C6.6.119 MADD
Alias conditions
Assembler symbols
Operation
C6.6.120 MNEG
Assembler symbols
Operation
C6.6.121 MOV (to/from SP)
Assembler symbols
Operation
C6.6.122 MOV (inverted wide immediate)
Assembler symbols
Operation
C6.6.123 MOV (wide immediate)
Assembler symbols
Operation
C6.6.124 MOV (bitmask immediate)
Assembler symbols
Operation
C6.6.125 MOV (register)
Assembler symbols
Operation
C6.6.126 MOVK
Assembler symbols
Operation
C6.6.127 MOVN
Alias conditions
Assembler symbols
Operation
C6.6.128 MOVZ
Alias conditions
Assembler symbols
Operation
C6.6.129 MRS
Assembler symbols
Operation
C6.6.130 MSR (immediate)
Assembler symbols
Operation
C6.6.131 MSR (register)
Assembler symbols
Operation
C6.6.132 MSUB
Alias conditions
Assembler symbols
Operation
C6.6.133 MUL
Assembler symbols
Operation
C6.6.134 MVN
Assembler symbols
Operation
C6.6.135 NEG (shifted register)
Assembler symbols
Operation
C6.6.136 NEGS
Assembler symbols
Operation
C6.6.137 NGC
Assembler symbols
Operation
C6.6.138 NGCS
Assembler symbols
Operation
C6.6.139 NOP
Operation
C6.6.140 ORN (shifted register)
Alias conditions
Assembler symbols
Operation
C6.6.141 ORR (immediate)
Alias conditions
Assembler symbols
Operation
C6.6.142 ORR (shifted register)
Alias conditions
Assembler symbols
Operation
C6.6.143 PRFM (immediate)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.144 PRFM (literal)
Assembler symbols
Operation
C6.6.145 PRFM (register)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.146 PRFM (unscaled offset)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.147 RBIT
Assembler symbols
Operation
C6.6.148 RET
Assembler symbols
Operation
C6.6.149 REV
Assembler symbols
Operation
C6.6.150 REV16
Assembler symbols
Operation
C6.6.151 REV32
Assembler symbols
Operation
C6.6.152 REV64
Assembler symbols
Operation
C6.6.153 ROR (immediate)
Assembler symbols
Operation
C6.6.154 ROR (register)
Assembler symbols
Operation
C6.6.155 RORV
Assembler symbols
Operation
C6.6.156 SBC
Alias conditions
Assembler symbols
Operation
C6.6.157 SBCS
Alias conditions
Assembler symbols
Operation
C6.6.158 SBFIZ
Assembler symbols
Operation
C6.6.159 SBFM
Alias conditions
Assembler symbols
Operation
C6.6.160 SBFX
Assembler symbols
Operation
C6.6.161 SDIV
Assembler symbols
Operation
C6.6.162 SEV
Operation
C6.6.163 SEVL
Operation
C6.6.164 SMADDL
Alias conditions
Assembler symbols
Operation
C6.6.165 SMC
Assembler symbols
Operation
C6.6.166 SMNEGL
Assembler symbols
Operation
C6.6.167 SMSUBL
Alias conditions
Assembler symbols
Operation
C6.6.168 SMULH
Assembler symbols
Operation
C6.6.169 SMULL
Assembler symbols
Operation
C6.6.170 STLR
Assembler symbols
Operation
C6.6.171 STLRB
Assembler symbols
Operation
C6.6.172 STLRH
Assembler symbols
Operation
C6.6.173 STLXP
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation
C6.6.174 STLXR
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation
C6.6.175 STLXRB
Notes for all encodings
Assembler symbols
Aborts
Operation
C6.6.176 STLXRH
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation
C6.6.177 STNP
Assembler symbols
Shared decode for all encodings
Operation
C6.6.178 STP
Post-index
Pre-index
Signed offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.179 STR (immediate)
Post-index
Pre-index
Unsigned offset
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.180 STR (register)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.181 STRB (immediate)
Post-index
Pre-index
Unsigned offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.182 STRB (register)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.183 STRH (immediate)
Post-index
Pre-index
Unsigned offset
Notes for all encodings
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C6.6.184 STRH (register)
Assembler symbols
Shared decode for all encodings
Operation
C6.6.185 STTR
Assembler symbols
Shared decode for all encodings
Operation
C6.6.186 STTRB
Assembler symbols
Shared decode for all encodings
Operation
C6.6.187 STTRH
Assembler symbols
Shared decode for all encodings
Operation
C6.6.188 STUR
Assembler symbols
Shared decode for all encodings
Operation
C6.6.189 STURB
Assembler symbols
Shared decode for all encodings
Operation
C6.6.190 STURH
Assembler symbols
Shared decode for all encodings
Operation
C6.6.191 STXP
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation
C6.6.192 STXR
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation
C6.6.193 STXRB
Notes for all encodings
Assembler symbols
Aborts
Operation
C6.6.194 STXRH
Assembler symbols
Aborts and alignment
Operation
C6.6.195 SUB (extended register)
Assembler symbols
Operation
C6.6.196 SUB (immediate)
Assembler symbols
Operation
C6.6.197 SUB (shifted register)
Alias conditions
Assembler symbols
Operation
C6.6.198 SUBS (extended register)
Alias conditions
Assembler symbols
Operation
C6.6.199 SUBS (immediate)
Alias conditions
Assembler symbols
Operation
C6.6.200 SUBS (shifted register)
Alias conditions
Assembler symbols
Operation
C6.6.201 SVC
Assembler symbols
Operation
C6.6.202 SXTB
Assembler symbols
Operation
C6.6.203 SXTH
Assembler symbols
Operation
C6.6.204 SXTW
Assembler symbols
Operation
C6.6.205 SYS
Alias conditions
Assembler symbols
Operation
C6.6.206 SYSL
Assembler symbols
Operation
C6.6.207 TBNZ
Assembler symbols
Operation
C6.6.208 TBZ
Assembler symbols
Operation
C6.6.209 TLBI
Assembler symbols
Operation
C6.6.210 TST (immediate)
Assembler symbols
Operation
C6.6.211 TST (shifted register)
Assembler symbols
Operation
C6.6.212 UBFIZ
Assembler symbols
Operation
C6.6.213 UBFM
Alias conditions
Assembler symbols
Operation
C6.6.214 UBFX
Assembler symbols
Operation
C6.6.215 UDIV
Assembler symbols
Operation
C6.6.216 UMADDL
Alias conditions
Assembler symbols
Operation
C6.6.217 UMNEGL
Assembler symbols
Operation
C6.6.218 UMSUBL
Alias conditions
Assembler symbols
Operation
C6.6.219 UMULH
Assembler symbols
Operation
C6.6.220 UMULL
Assembler symbols
Operation
C6.6.221 UXTB
Assembler symbols
Operation
C6.6.222 UXTH
Assembler symbols
Operation
C6.6.223 WFE
Operation
C6.6.224 WFI
Operation
C6.6.225 YIELD
Operation
C7: A64 Advanced SIMD and Floating-point Instruction Descriptions
C7.1 Introduction
C7.2 About the SIMD and floating-point instructions
C7.2.1 Register size
C7.2.2 Data types
C7.2.3 Condition flags and related instructions
C7.2.4 General capabilities
C7.3 Alphabetical list of floating-point and Advanced SIMD instructions
C7.3.1 ABS
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.2 ADD (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.3 ADDHN, ADDHN2
Assembler symbols
Operation
C7.3.4 ADDP (scalar)
Assembler symbols
Operation
C7.3.5 ADDP (vector)
Assembler symbols
Operation
C7.3.6 ADDV
Assembler symbols
Operation
C7.3.7 AESD
Assembler symbols
Operation
C7.3.8 AESE
Assembler symbols
Operation
C7.3.9 AESIMC
Assembler symbols
Operation
C7.3.10 AESMC
Assembler symbols
Operation
C7.3.11 AND (vector)
Assembler symbols
Operation
C7.3.12 BIC (vector, immediate)
Assembler symbols
Operation
C7.3.13 BIC (vector, register)
Assembler symbols
Operation
C7.3.14 BIF
Assembler symbols
Operation
C7.3.15 BIT
Assembler symbols
Operation
C7.3.16 BSL
Assembler symbols
Operation
C7.3.17 CLS (vector)
Assembler symbols
Operation
C7.3.18 CLZ (vector)
Assembler symbols
Operation
C7.3.19 CMEQ (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.20 CMEQ (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.21 CMGE (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.22 CMGE (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.23 CMGT (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.24 CMGT (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.25 CMHI (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.26 CMHS (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.27 CMLE (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.28 CMLT (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.29 CMTST
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.30 CNT
Assembler symbols
Operation
C7.3.31 DUP (element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.32 DUP (general)
Assembler symbols
Operation
C7.3.33 EOR (vector)
Assembler symbols
Operation
C7.3.34 EXT
Assembler symbols
Operation
C7.3.35 FABD
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.36 FABS (vector)
Assembler symbols
Operation
C7.3.37 FABS (scalar)
Assembler symbols
Operation
C7.3.38 FACGE
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.39 FACGT
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.40 FADD (vector)
Assembler symbols
Operation
C7.3.41 FADD (scalar)
Assembler symbols
Operation
C7.3.42 FADDP (scalar)
Assembler symbols
Operation
C7.3.43 FADDP (vector)
Assembler symbols
Operation
C7.3.44 FCCMP
Assembler symbols
Operation
C7.3.45 FCCMPE
Assembler symbols
Operation
C7.3.46 FCMEQ (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.47 FCMEQ (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.48 FCMGE (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.49 FCMGE (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.50 FCMGT (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.51 FCMGT (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.52 FCMLE (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.53 FCMLT (zero)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.54 FCMP
Assembler symbols
Operation
C7.3.55 FCMPE
Assembler symbols
Operation
C7.3.56 FCSEL
Assembler symbols
Operation
C7.3.57 FCVT
Assembler symbols
Operation
C7.3.58 FCVTAS (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.59 FCVTAS (scalar)
Assembler symbols
Operation
C7.3.60 FCVTAU (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.61 FCVTAU (scalar)
Assembler symbols
Operation
C7.3.62 FCVTL, FCVTL2
Assembler symbols
Operation
C7.3.63 FCVTMS (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.64 FCVTMS (scalar)
Assembler symbols
Operation
C7.3.65 FCVTMU (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.66 FCVTMU (scalar)
Assembler symbols
Operation
C7.3.67 FCVTN, FCVTN2
Assembler symbols
Operation
C7.3.68 FCVTNS (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.69 FCVTNS (scalar)
Assembler symbols
Operation
C7.3.70 FCVTNU (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.71 FCVTNU (scalar)
Assembler symbols
Operation
C7.3.72 FCVTPS (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.73 FCVTPS (scalar)
Assembler symbols
Operation
C7.3.74 FCVTPU (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.75 FCVTPU (scalar)
Assembler symbols
Operation
C7.3.76 FCVTXN, FCVTXN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.77 FCVTZS (vector, fixed-point)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.78 FCVTZS (vector, integer)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.79 FCVTZS (scalar, fixed-point)
Assembler symbols
Operation
C7.3.80 FCVTZS (scalar, integer)
Assembler symbols
Operation
C7.3.81 FCVTZU (vector, fixed-point)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.82 FCVTZU (vector, integer)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.83 FCVTZU (scalar, fixed-point)
Assembler symbols
Operation
C7.3.84 FCVTZU (scalar, integer)
Assembler symbols
Operation
C7.3.85 FDIV (vector)
Assembler symbols
Operation
C7.3.86 FDIV (scalar)
Assembler symbols
Operation
C7.3.87 FMADD
Assembler symbols
Operation
C7.3.88 FMAX (vector)
Assembler symbols
Operation
C7.3.89 FMAX (scalar)
Assembler symbols
Operation
C7.3.90 FMAXNM (vector)
Assembler symbols
Operation
C7.3.91 FMAXNM (scalar)
Assembler symbols
Operation
C7.3.92 FMAXNMP (scalar)
Assembler symbols
Operation
C7.3.93 FMAXNMP (vector)
Assembler symbols
Operation
C7.3.94 FMAXNMV
Assembler symbols
Operation
C7.3.95 FMAXP (scalar)
Assembler symbols
Operation
C7.3.96 FMAXP (vector)
Assembler symbols
Operation
C7.3.97 FMAXV
Assembler symbols
Operation
C7.3.98 FMIN (vector)
Assembler symbols
Operation
C7.3.99 FMIN (scalar)
Assembler symbols
Operation
C7.3.100 FMINNM (vector)
Assembler symbols
Operation
C7.3.101 FMINNM (scalar)
Assembler symbols
Operation
C7.3.102 FMINNMP (scalar)
Assembler symbols
Operation
C7.3.103 FMINNMP (vector)
Assembler symbols
Operation
C7.3.104 FMINNMV
Assembler symbols
Operation
C7.3.105 FMINP (scalar)
Assembler symbols
Operation
C7.3.106 FMINP (vector)
Assembler symbols
Operation
C7.3.107 FMINV
Assembler symbols
Operation
C7.3.108 FMLA (by element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.109 FMLA (vector)
Assembler symbols
Operation
C7.3.110 FMLS (by element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.111 FMLS (vector)
Assembler symbols
Operation
C7.3.112 FMOV (vector, immediate)
Assembler symbols
Operation
C7.3.113 FMOV (register)
Assembler symbols
Operation
C7.3.114 FMOV (general)
Assembler symbols
Operation
C7.3.115 FMOV (scalar, immediate)
Assembler symbols
Operation
C7.3.116 FMSUB
Assembler symbols
Operation
C7.3.117 FMUL (by element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.118 FMUL (vector)
Assembler symbols
Operation
C7.3.119 FMUL (scalar)
Assembler symbols
Operation
C7.3.120 FMULX (by element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.121 FMULX
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.122 FNEG (vector)
Assembler symbols
Operation
C7.3.123 FNEG (scalar)
Assembler symbols
Operation
C7.3.124 FNMADD
Assembler symbols
Operation
C7.3.125 FNMSUB
Assembler symbols
Operation
C7.3.126 FNMUL
Assembler symbols
Operation
C7.3.127 FRECPE
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.128 FRECPS
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.129 FRECPX
Assembler symbols
Operation
C7.3.130 FRINTA (vector)
Assembler symbols
Operation
C7.3.131 FRINTA (scalar)
Assembler symbols
Operation
C7.3.132 FRINTI (vector)
Assembler symbols
Operation
C7.3.133 FRINTI (scalar)
Assembler symbols
Operation
C7.3.134 FRINTM (vector)
Assembler symbols
Operation
C7.3.135 FRINTM (scalar)
Assembler symbols
Operation
C7.3.136 FRINTN (vector)
Assembler symbols
Operation
C7.3.137 FRINTN (scalar)
Assembler symbols
Operation
C7.3.138 FRINTP (vector)
Assembler symbols
Operation
C7.3.139 FRINTP (scalar)
Assembler symbols
Operation
C7.3.140 FRINTX (vector)
Assembler symbols
Operation
C7.3.141 FRINTX (scalar)
Assembler symbols
Operation
C7.3.142 FRINTZ (vector)
Assembler symbols
Operation
C7.3.143 FRINTZ (scalar)
Assembler symbols
Operation
C7.3.144 FRSQRTE
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.145 FRSQRTS
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.146 FSQRT (vector)
Assembler symbols
Operation
C7.3.147 FSQRT (scalar)
Assembler symbols
Operation
C7.3.148 FSUB (vector)
Assembler symbols
Operation
C7.3.149 FSUB (scalar)
Assembler symbols
Operation
C7.3.150 INS (element)
Assembler symbols
Operation
C7.3.151 INS (general)
Assembler symbols
Operation
C7.3.152 LD1 (multiple structures)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.153 LD1 (single structure)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.154 LD1R
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.155 LD2 (multiple structures)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.156 LD2 (single structure)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.157 LD2R
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.158 LD3 (multiple structures)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.159 LD3 (single structure)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.160 LD3R
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.161 LD4 (multiple structures)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.162 LD4 (single structure)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.163 LD4R
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.164 LDNP (SIMD&FP)
Assembler symbols
Shared decode for all encodings
Operation
C7.3.165 LDP (SIMD&FP)
Post-index
Pre-index
Signed offset
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.166 LDR (immediate, SIMD&FP)
Post-index
Pre-index
Unsigned offset
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.167 LDR (literal, SIMD&FP)
Assembler symbols
Operation
C7.3.168 LDR (register, SIMD&FP)
Assembler symbols
Shared decode for all encodings
Operation
C7.3.169 LDUR (SIMD&FP)
Assembler symbols
Shared decode for all encodings
Operation
C7.3.170 MLA (by element)
Assembler symbols
Operation
C7.3.171 MLA (vector)
Assembler symbols
Operation
C7.3.172 MLS (by element)
Assembler symbols
Operation
C7.3.173 MLS (vector)
Assembler symbols
Operation
C7.3.174 MOV (scalar)
Assembler symbols
Operation
C7.3.175 MOV (element)
Assembler symbols
Operation
C7.3.176 MOV (from general)
Assembler symbols
Operation
C7.3.177 MOV (vector)
Assembler symbols
Operation
C7.3.178 MOV (to general)
Assembler symbols
Operation
C7.3.179 MOVI
Assembler symbols
Operation
C7.3.180 MUL (by element)
Assembler symbols
Operation
C7.3.181 MUL (vector)
Assembler symbols
Operation
C7.3.182 MVN
Assembler symbols
Operation
C7.3.183 MVNI
Assembler symbols
Operation
C7.3.184 NEG (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.185 NOT
Assembler symbols
Operation
C7.3.186 ORN (vector)
Assembler symbols
Operation
C7.3.187 ORR (vector, immediate)
Assembler symbols
Operation
C7.3.188 ORR (vector, register)
Alias conditions
Assembler symbols
Operation
C7.3.189 PMUL
Assembler symbols
Operation
C7.3.190 PMULL, PMULL2
Assembler symbols
Operation
C7.3.191 RADDHN, RADDHN2
Assembler symbols
Operation
C7.3.192 RBIT (vector)
Assembler symbols
Operation
C7.3.193 REV16 (vector)
Assembler symbols
Operation
C7.3.194 REV32 (vector)
Assembler symbols
Operation
C7.3.195 REV64
Assembler symbols
Operation
C7.3.196 RSHRN, RSHRN2
Assembler symbols
Operation
C7.3.197 RSUBHN, RSUBHN2
Assembler symbols
Operation
C7.3.198 SABA
Assembler symbols
Operation
C7.3.199 SABAL, SABAL2
Assembler symbols
Operation
C7.3.200 SABD
Assembler symbols
Operation
C7.3.201 SABDL, SABDL2
Assembler symbols
Operation
C7.3.202 SADALP
Assembler symbols
Operation
C7.3.203 SADDL, SADDL2
Assembler symbols
Operation
C7.3.204 SADDLP
Assembler symbols
Operation
C7.3.205 SADDLV
Assembler symbols
Operation
C7.3.206 SADDW, SADDW2
Assembler symbols
Operation
C7.3.207 SCVTF (vector, fixed-point)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.208 SCVTF (vector, integer)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.209 SCVTF (scalar, fixed-point)
Assembler symbols
Operation
C7.3.210 SCVTF (scalar, integer)
Assembler symbols
Operation
C7.3.211 SHA1C
Assembler symbols
Operation
C7.3.212 SHA1H
Assembler symbols
Operation
C7.3.213 SHA1M
Assembler symbols
Operation
C7.3.214 SHA1P
Assembler symbols
Operation
C7.3.215 SHA1SU0
Assembler symbols
Operation
C7.3.216 SHA1SU1
Assembler symbols
Operation
C7.3.217 SHA256H2
Assembler symbols
Operation
C7.3.218 SHA256H
Assembler symbols
Operation
C7.3.219 SHA256SU0
Assembler symbols
Operation
C7.3.220 SHA256SU1
Assembler symbols
Operation
C7.3.221 SHADD
Assembler symbols
Operation
C7.3.222 SHL
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.223 SHLL, SHLL2
Assembler symbols
Operation
C7.3.224 SHRN, SHRN2
Assembler symbols
Operation
C7.3.225 SHSUB
Assembler symbols
Operation
C7.3.226 SLI
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.227 SMAX
Assembler symbols
Operation
C7.3.228 SMAXP
Assembler symbols
Operation
C7.3.229 SMAXV
Assembler symbols
Operation
C7.3.230 SMIN
Assembler symbols
Operation
C7.3.231 SMINP
Assembler symbols
Operation
C7.3.232 SMINV
Assembler symbols
Operation
C7.3.233 SMLAL, SMLAL2 (by element)
Assembler symbols
Operation
C7.3.234 SMLAL, SMLAL2 (vector)
Assembler symbols
Operation
C7.3.235 SMLSL, SMLSL2 (by element)
Assembler symbols
Operation
C7.3.236 SMLSL, SMLSL2 (vector)
Assembler symbols
Operation
C7.3.237 SMOV
Assembler symbols
Operation
C7.3.238 SMULL, SMULL2 (by element)
Assembler symbols
Operation
C7.3.239 SMULL, SMULL2 (vector)
Assembler symbols
Operation
C7.3.240 SQABS
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.241 SQADD
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.242 SQDMLAL, SQDMLAL2 (by element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.243 SQDMLAL, SQDMLAL2 (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.244 SQDMLSL, SQDMLSL2 (by element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.245 SQDMLSL, SQDMLSL2 (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.246 SQDMULH (by element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.247 SQDMULH (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.248 SQDMULL, SQDMULL2 (by element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.249 SQDMULL, SQDMULL2 (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.250 SQNEG
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.251 SQRDMULH (by element)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.252 SQRDMULH (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.253 SQRSHL
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.254 SQRSHRN, SQRSHRN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.255 SQRSHRUN, SQRSHRUN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.256 SQSHL (immediate)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.257 SQSHL (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.258 SQSHLU
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.259 SQSHRN, SQSHRN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.260 SQSHRUN, SQSHRUN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.261 SQSUB
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.262 SQXTN, SQXTN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.263 SQXTUN, SQXTUN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.264 SRHADD
Assembler symbols
Operation
C7.3.265 SRI
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.266 SRSHL
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.267 SRSHR
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.268 SRSRA
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.269 SSHL
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.270 SSHLL, SSHLL2
Alias conditions
Assembler symbols
Operation
C7.3.271 SSHR
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.272 SSRA
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.273 SSUBL, SSUBL2
Assembler symbols
Operation
C7.3.274 SSUBW, SSUBW2
Assembler symbols
Operation
C7.3.275 ST1 (multiple structures)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.276 ST1 (single structure)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.277 ST2 (multiple structures)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.278 ST2 (single structure)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.279 ST3 (multiple structures)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.280 ST3 (single structure)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.281 ST4 (multiple structures)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.282 ST4 (single structure)
No offset
Post-index
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.283 STNP (SIMD&FP)
Assembler symbols
Shared decode for all encodings
Operation
C7.3.284 STP (SIMD&FP)
Post-index
Pre-index
Signed offset
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.285 STR (immediate, SIMD&FP)
Post-index
Pre-index
Unsigned offset
Assembler symbols
Shared decode for all encodings
Operation for all encodings
C7.3.286 STR (register, SIMD&FP)
Assembler symbols
Shared decode for all encodings
Operation
C7.3.287 STUR (SIMD&FP)
Assembler symbols
Shared decode for all encodings
Operation
C7.3.288 SUB (vector)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.289 SUBHN, SUBHN2
Assembler symbols
Operation
C7.3.290 SUQADD
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.291 SXTL, SXTL2
Assembler symbols
Operation
C7.3.292 TBL
Assembler symbols
Operation
C7.3.293 TBX
Assembler symbols
Operation
C7.3.294 TRN1
Assembler symbols
Operation
C7.3.295 TRN2
Assembler symbols
Operation
C7.3.296 UABA
Assembler symbols
Operation
C7.3.297 UABAL, UABAL2
Assembler symbols
Operation
C7.3.298 UABD
Assembler symbols
Operation
C7.3.299 UABDL, UABDL2
Assembler symbols
Operation
C7.3.300 UADALP
Assembler symbols
Operation
C7.3.301 UADDL, UADDL2
Assembler symbols
Operation
C7.3.302 UADDLP
Assembler symbols
Operation
C7.3.303 UADDLV
Assembler symbols
Operation
C7.3.304 UADDW, UADDW2
Assembler symbols
Operation
C7.3.305 UCVTF (vector, fixed-point)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.306 UCVTF (vector, integer)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.307 UCVTF (scalar, fixed-point)
Assembler symbols
Operation
C7.3.308 UCVTF (scalar, integer)
Assembler symbols
Operation
C7.3.309 UHADD
Assembler symbols
Operation
C7.3.310 UHSUB
Assembler symbols
Operation
C7.3.311 UMAX
Assembler symbols
Operation
C7.3.312 UMAXP
Assembler symbols
Operation
C7.3.313 UMAXV
Assembler symbols
Operation
C7.3.314 UMIN
Assembler symbols
Operation
C7.3.315 UMINP
Assembler symbols
Operation
C7.3.316 UMINV
Assembler symbols
Operation
C7.3.317 UMLAL, UMLAL2 (by element)
Assembler symbols
Operation
C7.3.318 UMLAL, UMLAL2 (vector)
Assembler symbols
Operation
C7.3.319 UMLSL, UMLSL2 (by element)
Assembler symbols
Operation
C7.3.320 UMLSL, UMLSL2 (vector)
Assembler symbols
Operation
C7.3.321 UMOV
Alias conditions
Assembler symbols
Operation
C7.3.322 UMULL, UMULL2 (by element)
Assembler symbols
Operation
C7.3.323 UMULL, UMULL2 (vector)
Assembler symbols
Operation
C7.3.324 UQADD
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.325 UQRSHL
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.326 UQRSHRN, UQRSHRN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.327 UQSHL (immediate)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.328 UQSHL (register)
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.329 UQSHRN, UQSHRN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.330 UQSUB
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.331 UQXTN, UQXTN2
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.332 URECPE
Assembler symbols
Operation
C7.3.333 URHADD
Assembler symbols
Operation
C7.3.334 URSHL
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.335 URSHR
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.336 URSQRTE
Assembler symbols
Operation
C7.3.337 URSRA
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.338 USHL
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.339 USHLL, USHLL2
Alias conditions
Assembler symbols
Operation
C7.3.340 USHR
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.341 USQADD
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.342 USRA
Scalar
Vector
Assembler symbols
Operation for all encodings
C7.3.343 USUBL, USUBL2
Assembler symbols
Operation
C7.3.344 USUBW, USUBW2
Assembler symbols
Operation
C7.3.345 UXTL, UXTL2
Assembler symbols
Operation
C7.3.346 UZP1
Assembler symbols
Operation
C7.3.347 UZP2
Assembler symbols
Operation
C7.3.348 XTN, XTN2
Assembler symbols
Operation
C7.3.349 ZIP1
Assembler symbols
Operation
C7.3.350 ZIP2
Assembler symbols
Operation
Part D: The AArch64 System Level Architecture
D1: The AArch64 System Level Programmers’ Model
D1.1 Exception levels
D1.1.1 Typical Exception level usage model
D1.2 Exception terminology
D1.2.1 Terminology for taking an exception
D1.2.2 Terminology for returning from an exception
D1.2.3 Exception levels
D1.2.4 Definition of a precise exception
D1.2.5 Definitions of synchronous and asynchronous exceptions
D1.3 Execution state
D1.4 Security state
D1.4.1 The ARMv8-A security model
Security model when EL3 is using AArch64
D1.5 Virtualization
D1.5.1 The effect of implementing EL2 on the Exception model
Virtual interrupts
D1.6 Registers for instruction processing and exception handling
D1.6.1 The general purpose registers, R0-R30
D1.6.2 The stack pointer registers
Stack pointer register selection
D1.6.3 The SIMD and floating-point registers, V0-V31
D1.6.4 Saved Program Status Registers (SPSRs)
SPSR format for exceptions taken to AArch64 state
Pseudocode description of SPSR operations
D1.6.5 Exception Link Registers (ELRs)
D1.7 Process state, PSTATE
D1.7.1 Accessing PSTATE fields
D1.7.2 The Saved Program Status Registers (SPSRs)
D1.8 Program counter and stack pointer alignment
D1.8.1 PC alignment checking
D1.8.2 Stack pointer alignment checking
D1.9 Reset
D1.9.1 PE state on reset to AArch64 state
D1.9.2 Code sequence to use RMR_ELx.RR to request a Warm reset
D1.9.3 Pseudocode description of reset
D1.10 Exception entry
D1.10.1 Preferred exception return address
D1.10.2 Exception vectors
D1.10.3 Pseudocode description of exception entry to AArch64 state
D1.10.4 Exception classes and the ESR_ELx syndrome registers
Use of the ESR_EL1, ESR_EL2, and ESR_EL3
Reporting the EC encoding when an exception is routed to EL2
D1.10.5 Summary of register updates on faults taken to an Exception level that is using AArch64
Validity of FAR_ELx
Validity of HPFAR_EL2
D1.11 Exception return
D1.11.1 Exception return and PC alignment
D1.11.2 Illegal return events from AArch64 state
D1.11.3 Legal returns that set PSTATE.IL to 1
D1.11.4 The Illegal Execution state exception
D1.11.5 Pseudocode description of exception return
D1.12 The Exception level hierarchy
D1.12.1 The hierarchy of configuration and routing control
Controls provided at EL3
Controls provided at EL2
Controls provided at EL1
D1.12.2 Control of SIMD, floating-point and trace functionality
D1.12.3 Control of IMPLEMENTATION DEFINED features
D1.13 Synchronous exception types, routing and priorities
D1.13.1 Routing exceptions to EL2
D1.13.2 Synchronous exception prioritization for exceptions taken to AArch64
D1.13.3 Effect of Data Aborts
D1.13.4 Floating-point exception traps
Combinations of floating-point exceptions
D1.14 Asynchronous exception types, routing, masking and priorities
D1.14.1 Asynchronous exception routing
D1.14.2 Asynchronous exception masking
D1.14.3 Virtual interrupts
D1.14.4 Prioritization and recognition of asynchronous exceptions
D1.14.5 Taking an interrupt or other exception during a multiple-register load or store
D1.15 Configurable instruction enables and disables, and trap controls
D1.15.1 Register access instructions
D1.15.2 EL1 configurable controls
Traps to EL1 of EL0 execution of cache maintenance instructions
Traps to EL1 of EL0 accesses to the CTR_EL0
Traps to EL1 of EL0 execution of WFE and WFI instructions
Traps to EL1 of EL0 execution of DC ZVA instructions
Traps to EL1 of EL0 accesses to the PSTATE.{D, A, I, F} interrupt masks
Disabling or enabling EL0 use of AArch32 deprecated functionality
Traps to EL1 of EL0 and EL1 System register accesses to the trace registers
Traps to EL1 of EL0 and EL1 accesses to SIMD and floating-point functionality
Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers
Traps to EL1 of EL0 accesses to the Generic Timer registers
Traps to EL1 of EL0 accesses to Performance Monitors registers
D1.15.3 EL2 configurable controls
Traps to EL2 of Non-secure EL1 accesses to virtual memory control registers
Disabling Non-secure state execution of HVC instructions
Traps to EL2 of Non-secure EL0 and EL1 execution of DC ZVA instructions
Traps to EL2 of Non-secure EL1 execution of TLB maintenance instructions
Traps to EL2 of Non-secure EL0 and EL1 execution of cache maintenance instructions
Traps to EL2 of Non-secure EL1 accesses to the Auxiliary Control Register
Traps to EL2 of Non-secure EL0 and EL1 accesses to lockdown, DMA, and TCM operations
Traps to EL2 of Non-secure EL1 execution of SMC instructions
Traps to EL2 of Non-secure EL0 and EL1 accesses to the ID registers
Traps to EL2 of Non-secure EL0 and EL1 execution of WFE and WFI instructions
Trapping to EL2 of Non-secure EL1 accesses to the CPACR_EL1 or CPACR
General trapping to EL2 of Non-secure accesses to the SIMD and floating-point registers
Traps to EL2 of Non-secure System register accesses to the trace registers
General trapping to EL2 of Non-secure EL0 and EL1 accesses to System registers, from AArch32 state only
Traps to EL2 of Non-secure EL0 and EL1 System register accesses to debug registers
Traps to EL2 of Non-secure EL0 and EL1 accesses to the Generic Timer registers
Traps to EL2 of Non-secure EL0 and EL1 accesses to Performance Monitors registers
D1.15.4 EL3 configurable controls
Traps to EL3 of Secure monitor functionality from Secure EL1 using AArch32
Traps to EL3 of EL2, EL1, and EL0 execution of WFE and WFI instructions
Traps to EL3 of Secure EL1 accesses to the Counter-timer Physical Secure timer registers
Enabling EL3, EL2, and Non-secure EL1 execution of HVC instructions
Disabling EL3, EL2, and EL1 execution of SMC instructions
Trapping to EL3 of EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR
Traps to EL3 of all System register accesses to the trace registers
Traps to EL3 of all accesses to the SIMD and floating-point registers
Traps to EL3 of EL2, EL1, and EL0 System register accesses to debug registers
Traps to EL3 of EL2, EL1, and EL0 accesses to Performance Monitors registers
D1.16 System calls
D1.16.1 Pseudocode description of system calls
D1.17 Mechanisms for entering a low-power state
D1.17.1 Wait for Event mechanism and Send event
The Event Register
The Wait For Event instruction
WFE wake-up events in AArch64 state
The Send Event instructions
Pseudocode description of the Wait For Event mechanism
D1.17.2 Wait For Interrupt
WFI wake-up events
Using WFI to indicate an idle state on bus interfaces
Pseudocode description of Wait For Interrupt
D1.18 Self-hosted debug
D1.18.1 Debug exceptions
D1.18.2 The PSTATE debug mask bit, D
D1.19 The Performance Monitors Extension
D1.20 Interprocessing
D1.20.1 Register mappings between AArch32 state and AArch64 state
Mapping of the general-purpose registers between the Execution states
Mapping of the SIMD and floating-point registers between the Execution states
Mapping of the System registers between the Execution states
D1.20.2 State of the general-purpose registers on taking an exception to AArch64 state
D1.20.3 SPSR, ELR, and AArch64 SP relationships on changing Execution state
D1.21 The effect of implementation choices on the programmers’ model
D1.21.1 Implication of Exception levels implemented
D1.21.2 Support for Exception levels and Execution states
D1.21.3 Implementations not including Advanced SIMD and floating-point instructions
D1.21.4 The effects of supporting fewer than four Exception levels
Behavior when EL2 is not implemented
Behavior when EL3 is not implemented and EL2 is implemented
Behavior when only EL1 and EL0 are implemented
D2: AArch64 Self-hosted Debug
D2.1 About debug exceptions
D2.2 The debug exception enable controls
D2.3 Routing debug exceptions
D2.3.1 Pseudocode description of routing debug exceptions
D2.4 Enabling debug exceptions from the current Exception level and Security state
D2.4.1 Disabling debug exceptions from Secure state
D2.4.2 Pseudocode description of enabling debug exceptions
D2.5 The effect of powerdown on debug exceptions
D2.6 Summary of the routing and enabling of debug exceptions
D2.7 Pseudocode description of debug exceptions
D2.8 Software Breakpoint Instruction exceptions
D2.8.1 About Software Breakpoint Instruction exceptions
D2.8.2 Breakpoint instructions
D2.8.3 Exception syndrome information and preferred return address
Exception syndrome information
Preferred return address
D2.8.4 Pseudocode description of Software Breakpoint Instruction exceptions
D2.9 Breakpoint exceptions
D2.9.1 About Breakpoint exceptions
D2.9.2 Breakpoint types and linking of breakpoints
Rules for linking breakpoints
Breakpoint types defined by DBGBCRn_EL1.BT
D2.9.3 Execution conditions for which a breakpoint generates Breakpoint exceptions
D2.9.4 Breakpoint instruction address comparisons
Specifying the halfword-aligned address that an Address breakpoint matches on
D2.9.5 Breakpoint context comparisons
D2.9.6 Breakpoint usage constraints
Reserved DBGBCR_EL1.BT values
Reserved DBGBCR_EL1.{SSC, HMC, PMC} values
Reserved DBGBCR_EL1.BAS values
Reserved DBGBCR_EL1.LBN values
Other usage constraints for Address breakpoints
Other usage constraints for Context breakpoints
D2.9.7 Exception syndrome information and preferred return address
Exception syndrome information
Preferred return address
D2.9.8 Pseudocode description of Breakpoint exceptions taken from AArch64 state
D2.10 Watchpoint exceptions
D2.10.1 About Watchpoint exceptions
D2.10.2 Watchpoint types and linking of watchpoints
Rules for linking watchpoints
D2.10.3 Execution conditions for which a watchpoint generates Watchpoint exceptions
D2.10.4 Watchpoint data address comparisons
Size of the data access
Programming a watchpoint with eight bytes or fewer
Programming a watchpoint with eight or more bytes
D2.10.5 Determining the memory location that caused a Watchpoint exception
Address recorded for Watchpoint exceptions generated by instructions other than Data Cache instructions
Address recorded for Watchpoint exceptions generated by Data Cache instructions
D2.10.6 Watchpoint behavior on other instructions
Watchpoint behavior on accesses by Store-Exclusive instructions
Watchpoint behavior on accesses by the DC IVAC instruction and the DC ZVA instruction
D2.10.7 Usage constraints
Reserved DBGWCR_EL1.{HMC, SSC, PAC} values
Reserved DBGWCR_EL1.LBN values
Programming dependencies of the BAS and MASK fields
Reserved DBGWCR_EL1.BAS values
Reserved DBGWCR_EL1.MASK values
Other usage constraints
D2.10.8 Exception syndrome information and preferred return address
Exception syndrome information
Preferred return address
D2.10.9 Pseudocode description of Watchpoint exceptions taken from AArch64 state
D2.11 Vector Catch exceptions
D2.12 Software Step exceptions
D2.12.1 About Software Step exceptions
D2.12.2 Rules for setting MDSCR_EL1.SS to 1
D2.12.3 The software step state machine
D2.12.4 Entering the active-not-pending state
D2.12.5 Behavior in the active-not-pending state
If the PE takes an exception to an Exception level that is using AArch64
If the PE takes an exception to an Exception level that is using AArch32
Summary of behavior in the active-not-pending state
D2.12.6 Entering the active-pending state
D2.12.7 Behavior in the active-pending state
D2.12.8 Stepping T32 IT instructions
D2.12.9 Exception syndrome information and preferred return address
Exception syndrome information
Preferred return address
D2.12.10 Additional considerations
Behavior when an ERET instruction is an illegal exception return
Behavior when the instruction stepped writes a misaligned PC value
Stepping code that uses exclusive monitors
Synchronization and the software step state machine
D2.12.11 Pseudocode description of Software Step exceptions
D2.13 Synchronization and debug exceptions
D3: The AArch64 System Level Memory Model
D3.1 About the memory system architecture
D3.1.1 Form of the memory system architecture
D3.1.2 Memory attributes
D3.2 Address space
D3.2.1 Instruction address space overflow
D3.3 Mixed-endian support
D3.4 Cache support
D3.4.1 General behavior of the caches
D3.4.2 Cache identification
D3.4.3 Cacheability, cache allocation hints, and cache transient hints
D3.4.4 Behavior of caches at reset
D3.4.5 Cache enabling and disabling
D3.4.6 Non-cacheable accesses and instruction caches
D3.4.7 Overview of the cache maintenance instructions
Terms used in describing the maintenance instructions
The ARMv8 abstraction of the cache hierarchy
D3.4.8 Cache maintenance instructions
Instruction cache maintenance instructions (IC*)
Data cache maintenance instructions (DC*)
EL0 accessibility to cache maintenance instructions
General requirements for the scope of maintenance instructions
Effects of instructions that operate by VA to the Point of Coherency
Effects of instructions operate by VA but not to the Point of Coherency
Effects of All and set/way maintenance instructions
Effects of virtualization and security on the cache maintenance instructions
Boundary conditions for cache maintenance instructions
Ordering and completion of data and instruction cache instructions
Performing cache maintenance instructions
D3.4.9 Data cache zero instruction
D3.4.10 Cache lockdown
The interaction of cache lockdown with cache maintenance instructions
D3.4.11 System level caches
D3.4.12 Branch prediction
D3.5 External aborts
D3.5.1 External abort on an instruction fetch
D3.5.2 External abort on data read or write
D3.5.3 Provision for the classification of external aborts
D3.5.4 Parity or ECC error reporting
D3.6 Memory barrier instructions
D3.6.1 EL2 control of the shareability of data barrier instructions executed at Non-secure EL0 or EL1
D3.7 Pseudocode description of general memory system instructions
D3.7.1 Memory data type definitions
D3.7.2 Basic memory access
D3.7.3 Aligned memory access
D3.7.4 Unaligned memory access
D3.7.5 Exclusive monitors operations
D3.7.6 Access permission checking
D3.7.7 Abort exceptions
D3.7.8 Memory barriers
D4: The AArch64 Virtual Memory System Architecture
D4.1 About the Virtual Memory System Architecture (VMSA)
D4.1.1 Address tagging in AArch64 state
Relaxation of the tagged address handling requirements on an Illegal exception return
D4.2 The VMSAv8-64 address translation system
D4.2.1 About the VMSAv8-64 address translation system
ARMv8 VMSA naming
VMSA address types and address spaces
About address translation
The VMSAv8-64 translation table format
D4.2.2 Controlling address translation stages
System registers relevant to MMU operation
Address size configuration
Atomicity of register changes on changing virtual machine
Use of out-of-context translation regimes
D4.2.3 Memory translation granule size
How the granule size affects the address translation process
Effect of granule size on translation table addressing and indexing
D4.2.4 Translation tables and the translation process
Translation table walks
Security state of translation table lookups
Control of translation table walks
D4.2.5 Overview of the VMSAv8-64 address translation stages
Overview of VMSAv8-64 address translation using the 4KB translation granule
Overview of VMSAv8-64 address translation using the 16KB translation granule
Overview of VMSAv8-64 address translation using the 64KB translation granule
D4.2.6 The VMSAv8-64 translation table format
Translation granule size and associate block and page sizes
Selection between TTBR0 and TTBR1
Concatenated translation tables for the initial stage 2 lookup
Possible translation table registers programming errors
D4.2.7 The algorithm for finding the translation table entries
Finding the translation table entry when using the 4KB translation granule
Finding the translation table entry when using the 16KB translation granule
Finding the translation table descriptor when using the 64KB translation granule
D4.2.8 The effects of disabling a stage of address translation
Behavior when stage 1 address translation is disabled
Behavior when stage 2 address translation is disabled
Behavior of instruction fetches when all associated stages of translation are disabled
D4.2.9 The implemented Exception levels and the resulting translation stages and regimes
D4.2.10 Pseudocode description of VMSAv8-64 address translation
Definitions required for address translation
Performing the full address translation
Stage 1 translation
Stage 2 translation
Translation table walk
Support functions
D4.2.11 Address translation instructions
Address translation instructions, AT*
D4.3 VMSAv8-64 translation table format descriptors
D4.3.1 VMSAv8-64 translation table level 0, level 1, and level 2 descriptor formats
Descriptor encodings, ARMv8 level 0, level 1, and level 2 formats
D4.3.2 ARMv8 translation table level 3 descriptor formats
D4.3.3 Memory attribute fields in the VMSAv8-64 translation table format descriptors
Next-level attributes in stage 1 VMSAv8-64 Table descriptors
Attribute fields in stage 1 VMSAv8-64 Block and Page descriptors
Attribute fields in stage 2 VMSAv8-64 Block and Page descriptors
D4.3.4 Control of Secure or Non-secure memory access
Hierarchical control of Secure or Non-secure memory accesses
D4.4 Access controls and memory region attributes
D4.4.1 Memory access control
About the access permissions
The data access permission controls
Access permissions for instruction execution
The Access flag
D4.4.2 Memory region attributes
The memory region attributes for stage 1 translations
The memory region attributes for stage 2 translations, EL1&0 translation regime
Other fields in the VMSAv8-64 translation table format descriptors
D4.4.3 Combining the stage 1 and stage 2 attributes, Non-secure EL1&0 translation regime
Combining the stage 1 and stage 2 data access permissions
Combining the stage 1 and stage 2 instruction execution permissions
Combining the stage 1 and stage 2 memory type attributes
Combining the stage 1 and stage 2 cacheability attributes for Normal memory
Combining the stage 1 and stage 2 shareability attributes for Normal memory
D4.5 MMU faults
D4.5.1 Types of MMU faults
Permission fault
Translation fault
Address size fault
External abort on a translation table walk
Access flag fault
D4.5.2 The MMU fault-checking sequence
Stage 2 fault on a stage 1 translation table walk
D4.5.3 AArch64 prioritization of synchronous aborts from a single stage of address translation
D4.5.4 Pseudocode description of the MMU faults
D4.6 Translation Lookaside Buffers (TLBs)
D4.6.1 About ARMv8 Translation Lookaside Buffers (TLBs)
Global and process-specific translation table entries
TLB matching
TLB behavior at reset
TLB lockdown
TLB conflict aborts
D4.7 TLB maintenance requirements and the TLB maintenance instructions
D4.7.1 General TLB maintenance requirements
Using break-before-make when updating translation table entries
D4.7.2 TLB maintenance instructions
TLB maintenance instruction syntax
Operation of the TLB maintenance instructions
Scope of the A64 TLB maintenance instructions
Invalidation of TLB entries from stage 2 translations
Broadcast TLB maintenance between AArch32 and AArch64
Broadcast TLB maintenance with different translation granule sizes
Ordering and completion of TLB maintenance instructions
TLB maintenance in the event of TLB conflict
The interaction of TLB lockdown with TLB maintenance instructions
D4.7.3 Maintenance requirements on changing System register values
Changing HCR_EL2.PTW
D4.8 Caches in a VMSA implementation
D4.8.1 Data and unified caches
D4.8.2 Instruction caches
PIPT instruction caches
VIPT instruction caches
ASID and VMID tagged VIVT instruction caches
The IVIPT Extension
D4.8.3 Cache maintenance requirement created by changing translation table attributes
D5: The Performance Monitors Extension
D5.1 About the Performance Monitors
D5.1.1 Time as measured by the Performance Monitors cycle counter
D5.1.2 Interaction with trace
D5.1.3 Interaction with power saving operations
D5.2 Accuracy of the Performance Monitors
D5.2.1 Non-invasive behavior
D5.2.2 A reasonable degree of inaccuracy
D5.3 Behavior on overflow
D5.3.1 Generating overflow interrupt requests
Pseudocode description of overflow interrupt requests
D5.4 Attributability
D5.5 Effect of EL3 and EL2
D5.5.1 Interaction with EL3
Multithreaded implementations
D5.5.2 Interaction with EL2
D5.6 Event filtering
D5.6.1 Filtering by Exception level and PE state
Reserved combinations of the filtering controls
D5.6.2 Accuracy of event filtering
Exception-related events
Software increment events
Pseudocode description of event filtering
D5.7 Performance Monitors and Debug state
D5.8 Counter enables
D5.9 Counter access
D5.9.1 PMNx event counters
D5.9.2 Cycle counter
D5.10 Events, event numbers, and mnemonics
D5.10.1 Definitions
Definition of terms
Levels of caches and TLBs
D5.10.2 Common event numbers
D5.10.3 Common architectural event numbers
D5.10.4 Common microarchitectural event numbers
D5.10.5 Meaningful ratios between common microarchitectural events
D5.10.6 Required events
D5.10.7 IMPLEMENTATION DEFINED event numbers
D5.11 Performance Monitors Extension registers
D5.11.1 Relationship between AArch32 and AArch64 Performance Monitors registers
D5.11.2 Access permissions
D6: The Generic Timer in AArch64 state
D6.1 About the Generic Timer
D6.1.1 The full set of Generic Timer components
D6.1.2 The system counter
Initializing and reading the system counter frequency
Memory-mapped controls of the system counter
D6.2 The AArch64 view of the Generic Timer
D6.2.1 The physical counter
Accessing the physical counter
D6.2.2 The virtual counter
Accessing the virtual counter
Status of the CNTVOFF register
D6.2.3 Event streams
D6.2.4 Timers
Accessing the timer registers
Operation of the CompareValue views of the timers
Operation of the TimerValue views of the timers
D7: AArch64 System Register Descriptions
D7.1 About the AArch64 System registers
D7.1.1 Fixed values in the System register descriptions
System register width
D7.1.2 General behavior of accesses to the AArch64 System registers
Synchronization requirements for AArch64 System registers
D7.1.3 Principles of the ID scheme for fields in ID registers
ID registers to which this scheme applies
D7.2 General system control registers
D7.2.1 ACTLR_EL1, Auxiliary Control Register (EL1)
Field descriptions
Accessing the ACTLR_EL1:
D7.2.2 ACTLR_EL2, Auxiliary Control Register (EL2)
Field descriptions
Accessing the ACTLR_EL2:
D7.2.3 ACTLR_EL3, Auxiliary Control Register (EL3)
Field descriptions
Accessing the ACTLR_EL3:
D7.2.4 AFSR0_EL1, Auxiliary Fault Status Register 0 (EL1)
Field descriptions
Accessing the AFSR0_EL1:
D7.2.5 AFSR0_EL2, Auxiliary Fault Status Register 0 (EL2)
Field descriptions
Accessing the AFSR0_EL2:
D7.2.6 AFSR0_EL3, Auxiliary Fault Status Register 0 (EL3)
Field descriptions
Accessing the AFSR0_EL3:
D7.2.7 AFSR1_EL1, Auxiliary Fault Status Register 1 (EL1)
Field descriptions
Accessing the AFSR1_EL1:
D7.2.8 AFSR1_EL2, Auxiliary Fault Status Register 1 (EL2)
Field descriptions
Accessing the AFSR1_EL2:
D7.2.9 AFSR1_EL3, Auxiliary Fault Status Register 1 (EL3)
Field descriptions
Accessing the AFSR1_EL3:
D7.2.10 AIDR_EL1, Auxiliary ID Register
Field descriptions
Accessing the AIDR_EL1:
D7.2.11 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register (EL1)
Field descriptions
Accessing the AMAIR_EL1:
D7.2.12 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register (EL2)
Field descriptions
Accessing the AMAIR_EL2:
D7.2.13 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register (EL3)
Field descriptions
Accessing the AMAIR_EL3:
D7.2.14 CCSIDR_EL1, Current Cache Size ID Register
Field descriptions
Accessing the CCSIDR_EL1:
D7.2.15 CLIDR_EL1, Cache Level ID Register
Field descriptions
Accessing the CLIDR_EL1:
D7.2.16 CONTEXTIDR_EL1, Context ID Register (EL1)
Field descriptions
Accessing the CONTEXTIDR_EL1:
D7.2.17 CPACR_EL1, Architectural Feature Access Control Register
Field descriptions
Accessing the CPACR_EL1:
D7.2.18 CPTR_EL2, Architectural Feature Trap Register (EL2)
Field descriptions
Accessing the CPTR_EL2:
D7.2.19 CPTR_EL3, Architectural Feature Trap Register (EL3)
Field descriptions
Accessing the CPTR_EL3:
D7.2.20 CSSELR_EL1, Cache Size Selection Register
Field descriptions
Accessing the CSSELR_EL1:
D7.2.21 CTR_EL0, Cache Type Register
Field descriptions
Accessing the CTR_EL0:
D7.2.22 DACR32_EL2, Domain Access Control Register
Field descriptions
Accessing the DACR32_EL2:
D7.2.23 DCZID_EL0, Data Cache Zero ID register
Field descriptions
Accessing the DCZID_EL0:
D7.2.24 ESR_EL1, Exception Syndrome Register (EL1)
Field descriptions
Accessing the ESR_EL1:
D7.2.25 ESR_EL2, Exception Syndrome Register (EL2)
Field descriptions
Accessing the ESR_EL2:
D7.2.26 ESR_EL3, Exception Syndrome Register (EL3)
Field descriptions
Accessing the ESR_EL3:
D7.2.27 ESR_ELx, Exception Syndrome Register (ELx)
Field descriptions
D7.2.28 FAR_EL1, Fault Address Register (EL1)
Field descriptions
Accessing the FAR_EL1:
D7.2.29 FAR_EL2, Fault Address Register (EL2)
Field descriptions
Accessing the FAR_EL2:
D7.2.30 FAR_EL3, Fault Address Register (EL3)
Field descriptions
Accessing the FAR_EL3:
D7.2.31 FPEXC32_EL2, Floating-Point Exception Control register
Field descriptions
Accessing the FPEXC32_EL2:
D7.2.32 HACR_EL2, Hypervisor Auxiliary Control Register
Field descriptions
Accessing the HACR_EL2:
D7.2.33 HCR_EL2, Hypervisor Configuration Register
Field descriptions
Accessing the HCR_EL2:
D7.2.34 HPFAR_EL2, Hypervisor IPA Fault Address Register
Field descriptions
Accessing the HPFAR_EL2:
D7.2.35 HSTR_EL2, Hypervisor System Trap Register
Field descriptions
Accessing the HSTR_EL2:
D7.2.36 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0
Field descriptions
Accessing the ID_AA64AFR0_EL1:
D7.2.37 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1
Field descriptions
Accessing the ID_AA64AFR1_EL1:
D7.2.38 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0
Field descriptions
Accessing the ID_AA64DFR0_EL1:
D7.2.39 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1
Field descriptions
Accessing the ID_AA64DFR1_EL1:
D7.2.40 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0
Field descriptions
Accessing the ID_AA64ISAR0_EL1:
D7.2.41 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1
Field descriptions
Accessing the ID_AA64ISAR1_EL1:
D7.2.42 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0
Field descriptions
Accessing the ID_AA64MMFR0_EL1:
D7.2.43 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1
Field descriptions
Accessing the ID_AA64MMFR1_EL1:
D7.2.44 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0
Field descriptions
Accessing the ID_AA64PFR0_EL1:
D7.2.45 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1
Field descriptions
Accessing the ID_AA64PFR1_EL1:
D7.2.46 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0
Field descriptions
Accessing the ID_AFR0_EL1:
D7.2.47 ID_DFR0_EL1, AArch32 Debug Feature Register 0
Field descriptions
Accessing the ID_DFR0_EL1:
D7.2.48 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0
Field descriptions
Accessing the ID_ISAR0_EL1:
D7.2.49 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1
Field descriptions
Accessing the ID_ISAR1_EL1:
D7.2.50 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2
Field descriptions
Accessing the ID_ISAR2_EL1:
D7.2.51 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3
Field descriptions
Accessing the ID_ISAR3_EL1:
D7.2.52 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4
Field descriptions
Accessing the ID_ISAR4_EL1:
D7.2.53 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5
Field descriptions
Accessing the ID_ISAR5_EL1:
D7.2.54 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0
Field descriptions
Accessing the ID_MMFR0_EL1:
D7.2.55 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1
Field descriptions
Accessing the ID_MMFR1_EL1:
D7.2.56 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2
Field descriptions
Accessing the ID_MMFR2_EL1:
D7.2.57 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3
Field descriptions
Accessing the ID_MMFR3_EL1:
D7.2.58 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4
Field descriptions
Accessing the ID_MMFR4_EL1:
D7.2.59 ID_PFR0_EL1, AArch32 Processor Feature Register 0
Field descriptions
Accessing the ID_PFR0_EL1:
D7.2.60 ID_PFR1_EL1, AArch32 Processor Feature Register 1
Field descriptions
Accessing the ID_PFR1_EL1:
D7.2.61 IFSR32_EL2, Instruction Fault Status Register (EL2)
Field descriptions
Accessing the IFSR32_EL2:
D7.2.62 ISR_EL1, Interrupt Status Register
Field descriptions
Accessing the ISR_EL1:
D7.2.63 MAIR_EL1, Memory Attribute Indirection Register (EL1)
Field descriptions
Accessing the MAIR_EL1:
D7.2.64 MAIR_EL2, Memory Attribute Indirection Register (EL2)
Field descriptions
Accessing the MAIR_EL2:
D7.2.65 MAIR_EL3, Memory Attribute Indirection Register (EL3)
Field descriptions
Accessing the MAIR_EL3:
D7.2.66 MIDR_EL1, Main ID Register
Field descriptions
Accessing the MIDR_EL1:
D7.2.67 MPIDR_EL1, Multiprocessor Affinity Register
Field descriptions
Accessing the MPIDR_EL1:
D7.2.68 MVFR0_EL1, AArch32 Media and VFP Feature Register 0
Field descriptions
Accessing the MVFR0_EL1:
D7.2.69 MVFR1_EL1, AArch32 Media and VFP Feature Register 1
Field descriptions
Accessing the MVFR1_EL1:
D7.2.70 MVFR2_EL1, AArch32 Media and VFP Feature Register 2
Field descriptions
Accessing the MVFR2_EL1:
D7.2.71 PAR_EL1, Physical Address Register
Field descriptions
Accessing the PAR_EL1:
D7.2.72 REVIDR_EL1, Revision ID Register
Field descriptions
Accessing the REVIDR_EL1:
D7.2.73 RMR_EL1, Reset Management Register (if EL2 and EL3 not implemented)
Field descriptions
Accessing the RMR_EL1:
D7.2.74 RMR_EL2, Reset Management Register (if EL2 implemented and EL3 not implemented)
Field descriptions
Accessing the RMR_EL2:
D7.2.75 RMR_EL3, Reset Management Register (if EL3 implemented)
Field descriptions
Accessing the RMR_EL3:
D7.2.76 RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented)
Field descriptions
Accessing the RVBAR_EL1:
D7.2.77 RVBAR_EL2, Reset Vector Base Address Register (if EL3 not implemented)
Field descriptions
Accessing the RVBAR_EL2:
D7.2.78 RVBAR_EL3, Reset Vector Base Address Register (if EL3 implemented)
Field descriptions
Accessing the RVBAR_EL3:
D7.2.79 S3____, IMPLEMENTATION DEFINED registers
Field descriptions
Accessing the S3____:
D7.2.80 SCR_EL3, Secure Configuration Register
Field descriptions
Accessing the SCR_EL3:
D7.2.81 SCTLR_EL1, System Control Register (EL1)
Field descriptions
Accessing the SCTLR_EL1:
D7.2.82 SCTLR_EL2, System Control Register (EL2)
Field descriptions
Accessing the SCTLR_EL2:
D7.2.83 SCTLR_EL3, System Control Register (EL3)
Field descriptions
Accessing the SCTLR_EL3:
D7.2.84 TCR_EL1, Translation Control Register (EL1)
Field descriptions
Accessing the TCR_EL1:
D7.2.85 TCR_EL2, Translation Control Register (EL2)
Field descriptions
Accessing the TCR_EL2:
D7.2.86 TCR_EL3, Translation Control Register (EL3)
Field descriptions
Accessing the TCR_EL3:
D7.2.87 TPIDR_EL0, EL0 Read/Write Software Thread ID Register
Field descriptions
Accessing the TPIDR_EL0:
D7.2.88 TPIDR_EL1, EL1 Software Thread ID Register
Field descriptions
Accessing the TPIDR_EL1:
D7.2.89 TPIDR_EL2, EL2 Software Thread ID Register
Field descriptions
Accessing the TPIDR_EL2:
D7.2.90 TPIDR_EL3, EL3 Software Thread ID Register
Field descriptions
Accessing the TPIDR_EL3:
D7.2.91 TPIDRRO_EL0, EL0 Read-Only Software Thread ID Register
Field descriptions
Accessing the TPIDRRO_EL0:
D7.2.92 TTBR0_EL1, Translation Table Base Register 0 (EL1)
Field descriptions
Accessing the TTBR0_EL1:
D7.2.93 TTBR0_EL2, Translation Table Base Register 0 (EL2)
Field descriptions
Accessing the TTBR0_EL2:
D7.2.94 TTBR0_EL3, Translation Table Base Register 0 (EL3)
Field descriptions
Accessing the TTBR0_EL3:
D7.2.95 TTBR1_EL1, Translation Table Base Register 1 (EL1)
Field descriptions
Accessing the TTBR1_EL1:
D7.2.96 VBAR_EL1, Vector Base Address Register (EL1)
Field descriptions
Accessing the VBAR_EL1:
D7.2.97 VBAR_EL2, Vector Base Address Register (EL2)
Field descriptions
Accessing the VBAR_EL2:
D7.2.98 VBAR_EL3, Vector Base Address Register (EL3)
Field descriptions
Accessing the VBAR_EL3:
D7.2.99 VMPIDR_EL2, Virtualization Multiprocessor ID Register
Field descriptions
Accessing the VMPIDR_EL2:
D7.2.100 VPIDR_EL2, Virtualization Processor ID Register
Field descriptions
Accessing the VPIDR_EL2:
D7.2.101 VTCR_EL2, Virtualization Translation Control Register
Field descriptions
Accessing the VTCR_EL2:
D7.2.102 VTTBR_EL2, Virtualization Translation Table Base Register
Field descriptions
Accessing the VTTBR_EL2:
D7.3 Debug registers
D7.3.1 DBGAUTHSTATUS_EL1, Debug Authentication Status register
Field descriptions
Accessing the DBGAUTHSTATUS_EL1:
D7.3.2 DBGBCR_EL1, Debug Breakpoint Control Registers, n = 0 - 15
Field descriptions
Accessing the DBGBCR_EL1:
D7.3.3 DBGBVR_EL1, Debug Breakpoint Value Registers, n = 0 - 15
Field descriptions
Accessing the DBGBVR_EL1:
D7.3.4 DBGCLAIMCLR_EL1, Debug Claim Tag Clear register
Field descriptions
Accessing the DBGCLAIMCLR_EL1:
D7.3.5 DBGCLAIMSET_EL1, Debug Claim Tag Set register
Field descriptions
Accessing the DBGCLAIMSET_EL1:
D7.3.6 DBGDTR_EL0, Debug Data Transfer Register, half-duplex
Field descriptions
Accessing the DBGDTR_EL0:
D7.3.7 DBGDTRRX_EL0, Debug Data Transfer Register, Receive
Field descriptions
Accessing the DBGDTRRX_EL0:
D7.3.8 DBGDTRTX_EL0, Debug Data Transfer Register, Transmit
Field descriptions
Accessing the DBGDTRTX_EL0:
D7.3.9 DBGPRCR_EL1, Debug Power Control Register
Field descriptions
Accessing the DBGPRCR_EL1:
D7.3.10 DBGVCR32_EL2, Debug Vector Catch Register
Field descriptions
Accessing the DBGVCR32_EL2:
D7.3.11 DBGWCR_EL1, Debug Watchpoint Control Registers, n = 0 - 15
Field descriptions
Accessing the DBGWCR_EL1:
D7.3.12 DBGWVR_EL1, Debug Watchpoint Value Registers, n = 0 - 15
Field descriptions
Accessing the DBGWVR_EL1:
D7.3.13 DLR_EL0, Debug Link Register
Field descriptions
Accessing the DLR_EL0:
D7.3.14 DSPSR_EL0, Debug Saved Program Status Register
Field descriptions
Accessing the DSPSR_EL0:
D7.3.15 MDCCINT_EL1, Monitor DCC Interrupt Enable Register
Field descriptions
Accessing the MDCCINT_EL1:
D7.3.16 MDCCSR_EL0, Monitor DCC Status Register
Field descriptions
Accessing the MDCCSR_EL0:
D7.3.17 MDCR_EL2, Monitor Debug Configuration Register (EL2)
Field descriptions
Accessing the MDCR_EL2:
D7.3.18 MDCR_EL3, Monitor Debug Configuration Register (EL3)
Field descriptions
Accessing the MDCR_EL3:
D7.3.19 MDRAR_EL1, Monitor Debug ROM Address Register
Field descriptions
Accessing the MDRAR_EL1:
D7.3.20 MDSCR_EL1, Monitor Debug System Control Register
Field descriptions
Accessing the MDSCR_EL1:
D7.3.21 OSDLR_EL1, OS Double Lock Register
Field descriptions
Accessing the OSDLR_EL1:
D7.3.22 OSDTRRX_EL1, OS Lock Data Transfer Register, Receive
Field descriptions
Accessing the OSDTRRX_EL1:
D7.3.23 OSDTRTX_EL1, OS Lock Data Transfer Register, Transmit
Field descriptions
Accessing the OSDTRTX_EL1:
D7.3.24 OSECCR_EL1, OS Lock Exception Catch Control Register
Field descriptions
Accessing the OSECCR_EL1:
D7.3.25 OSLAR_EL1, OS Lock Access Register
Field descriptions
Accessing the OSLAR_EL1:
D7.3.26 OSLSR_EL1, OS Lock Status Register
Field descriptions
Accessing the OSLSR_EL1:
D7.3.27 SDER32_EL3, AArch32 Secure Debug Enable Register
Field descriptions
Accessing the SDER32_EL3:
D7.4 Performance Monitors registers
D7.4.1 PMCCFILTR_EL0, Performance Monitors Cycle Count Filter Register
Field descriptions
Accessing the PMCCFILTR_EL0:
D7.4.2 PMCCNTR_EL0, Performance Monitors Cycle Count Register
Field descriptions
Accessing the PMCCNTR_EL0:
D7.4.3 PMCEID0_EL0, Performance Monitors Common Event Identification register 0
Field descriptions
Accessing the PMCEID0_EL0:
D7.4.4 PMCEID1_EL0, Performance Monitors Common Event Identification register 1
Field descriptions
Accessing the PMCEID1_EL0:
D7.4.5 PMCNTENCLR_EL0, Performance Monitors Count Enable Clear register
Field descriptions
Accessing the PMCNTENCLR_EL0:
D7.4.6 PMCNTENSET_EL0, Performance Monitors Count Enable Set register
Field descriptions
Accessing the PMCNTENSET_EL0:
D7.4.7 PMCR_EL0, Performance Monitors Control Register
Field descriptions
Accessing the PMCR_EL0:
D7.4.8 PMEVCNTR_EL0, Performance Monitors Event Count Registers, n = 0 - 30
Field descriptions
Accessing the PMEVCNTR_EL0:
D7.4.9 PMEVTYPER_EL0, Performance Monitors Event Type Registers, n = 0 - 30
Field descriptions
Accessing the PMEVTYPER_EL0:
D7.4.10 PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear register
Field descriptions
Accessing the PMINTENCLR_EL1:
D7.4.11 PMINTENSET_EL1, Performance Monitors Interrupt Enable Set register
Field descriptions
Accessing the PMINTENSET_EL1:
D7.4.12 PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear Register
Field descriptions
Accessing the PMOVSCLR_EL0:
D7.4.13 PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set register
Field descriptions
Accessing the PMOVSSET_EL0:
D7.4.14 PMSELR_EL0, Performance Monitors Event Counter Selection Register
Field descriptions
Accessing the PMSELR_EL0:
D7.4.15 PMSWINC_EL0, Performance Monitors Software Increment register
Field descriptions
Accessing the PMSWINC_EL0:
D7.4.16 PMUSERENR_EL0, Performance Monitors User Enable Register
Field descriptions
Accessing the PMUSERENR_EL0:
D7.4.17 PMXEVCNTR_EL0, Performance Monitors Selected Event Count Register
Field descriptions
Accessing the PMXEVCNTR_EL0:
D7.4.18 PMXEVTYPER_EL0, Performance Monitors Selected Event Type Register
Field descriptions
Accessing the PMXEVTYPER_EL0:
D7.5 Generic Timer registers
D7.5.1 CNTFRQ_EL0, Counter-timer Frequency register
Field descriptions
Accessing the CNTFRQ_EL0:
D7.5.2 CNTHCTL_EL2, Counter-timer Hypervisor Control register
Field descriptions
Accessing the CNTHCTL_EL2:
D7.5.3 CNTHP_CTL_EL2, Counter-timer Hypervisor Physical Timer Control register
Field descriptions
Accessing the CNTHP_CTL_EL2:
D7.5.4 CNTHP_CVAL_EL2, Counter-timer Hypervisor Physical Timer CompareValue register
Field descriptions
Accessing the CNTHP_CVAL_EL2:
D7.5.5 CNTHP_TVAL_EL2, Counter-timer Hypervisor Physical Timer TimerValue register
Field descriptions
Accessing the CNTHP_TVAL_EL2:
D7.5.6 CNTKCTL_EL1, Counter-timer Kernel Control register
Field descriptions
Accessing the CNTKCTL_EL1:
D7.5.7 CNTP_CTL_EL0, Counter-timer Physical Timer Control register
Field descriptions
Accessing the CNTP_CTL_EL0:
D7.5.8 CNTP_CVAL_EL0, Counter-timer Physical Timer CompareValue register
Field descriptions
Accessing the CNTP_CVAL_EL0:
D7.5.9 CNTP_TVAL_EL0, Counter-timer Physical Timer TimerValue register
Field descriptions
Accessing the CNTP_TVAL_EL0:
D7.5.10 CNTPCT_EL0, Counter-timer Physical Count register
Field descriptions
Accessing the CNTPCT_EL0:
D7.5.11 CNTPS_CTL_EL1, Counter-timer Physical Secure Timer Control register
Field descriptions
Accessing the CNTPS_CTL_EL1:
D7.5.12 CNTPS_CVAL_EL1, Counter-timer Physical Secure Timer CompareValue register
Field descriptions
Accessing the CNTPS_CVAL_EL1:
D7.5.13 CNTPS_TVAL_EL1, Counter-timer Physical Secure Timer TimerValue register
Field descriptions
Accessing the CNTPS_TVAL_EL1:
D7.5.14 CNTV_CTL_EL0, Counter-timer Virtual Timer Control register
Field descriptions
Accessing the CNTV_CTL_EL0:
D7.5.15 CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register
Field descriptions
Accessing the CNTV_CVAL_EL0:
D7.5.16 CNTV_TVAL_EL0, Counter-timer Virtual Timer TimerValue register
Field descriptions
Accessing the CNTV_TVAL_EL0:
D7.5.17 CNTVCT_EL0, Counter-timer Virtual Count register
Field descriptions
Accessing the CNTVCT_EL0:
D7.5.18 CNTVOFF_EL2, Counter-timer Virtual Offset register
Field descriptions
Accessing the CNTVOFF_EL2:
Part E: The AArch32 Application Level Architecture
E1: The AArch32 Application Level Programmers’ Model
E1.1 About the Application level programmers’ model
E1.2 Additional information about the programmers’ model in AArch32 state
E1.2.1 Instruction sets, arithmetic operations, and register files
E1.2.2 Core data types and arithmetic in AArch32 state
Integer arithmetic
E1.2.3 The general-purpose registers, and the PC, in AArch32 state
Writing to the PC
Pseudocode description of operations on the AArch32 general-purpose registers and the PC
E1.2.4 Process state, PSTATE
Accessing PSTATE fields at EL0
Pseudocode description of PSTATE PE state fields
E1.2.5 Jazelle support
E1.3 Advanced SIMD and floating-point instructions
E1.3.1 The SIMD and floating-point register file
Advanced SIMD views of the register file
Floating-point views of the register file
SIMD and Floating-point register file mapping onto registers
Pseudocode description of the SIMD and Floating-point register file
E1.3.2 Data types supported by the Advanced SIMD implementation
Advanced SIMD vectors
E1.3.3 Advanced SIMD and floating-point System registers
E1.3.4 Trapping of floating-point exceptions
E1.3.5 Floating-point data types and arithmetic
E1.3.6 Floating-point exceptions
Combinations of floating-point exceptions
E1.3.7 Controls of Advanced SIMD operation that do not apply to floating-point operation
E1.3.8 Implications of not including Advanced SIMD and floating-point support
E1.3.9 Pseudocode description of floating-point operations
Generation of specific floating-point values
Floating-point negation and absolute value
Floating-point value unpacking
Floating-point exception and NaN handling
Floating-point rounding
Selection of ARM standard floating-point arithmetic
Floating-point comparisons
Floating-point maximum and minimum
Floating-point addition and subtraction
Floating-point multiplication and division
Floating-point fused multiply-add
Floating-point reciprocal estimate and step
Floating-point square root
Floating-point reciprocal square root estimate and step
Floating-point conversions
E1.4 Conceptual coprocessor support
E1.5 Exceptions
E2: The AArch32 Application Level Memory Model
E2.1 Address space
E2.2 Memory type overview
E2.3 Caches and memory hierarchy
E2.3.1 Introduction to caches
E2.3.2 Memory hierarchy
The Cacheability and Shareability memory attributes
E2.3.3 Implication of caches for the application programmer
Data coherency issues
Synchronization and coherency issues between data and instruction accesses
E2.3.4 Preloading caches
E2.4 Alignment support
E2.4.1 Instruction alignment
E2.4.2 Unaligned data access
E2.4.3 Cases where unaligned accesses are CONSTRAINED UNPREDICTABLE
E2.4.4 Unaligned data access restrictions
E2.5 Endian support
E2.5.1 General description of endianness in the ARM architecture
E2.5.2 Instruction endianness
E2.5.3 Data endianness
Instructions to reverse bytes in registers
Endianness in Advanced SIMD
E2.6 Atomicity in the ARM architecture
E2.6.1 Requirements for single-copy atomicity
E2.6.2 Properties of single-copy atomic accesses
E2.6.3 Multi-copy atomicity
E2.6.4 Requirements for multi-copy atomicity
E2.6.5 Concurrent modification and execution of instructions
E2.7 Memory ordering
E2.7.1 Observability and completion
Completion of side-effects of accesses to Device memory
E2.7.2 Ordering requirements
Address dependencies and order
E2.7.3 Memory barriers
Instruction Synchronization Barrier (ISB)
Data Memory Barrier (DMB)
Data Synchronization Barrier (DSB)
Shareability and access limitations on the data barrier operations
Load-Acquire, Store-Release
E2.7.4 Summary of the memory ordering rules
Terms used in the summary of the memory ordering rules
E2.8 Memory types and attributes
E2.8.1 Normal memory
Shareable Normal memory
Non-shareable Normal memory
Write-Through Cacheable, Write-Back Cacheable and Non-cacheable Normal memory
Multi-register loads and stores that access Normal memory
E2.8.2 Device memory
Gathering
Reordering
Early Write Acknowledgement
Multi-register loads and stores that access Device memory
E2.8.3 Memory access restrictions
E2.9 Mismatched memory attributes
E2.10 Synchronization and semaphores
E2.10.1 Exclusive access instructions and Non-shareable memory locations
Changes to the local monitor state resulting from speculative execution
E2.10.2 Exclusive access instructions and shareable memory locations
Operation of the global monitor
E2.10.3 Marking and the size of the marked memory block
E2.10.4 Context switch support
E2.10.5 Load-Exclusive and Store-Exclusive instruction usage restrictions
E2.10.6 Use of WFE and SEV instructions by spin-locks
Part F: The AArch32 Instruction Sets
F1: The AArch32 Instruction Sets Overview
F1.1 Support for instructions in different versions of the ARM architecture
F1.2 Unified Assembler Language
F1.2.1 Conditional instructions
F1.2.2 Use of labels in UAL instruction syntax
F1.3 Branch instructions
F1.4 Data-processing instructions
F1.4.1 Standard data-processing instructions
F1.4.2 Shift instructions
F1.4.3 Multiply instructions
F1.4.4 Saturating instructions
F1.4.5 Saturating addition and subtraction instructions
F1.4.6 Packing and unpacking instructions
F1.4.7 Parallel addition and subtraction instructions
F1.4.8 Divide instructions
F1.4.9 Miscellaneous data-processing instructions
F1.5 PSTATE and banked register access instructions
F1.5.1 PSTATE access instructions
F1.5.2 Banked register access instructions
F1.6 Load/store instructions
F1.6.1 Loads to the PC
F1.6.2 Halfword and byte loads and stores
F1.6.3 Load unprivileged and Store unprivileged
F1.6.4 Load-Exclusive and Store-Exclusive
F1.6.5 Load-Acquire and Store-Release
F1.6.6 Addressing modes
F1.7 Load/store multiple instructions
F1.7.1 Loads to the PC
F1.8 Miscellaneous instructions
F1.8.1 The Yield instruction
F1.9 Exception-generating and exception-handling instructions
F1.10 Coprocessor instructions
F1.11 Advanced SIMD and floating-point load/store instructions
F1.11.1 Element and structure load/store instructions
F1.12 Advanced SIMD and floating-point register transfer instructions
F1.13 Advanced SIMD data-processing instructions
F1.13.1 Advanced SIMD parallel addition and subtraction
F1.13.2 Bitwise Advanced SIMD data-processing instructions
F1.13.3 Advanced SIMD comparison instructions
F1.13.4 Advanced SIMD shift instructions
F1.13.5 Advanced SIMD multiply instructions
F1.13.6 Miscellaneous Advanced SIMD data-processing instructions
F1.14 Floating-point data-processing instructions
F2: About the T32 and A32 Instruction Descriptions
F2.1 Format of instruction descriptions
F2.1.1 Instruction section title
F2.1.2 Introduction to the instruction
F2.1.3 Instruction encodings
F2.1.4 Assembler symbols
Assembler syntax prototype line conventions
F2.1.5 Pseudocode describing how the instruction operates
F2.2 Standard assembler syntax fields
F2.3 Conditional execution
F2.3.1 The condition code field in A32 instruction encodings
F2.3.2 Pseudocode description of conditional execution
F2.4 Shifts applied to a register
F2.4.1 Constant shifts
Encoding
F2.4.2 Register controlled shifts
F2.4.3 Pseudocode description of instruction-specified shifts and rotates
F2.5 Memory accesses
F2.6 Encoding of lists of general-purpose registers and the PC
F2.7 About the T32 and A32 instruction encodings
F2.7.1 UNDEFINED, UNPREDICTABLE, and CONSTRAINED UNPREDICTABLE instruction set space
F2.7.2 Advanced SIMD and floating-point instruction encodings
Advanced SIMD data-processing
Advanced SIMD element or structure load/store
Floating-point and Advanced SIMD load/store and 64-bit register moves
Floating-point and Advanced SIMD 32-bit register moves
Floating-point data-processing
F2.7.3 The PC and the use of 0b1111 as a register specifier
T32 restrictions on the use of the PC, and use of 0b1111 as a register specifier
A32 restrictions on the use of PC or 0b1111 as a register specifier
F2.7.4 The SP and the use of 0b1101 as a register specifier
F2.7.5 Modified immediate constants
Modified immediate constants in T32 instructions
Modified immediate constants in A32 instructions
Modified immediate constants in T32 and A32 Advanced SIMD instructions
Modified immediate constants in T32 and A32 floating-point instructions
F2.8 Additional pseudocode support for instruction descriptions
F2.8.1 Pseudocode description of coprocessor operations
F2.8.2 Pseudocode details of system calls
F2.9 Additional information about Advanced SIMD and floating-point instructions
F2.9.1 Advanced SIMD and floating-point instruction syntax
F2.9.2 Advanced SIMD addressing mode
F2.9.3 Advanced SIMD instruction modifiers
F2.9.4 Advanced SIMD operand shapes
F2.9.5 Data type specifiers
Syntax flexibility
F2.9.6 Register specifiers
F2.9.7 Register lists
Syntax flexibility
F2.9.8 Register encoding
F2.9.9 Advanced SIMD scalars
F3: The T32 Instruction Set Encoding
F3.1 Top level T32 instruction set encoding
F3.1.1 About the T32 Advanced SIMD and floating-point instructions and their encoding
F3.2 16-bit T32 instruction encoding
F3.2.1 Shift (immediate), add, subtract, move, and compare
Add, subtract (three low registers)
Add, subtract (two low registers and immediate)
Add, subtract, compare, move (one low register and immediate)
F3.2.2 Data-processing (two low registers)
F3.2.3 Special data instructions and branch and exchange
Branch and exchange
Add, subtract, compare, move (two high registers)
F3.2.4 Load/store (register offset)
F3.2.5 Load/store word/byte (immediate offset)
F3.2.6 Load/store halfword (immediate offset)
F3.2.7 Load/store (SP-relative)
F3.2.8 Add PC/SP (immediate)
F3.2.9 Miscellaneous 16-bit instructions
Adjust SP (immediate)
Extend
Change Processor State
Reverse bytes
Hints
Push and Pop
F3.2.10 Load/store multiple
F3.2.11 Conditional branch, and Supervisor Call
Exception generation
F3.3 32-bit T32 instruction encoding
F3.3.1 Coprocessor, Advanced SIMD, and floating-point instructions
Floating-point and Advanced SIMD load/store and 64-bit register moves
Floating-point data-processing
Floating-point and Advanced SIMD 32-bit register moves
Advanced SIMD data-processing
Coprocessor
F3.3.2 Load/store multiple
F3.3.3 Load/store dual, load/store exclusive, table branch
Load/store exclusive
Load/store exclusive byte/half/dual
Load-acquire / Store-release
Load/store dual (immediate, post-indexed)
Load/store dual (immediate)
Load/store dual (immediate, pre-indexed)
F3.3.4 Data-processing (shifted register)
F3.3.5 Branches and miscellaneous control
Hints
Change processor state
Miscellaneous system
Exception return
DCPS
Exception generation
F3.3.6 Data-processing (modified immediate)
F3.3.7 Data-processing (plain binary immediate)
Data-processing (simple immediate)
Move Wide (16-bit immediate)
Saturate, Bitfield
F3.3.8 Advanced SIMD element or structure load/store
Advanced SIMD load/store multiple structures (immediate, post-indexed)
Advanced SIMD load/store multiple structures (no writeback)
Advanced SIMD load/store multiple structures (register, post-indexed)
Advanced SIMD load single structure to all lanes (immediate, post-indexed)
Advanced SIMD load single structure to all lanes (no writeback)
Advanced SIMD load single structure to all lanes (register, post-indexed)
Advanced SIMD load/store single structure to one lane (immediate, post-indexed)
Advanced SIMD load/store single structure to one lane (no writeback)
Advanced SIMD load/store single structure to one lane (register, post-indexed)
F3.3.9 Load/store single
Load/store (register offset)
Load/store (immediate, post-indexed)
Load/store (negative immediate)
Load/store (unprivileged)
Load/store (immediate, pre-indexed)
Load/store (positive immediate)
Load literal
F3.3.10 Data-processing (register)
Register extends
Parallel add-subtract
Data-processing (two source registers)
F3.3.11 Multiply, multiply accumulate, and absolute difference
Multiply and absolute difference
F3.3.12 Long multiply and divide
F4: The A32 Instruction Set Encoding
F4.1 Top level A32 instruction set encoding
F4.1.1 About the A32 Advanced SIMD and floating-point instructions and their encodings
F4.2 Data-processing and miscellaneous instructions
F4.2.1 Extra load/store
Load/Store Dual, Half, Signed Byte (register)
Load/Store Dual, Half, Signed Byte (immediate, literal)
F4.2.2 Multiply and Accumulate
F4.2.3 Synchronization primitives
Load/Store Exclusive
F4.2.4 Miscellaneous
Exception Generation
Move special register (register)
Cyclic Redundancy Check
Integer Saturating Arithmetic
F4.2.5 Halfword Multiply and Accumulate
F4.2.6 Data-processing register (immediate shift)
Integer Data Processing (three register, immediate shift)
Integer Test & Compare (two register, immediate shift)
Logical Arithmetic (three register, immediate shift)
F4.2.7 Data-processing register (register shift)
Integer Data Processing (three register, register shift)
Integer Test & Compare (two register, register shift)
Logical Arithmetic (three register, register shift)
F4.2.8 Data-processing immediate
Integer Data Processing (two register and immediate)
Move Halfword (immediate)
Move Special Register & Hints (immediate)
Integer Test & Compare (one register and immediate)
Logical Arithmetic (two register and immediate)
F4.3 Load/Store Word, Unsigned Byte (immediate, literal)
F4.4 Load/Store Word, Unsigned Byte (register)
F4.5 Media instructions
F4.5.1 Parallel Arithmetic
F4.5.2 Saturate 16-bit
F4.5.3 Reverse Bit/Byte
F4.5.4 Saturate 32-bit
F4.5.5 Extend and Add
F4.5.6 Signed multiply, Divide
F4.5.7 Unsigned Sum of Absolute Differences
F4.5.8 Bitfield Insert
F4.5.9 Permanently UNDEFINED
F4.5.10 Bitfield Extract
F4.6 Branch, branch with link, and block data transfer
F4.6.1 Exception Save/Restore
F4.6.2 Load/Store Multiple
F4.6.3 Branch (immediate)
F4.7 Coprocessor instructions, and Supervisor Call
F4.7.1 Floating-point and Advanced SIMD load/store and 64-bit register moves
Advanced SIMD and floating-point 64-bit move
Advanced SIMD and floating-point load/store
F4.7.2 Floating-point data-processing
Floating-point minNum/maxNum
Floating-point directed convert to integer
Floating-point data-processing (two registers)
Floating-point data-processing (three registers)
F4.7.3 Floating-point and Advanced SIMD 32-bit register moves
Floating-point move special register
Advanced SIMD 8/16/32-bit element move/duplicate
F4.7.4 Supervisor call
F4.7.5 Coprocessor instructions
Coprocessor 64-bit Move
Coprocessor Load/Store
Coprocessor 32-bit Move
F4.8 Unconditional instructions
F4.8.1 Miscellaneous
Change Process State
F4.8.2 Advanced SIMD data-processing
Advanced SIMD two registers misc
Advanced SIMD duplicate (scalar)
Advanced SIMD three registers of the same length
Advanced SIMD one register and modified immediate
Advanced SIMD three registers of different lengths
Advanced SIMD two registers and a scalar
Advanced SIMD two registers and shift amount
F4.8.3 Memory hints and barriers
Barriers
Preload (immediate)
Preload (register)
F4.8.4 Advanced SIMD element or structure load/store
Advanced SIMD load/store multiple structures (immediate, post-indexed)
Advanced SIMD load/store multiple structures (no writeback)
Advanced SIMD load/store multiple structures (register, post-indexed)
Advanced SIMD load single structure to all lanes (immediate, post-indexed)
Advanced SIMD load single structure to all lanes (no writeback)
Advanced SIMD load single structure to all lanes (register, post-indexed)
Advanced SIMD load/store single structure to one lane (immediate, post-indexed)
Advanced SIMD load/store single structure to one lane (no writeback)
Advanced SIMD load/store single structure to one lane (register, post-indexed)
F5: T32 and A32 Base Instruction Set Instruction Descriptions
F5.1 Alphabetical list of T32 and A32 base instruction set instructions
F5.1.1 ADC, ADCS (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.2 ADC, ADCS (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.3 ADC, ADCS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.4 ADD, ADDS (immediate)
A1
T1
T2
T3
T4
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.5 ADD, ADDS (register)
A1
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.6 ADD, ADDS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.7 ADD, ADDS (SP plus immediate)
A1
T1
T2
T3
T4
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.8 ADD, ADDS (SP plus register)
A1
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.9 ADD (immediate, to PC)
A1
T1
T3
Assembler symbols
Operation for all encodings
F5.1.10 ADR
A1
A2
T1
T2
T3
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F5.1.11 AND, ANDS (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.12 AND, ANDS (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.13 AND, ANDS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.14 ASR (immediate)
A1
T2
T3
Assembler symbols
Operation for all encodings
F5.1.15 ASR (register)
A1
T1
T2
Assembler symbols
Operation for all encodings
F5.1.16 ASRS (immediate)
A1
T2
T3
Assembler symbols
Operation for all encodings
F5.1.17 ASRS (register)
A1
T1
T2
Assembler symbols
Operation for all encodings
F5.1.18 B
A1
T1
T2
T3
T4
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.19 BFC
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.20 BFI
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.21 BIC, BICS (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.22 BIC, BICS (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.23 BIC, BICS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.24 BKPT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.25 BL, BLX (immediate)
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.26 BLX (register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.27 BX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.28 BXJ
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.29 CBNZ, CBZ
T1
Notes for all encodings
Assembler symbols
Operation
F5.1.30 CDP, CDP2
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.31 CLREX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.32 CLZ
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.33 CMN (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.34 CMN (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.35 CMN (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.36 CMP (immediate)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.37 CMP (register)
A1
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.38 CMP (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.39 CPS, CPSID, CPSIE
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.40 CRC32
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.41 CRC32C
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.42 DBG
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.43 DCPS1, DCPS2, DCPS3
T1
Operation
F5.1.44 DMB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.45 DSB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.46 EOR, EORS (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.47 EOR, EORS (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.48 EOR, EORS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.49 ERET
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.50 HLT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.51 HVC
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.52 ISB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.53 IT
T1
Notes for all encodings
Assembler symbols
Operation
F5.1.54 LDA
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.55 LDAB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.56 LDAEX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.57 LDAEXB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.58 LDAEXD
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.59 LDAEXH
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.60 LDAH
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.61 LDC, LDC2 (immediate)
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.62 LDC, LDC2 (literal)
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.63 LDM, LDMIA, LDMFD
A1
T1
T2
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F5.1.64 LDM (exception return)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.65 LDM (User registers)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.66 LDMDA, LDMFA
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.67 LDMDB, LDMEA
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.68 LDMIB, LDMED
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.69 LDR (immediate)
A1
T1
T2
T3
T4
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F5.1.70 LDR (literal)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.71 LDR (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.72 LDRB (immediate)
A1
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.73 LDRB (literal)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.74 LDRB (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.75 LDRBT
A1
A2
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.76 LDRD (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.77 LDRD (literal)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.78 LDRD (register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.79 LDREX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.80 LDREXB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.81 LDREXD
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.82 LDREXH
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.83 LDRH (immediate)
A1
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.84 LDRH (literal)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.85 LDRH (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.86 LDRHT
A1
A2
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.87 LDRSB (immediate)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.88 LDRSB (literal)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.89 LDRSB (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.90 LDRSBT
A1
A2
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.91 LDRSH (immediate)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.92 LDRSH (literal)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.93 LDRSH (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.94 LDRSHT
A1
A2
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.95 LDRT
A1
A2
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.96 LSL (immediate)
A1
T2
T3
Assembler symbols
Operation for all encodings
F5.1.97 LSL (register)
A1
T1
T2
Assembler symbols
Operation for all encodings
F5.1.98 LSLS (immediate)
A1
T2
T3
Assembler symbols
Operation for all encodings
F5.1.99 LSLS (register)
A1
T1
T2
Assembler symbols
Operation for all encodings
F5.1.100 LSR (immediate)
A1
T2
T3
Assembler symbols
Operation for all encodings
F5.1.101 LSR (register)
A1
T1
T2
Assembler symbols
Operation for all encodings
F5.1.102 LSRS (immediate)
A1
T2
T3
Assembler symbols
Operation for all encodings
F5.1.103 LSRS (register)
A1
T1
T2
Assembler symbols
Operation for all encodings
F5.1.104 MCR, MCR2
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.105 MCRR, MCRR2
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.106 MLA, MLAS
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.107 MLS
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.108 MOV, MOVS (immediate)
A1
A2
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.109 MOV, MOVS (register)
A1
T1
T2
T3
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F5.1.110 MOV, MOVS (register-shifted register)
A1
T1
T2
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F5.1.111 MOVT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.112 MRC, MRC2
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.113 MRRC, MRRC2
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.114 MRS
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.115 MRS (Banked register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.116 MSR (Banked register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.117 MSR (immediate)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.118 MSR (register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.119 MUL, MULS
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.120 MVN, MVNS (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.121 MVN, MVNS (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.122 MVN, MVNS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.123 NOP
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.124 ORN, ORNS (immediate)
T1
Notes for all encodings
Assembler symbols
Operation
F5.1.125 ORN, ORNS (register)
T1
Notes for all encodings
Assembler symbols
Operation
F5.1.126 ORR, ORRS (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.127 ORR, ORRS (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.128 ORR, ORRS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.129 PKHBT, PKHTB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.130 PLD, PLDW (immediate)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.131 PLD (literal)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.132 PLD, PLDW (register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.133 PLI (immediate, literal)
A1
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.134 PLI (register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.135 POP
T1
Notes for all encodings
Assembler symbols
Operation
F5.1.136 POP (multiple registers)
A1
T2
Assembler symbols
Operation for all encodings
F5.1.137 POP (single register)
A1
T4
Assembler symbols
Operation for all encodings
F5.1.138 PUSH
T1
Notes for all encodings
Assembler symbols
Operation
F5.1.139 PUSH (multiple registers)
A1
T1
Assembler symbols
Operation for all encodings
F5.1.140 PUSH (single register)
A1
T4
Assembler symbols
Operation for all encodings
F5.1.141 QADD
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.142 QADD16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.143 QADD8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.144 QASX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.145 QDADD
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.146 QDSUB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.147 QSAX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.148 QSUB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.149 QSUB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.150 QSUB8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.151 RBIT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.152 REV
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.153 REV16
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.154 REVSH
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.155 RFE, RFEDA, RFEDB, RFEIA, RFEIB
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.156 ROR (immediate)
A1
T3
Assembler symbols
Operation for all encodings
F5.1.157 ROR (register)
A1
T1
T2
Assembler symbols
Operation for all encodings
F5.1.158 RORS (immediate)
A1
T3
Assembler symbols
Operation for all encodings
F5.1.159 RORS (register)
A1
T1
T2
Assembler symbols
Operation for all encodings
F5.1.160 RRX
A1
T3
Assembler symbols
Operation for all encodings
F5.1.161 RRXS
A1
T3
Assembler symbols
Operation for all encodings
F5.1.162 RSB, RSBS (immediate)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.163 RSB, RSBS (register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.164 RSB, RSBS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.165 RSC, RSCS (immediate)
A1
Assembler symbols
Operation
F5.1.166 RSC, RSCS (register)
A1
Assembler symbols
Operation
F5.1.167 RSC, RSCS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.168 SADD16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.169 SADD8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.170 SASX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.171 SBC, SBCS (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.172 SBC, SBCS (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.173 SBC, SBCS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.174 SBFX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.175 SDIV
A1
T1
Notes for all encodings
Assembler symbols
Overflow
Operation for all encodings
F5.1.176 SEL
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.177 SETEND
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.178 SEV
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.179 SEVL
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.180 SHADD16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.181 SHADD8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.182 SHASX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.183 SHSAX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.184 SHSUB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.185 SHSUB8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.186 SMC
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.187 SMLABB, SMLABT, SMLATB, SMLATT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.188 SMLAD, SMLADX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.189 SMLAL, SMLALS
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.190 SMLALBB, SMLALBT, SMLALTB, SMLALTT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.191 SMLALD, SMLALDX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.192 SMLAWB, SMLAWT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.193 SMLSD, SMLSDX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.194 SMLSLD, SMLSLDX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.195 SMMLA, SMMLAR
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.196 SMMLS, SMMLSR
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.197 SMMUL, SMMULR
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.198 SMUAD, SMUADX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.199 SMULBB, SMULBT, SMULTB, SMULTT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.200 SMULL, SMULLS
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.201 SMULWB, SMULWT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.202 SMUSD, SMUSDX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.203 SRS, SRSDA, SRSDB, SRSIA, SRSIB
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.204 SSAT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.205 SSAT16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.206 SSAX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.207 SSUB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.208 SSUB8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.209 STC, STC2
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.210 STL
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.211 STLB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.212 STLEX
A1
T1
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation for all encodings
F5.1.213 STLEXB
A1
T1
Notes for all encodings
Assembler symbols
Aborts
Operation for all encodings
F5.1.214 STLEXD
A1
T1
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation for all encodings
F5.1.215 STLEXH
A1
T1
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation for all encodings
F5.1.216 STLH
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.217 STM, STMIA, STMEA
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.218 STM (User registers)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.219 STMDA, STMED
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.220 STMDB, STMFD
A1
T1
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F5.1.221 STMIB, STMFA
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.222 STR (immediate)
A1
T1
T2
T3
T4
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F5.1.223 STR (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.224 STRB (immediate)
A1
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.225 STRB (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.226 STRBT
A1
A2
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.227 STRD (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.228 STRD (register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.229 STREX
A1
T1
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation for all encodings
F5.1.230 STREXB
A1
T1
Notes for all encodings
Assembler symbols
Aborts
Operation for all encodings
F5.1.231 STREXD
A1
T1
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation for all encodings
F5.1.232 STREXH
A1
T1
Notes for all encodings
Assembler symbols
Aborts and alignment
Operation for all encodings
F5.1.233 STRH (immediate)
A1
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.234 STRH (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.235 STRHT
A1
A2
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.236 STRT
A1
A2
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.237 SUB (immediate, from PC)
A2
T2
Assembler symbols
Operation for all encodings
F5.1.238 SUB, SUBS (immediate)
A1
T1
T2
T3
T4
T5
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.239 SUB, SUBS (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.240 SUB, SUBS (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.241 SUB, SUBS (SP minus immediate)
A1
T1
T2
T3
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.242 SUB, SUBS (SP minus register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.243 SVC
A1
T1
Assembler symbols
Operation for all encodings
F5.1.244 SXTAB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.245 SXTAB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.246 SXTAH
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.247 SXTB
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.248 SXTB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.249 SXTH
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.250 TBB, TBH
T1
Notes for all encodings
Assembler symbols
Operation
F5.1.251 TEQ (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.252 TEQ (register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.253 TEQ (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.254 TST (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.255 TST (register)
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.256 TST (register-shifted register)
A1
Notes for all encodings
Assembler symbols
Operation
F5.1.257 UADD16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.258 UADD8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.259 UASX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.260 UBFX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.261 UDF
A1
T1
T2
Assembler symbols
Operation for all encodings
F5.1.262 UDIV
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.263 UHADD16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.264 UHADD8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.265 UHASX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.266 UHSAX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.267 UHSUB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.268 UHSUB8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.269 UMAAL
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.270 UMLAL, UMLALS
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.271 UMULL, UMULLS
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.272 UQADD16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.273 UQADD8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.274 UQASX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.275 UQSAX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.276 UQSUB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.277 UQSUB8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.278 USAD8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.279 USADA8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.280 USAT
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.281 USAT16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.282 USAX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.283 USUB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.284 USUB8
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.285 UXTAB
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.286 UXTAB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.287 UXTAH
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.288 UXTB
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.289 UXTB16
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.290 UXTH
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.291 WFE
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.292 WFI
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.1.293 YIELD
A1
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F5.2 Encoding and use of Banked register transfer instructions
F5.2.1 Register arguments in the Banked register transfer instructions
F5.2.2 Usage restrictions on the Banked register transfer instructions
F5.2.3 Encoding the register argument in the Banked register transfer instructions
F5.2.4 Pseudocode support for the Banked register transfer instructions
F6: T32 and A32 Advanced SIMD and floating-point Instruction Descriptions
F6.1 Alphabetical list of floating-point and Advanced SIMD instructions
F6.1.1 AESD
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.2 AESE
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.3 AESIMC
A1
T1
Assembler symbols
Operation for all encodings
F6.1.4 AESMC
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.5 FLDMDBX, FLDMIAX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.6 FSTMDBX, FSTMIAX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.7 SHA1C
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.8 SHA1H
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.9 SHA1M
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.10 SHA1P
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.11 SHA1SU0
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.12 SHA1SU1
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.13 SHA256H
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.14 SHA256H2
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.15 SHA256SU0
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.16 SHA256SU1
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.17 VABA
A1
T1
Assembler symbols
Operation for all encodings
F6.1.18 VABAL
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.19 VABD (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.20 VABD (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.21 VABDL (integer)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.22 VABS
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.23 VACGE
A1
T1
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.24 VACLE
A1
T1
Assembler symbols
Operation for all encodings
F6.1.25 VACGT
A1
T1
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.26 VACLT
A1
T1
Assembler symbols
Operation for all encodings
F6.1.27 VADD (floating-point)
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.28 VADD (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.29 VADDHN
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.30 VADDL
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.31 VADDW
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.32 VAND (immediate)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.33 VAND (register)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.34 VBIC (immediate)
A1
T1
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.35 VBIC (register)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.36 VBIF
A1
T1
Assembler symbols
Operation for all encodings
F6.1.37 VBIT
A1
T1
Assembler symbols
Operation for all encodings
F6.1.38 VBSL
A1
T1
Assembler symbols
Operation for all encodings
F6.1.39 VCEQ (immediate #0)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.40 VCEQ (register)
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.41 VCGE (immediate #0)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.42 VCGE (register)
A1
A2
T1
T2
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.43 VCGT (immediate #0)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.44 VCGT (register)
A1
A2
T1
T2
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.45 VCLE (immediate #0)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.46 VCLE (register)
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.47 VCLS
A1
T1
Assembler symbols
Operation for all encodings
F6.1.48 VCLT (immediate #0)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.49 VCLT (register)
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.50 VCLZ
A1
T1
Assembler symbols
Operation for all encodings
F6.1.51 VCMP
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
NaNs
Operation for all encodings
F6.1.52 VCMPE
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
NaNs
Operation for all encodings
F6.1.53 VCNT
A1
T1
Assembler symbols
Operation for all encodings
F6.1.54 VCVT (between double-precision and single-precision)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.55 VCVT (between half-precision and single-precision, Advanced SIMD)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.56 VCVT (between floating-point and integer, Advanced SIMD)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.57 VCVT (floating-point to integer, floating-point)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.58 VCVT (integer to floating-point, floating-point)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.59 VCVT (between floating-point and fixed-point, Advanced SIMD)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.60 VCVT (between floating-point and fixed-point, floating-point)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.61 VCVTA (Advanced SIMD)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.62 VCVTA (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.63 VCVTB
A1
T1
Assembler symbols
Operation for all encodings
F6.1.64 VCVTM (Advanced SIMD)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.65 VCVTM (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.66 VCVTN (Advanced SIMD)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.67 VCVTN (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.68 VCVTP (Advanced SIMD)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.69 VCVTP (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.70 VCVTR
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.71 VCVTT
A1
T1
Assembler symbols
Operation for all encodings
F6.1.72 VDIV
A1
T1
Assembler symbols
Operation for all encodings
F6.1.73 VDUP (general-purpose register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.74 VDUP (scalar)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.75 VEOR
A1
T1
Assembler symbols
Operation for all encodings
F6.1.76 VEXT (byte elements)
A1
T1
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.77 VEXT (multibyte elements)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.78 VFMA
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.79 VFMS
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.80 VFNMA
A1
T1
Assembler symbols
Operation for all encodings
F6.1.81 VFNMS
A1
T1
Assembler symbols
Operation for all encodings
F6.1.82 VHADD
A1
T1
Assembler symbols
Operation for all encodings
F6.1.83 VHSUB
A1
T1
Assembler symbols
Operation for all encodings
F6.1.84 VLD1 (single element to one lane)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.85 VLD1 (single element to all lanes)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.86 VLD1 (multiple single elements)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.87 VLD2 (single 2-element structure to one lane)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.88 VLD2 (single 2-element structure to all lanes)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.89 VLD2 (multiple 2-element structures)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.90 VLD3 (single 3-element structure to one lane)
A1
T1
Notes for all encodings
Assembler symbols
Alignment
Operation for all encodings
F6.1.91 VLD3 (single 3-element structure to all lanes)
A1
T1
Notes for all encodings
Assembler symbols
Alignment
Operation for all encodings
F6.1.92 VLD3 (multiple 3-element structures)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.93 VLD4 (single 4-element structure to one lane)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.94 VLD4 (single 4-element structure to all lanes)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.95 VLD4 (multiple 4-element structures)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.96 VLDM, VLDMDB, VLDMIA
A1
A2
T1
T2
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.97 VLDR
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.98 VMAX (floating-point)
A1
T1
Assembler symbols
Floating-point maximum and minimum
Operation for all encodings
F6.1.99 VMAX (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.100 VMAXNM
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.101 VMIN (floating-point)
A1
T1
Assembler symbols
Floating-point maximum and minimum
Operation for all encodings
F6.1.102 VMIN (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.103 VMINNM
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.104 VMLA (floating-point)
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.105 VMLA (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.106 VMLA (by scalar)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.107 VMLAL (integer)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.108 VMLAL (by scalar)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.109 VMLS (floating-point)
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.110 VMLS (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.111 VMLS (by scalar)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.112 VMLSL (integer)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.113 VMLSL (by scalar)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.114 VMOV (between two general-purpose registers and a doubleword floating-point register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.115 VMOV (immediate)
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.116 VMOV (register)
A2
T2
Assembler symbols
Operation for all encodings
F6.1.117 VMOV (register, SIMD)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.118 VMOV (general-purpose register to scalar)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.119 VMOV (between general-purpose register and single-precision register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.120 VMOV (scalar to general-purpose register)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.121 VMOV (between two general-purpose registers and two single-precision registers)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.122 VMOVL
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.123 VMOVN
A1
T1
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.124 VMRS
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.125 VMSR
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.126 VMUL (floating-point)
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.127 VMUL (integer and polynomial)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.128 VMUL (by scalar)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.129 VMULL (integer and polynomial)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.130 VMULL (by scalar)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.131 VMVN (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.132 VMVN (register)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.133 VNEG
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.134 VNMLA
A1
T1
Assembler symbols
Operation for all encodings
F6.1.135 VNMLS
A1
T1
Assembler symbols
Operation for all encodings
F6.1.136 VNMUL
A1
T1
Assembler symbols
Operation for all encodings
F6.1.137 VORN (immediate)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.138 VORN (register)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.139 VORR (immediate)
A1
T1
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.140 VORR (register)
A1
T1
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.141 VPADAL
A1
T1
Assembler symbols
Operation for all encodings
F6.1.142 VPADD (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.143 VPADD (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.144 VPADDL
A1
T1
Assembler symbols
Operation for all encodings
F6.1.145 VPMAX (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.146 VPMAX (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.147 VPMIN (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.148 VPMIN (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.149 VPOP
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.150 VPUSH
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.151 VQABS
A1
T1
Assembler symbols
Operation for all encodings
F6.1.152 VQADD
A1
T1
Assembler symbols
Operation for all encodings
F6.1.153 VQDMLAL
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.154 VQDMLSL
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.155 VQDMULH
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.156 VQDMULL
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.157 VQMOVN, VQMOVUN
A1
T1
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.158 VQNEG
A1
T1
Assembler symbols
Operation for all encodings
F6.1.159 VQRDMULH
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.160 VQRSHL
A1
T1
Assembler symbols
Operation for all encodings
F6.1.161 VQRSHRN (zero)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.162 VQRSHRN, VQRSHRUN
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.163 VQRSHRUN (zero)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.164 VQSHL, VQSHLU (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.165 VQSHL (register)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.166 VQSHRN (zero)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.167 VQSHRN, VQSHRUN
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.168 VQSHRUN (zero)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.169 VQSUB
A1
T1
Assembler symbols
Operation for all encodings
F6.1.170 VRADDHN
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.171 VRECPE
A1
T1
Assembler symbols
Newton-Raphson iteration
Operation for all encodings
F6.1.172 VRECPS
A1
T1
Assembler symbols
Newton-Raphson iteration
Operation for all encodings
F6.1.173 VREV16
A1
T1
Assembler symbols
Operation for all encodings
F6.1.174 VREV32
A1
T1
Assembler symbols
Operation for all encodings
F6.1.175 VREV64
A1
T1
Assembler symbols
Operation for all encodings
F6.1.176 VRHADD
A1
T1
Assembler symbols
Operation for all encodings
F6.1.177 VRINTA (Advanced SIMD)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.178 VRINTA (floating-point)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.179 VRINTM (Advanced SIMD)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.180 VRINTM (floating-point)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.181 VRINTN (Advanced SIMD)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.182 VRINTN (floating-point)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.183 VRINTP (Advanced SIMD)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.184 VRINTP (floating-point)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.185 VRINTR
A1
T1
Assembler symbols
Operation for all encodings
F6.1.186 VRINTX (Advanced SIMD)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.187 VRINTX (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.188 VRINTZ (Advanced SIMD)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.189 VRINTZ (floating-point)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.190 VRSHL
A1
T1
Assembler symbols
Operation for all encodings
F6.1.191 VRSHR
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.192 VRSHR (zero)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.193 VRSHRN
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.194 VRSHRN (zero)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.195 VRSQRTE
A1
T1
Assembler symbols
Newton-Raphson iteration
Operation for all encodings
F6.1.196 VRSQRTS
A1
T1
Assembler symbols
Newton-Raphson iteration
Operation for all encodings
F6.1.197 VRSRA
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.198 VRSUBHN
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.199 VSELEQ, VSELGE, VSELGT, VSELVS
A1
T1
Assembler symbols
Operation for all encodings
F6.1.200 VSHL (immediate)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.201 VSHL (register)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.202 VSHLL
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.203 VSHR
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.204 VSHR (zero)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.205 VSHRN
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.206 VSHRN (zero)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.207 VSLI
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.208 VSQRT
A1
T1
Assembler symbols
Operation for all encodings
F6.1.209 VSRA
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.210 VSRI
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.211 VST1 (single element from one lane)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.212 VST1 (multiple single elements)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.213 VST2 (single 2-element structure from one lane)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.214 VST2 (multiple 2-element structures)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.215 VST3 (single 3-element structure from one lane)
A1
T1
Notes for all encodings
Assembler symbols
Alignment
Operation for all encodings
F6.1.216 VST3 (multiple 3-element structures)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.217 VST4 (single 4-element structure from one lane)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.218 VST4 (multiple 4-element structures)
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.219 VSTM, VSTMDB, VSTMIA
A1
A2
T1
T2
Notes for all encodings
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.220 VSTR
A1
A2
T1
T2
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.221 VSUB (floating-point)
A1
A2
T1
T2
Assembler symbols
Operation for all encodings
F6.1.222 VSUB (integer)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.223 VSUBHN
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.224 VSUBL
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.225 VSUBW
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.226 VSWP
A1
T1
Assembler symbols
Operation for all encodings
F6.1.227 VTBL, VTBX
A1
T1
Notes for all encodings
Assembler symbols
Operation for all encodings
F6.1.228 VTRN
A1
T1
Alias conditions
Assembler symbols
Operation for all encodings
F6.1.229 VTST
A1
T1
Assembler symbols
Operation for all encodings
F6.1.230 VUZP
A1
T1
Assembler symbols
Operation for all encodings
F6.1.231 VUZP (alias)
A1
T1
Assembler symbols
Operation for all encodings
F6.1.232 VZIP
A1
T1
Assembler symbols
Operation for all encodings
F6.1.233 VZIP (alias)
A1
T1
Assembler symbols
Operation for all encodings
Part G: The AArch32 System Level Architecture
G1: The AArch32 System Level Programmers’ Model
G1.1 About the AArch32 System level programmers’ model
G1.2 Exception levels
G1.2.1 Typical Exception level usage model
G1.3 Exception terminology
G1.3.1 Terminology for taking an exception
G1.3.2 Terminology for returning from an exception
G1.3.3 Exception levels
G1.3.4 Definition of a precise exception
G1.3.5 Definitions of synchronous and asynchronous exceptions
G1.4 Execution state
G1.4.1 About the AArch32 PE modes
G1.5 Instruction Set state
G1.6 Security state
G1.6.1 The ARMv8-A security model
The AArch32 security model, and execution privilege
Changing from Secure state to Non-secure state
G1.7 Virtualization
G1.7.1 The effect of implementing EL2 on the Exception model
Virtual interrupts
G1.8 AArch32 PE modes, and general-purpose and Special-purpose registers
G1.8.1 AArch32 PE mode descriptions
Notes on the AArch32 PE modes
Hyp mode
Pseudocode description of mode operations
G1.8.2 AArch32 general-purpose registers, the PC, and the Special-purpose registers
AArch32 Special-purpose registers
Pseudocode description of general-purpose register and PC operations
G1.8.3 Saved Program Status Registers (SPSRs)
SPSR format for exceptions taken to AArch32 state
Pseudocode description of SPSR operations
G1.8.4 ELR_hyp
G1.9 Process state, PSTATE
G1.9.1 Accessing PSTATE fields
The Current Program Status Register, CPSR
Accessing the PE state controls and the Execution state bit
The CPS instruction
The SETEND instruction
G1.9.2 The Saved Program Status Registers (SPSRs)
G1.9.3 Illegal changes to PSTATE.M
G1.9.4 Pseudocode description of PSTATE operations
G1.10 Instruction set states
G1.10.1 Exceptions and instruction set state
G1.10.2 Unimplemented instruction sets
Trivial implementation of the Jazelle extension
G1.11 Handling exceptions that are taken to an Exception level using AArch32
G1.11.1 Exception vectors and the exception base address
The vector tables and exception offsets
G1.11.2 Exception prioritization for exceptions taken to AArch32 state
Synchronous exception prioritization for exceptions taken to AArch32 state
Architectural requirements for taking asynchronous exceptions
G1.11.3 Overview of exception entry
Link values saved on exception entry
G1.11.4 PE mode for taking exceptions
Exceptions taken to Hyp mode
Security behavior in Exception levels using AArch32 when EL3 is using AArch64
The possible modes for taking each exception
G1.11.5 PE state on exception entry
Instruction set state on exception entry
PSTATE.E value on exception entry
PSTATE.{A, I, F, M} values on exception entry
G1.11.6 Routing exceptions from Non-secure EL0 to EL2
Exception reporting when HCR.TGE routes an exception to EL2 using AArch32
Exception reporting when HCR_EL2.TGE routes an exception to EL2 using AArch64
G1.11.7 Routing debug exceptions to EL2
G1.12 Exception return to an Exception level using AArch32
G1.12.1 Exception return instructions
Return from an exception taken to a PE mode other than Hyp mode
Return from an exception taken to Hyp mode
G1.12.2 Alignment of exception returns
G1.12.3 Illegal return events from AArch32 state
G1.12.4 Legal returns that set PSTATE.IL to 1
G1.12.5 The Illegal Execution state exception
Pseudocode description of exception return
G1.13 Asynchronous exception behavior for exceptions taken from AArch32 state
G1.13.1 Virtual exceptions when an implementation includes EL2
Effects of the HCR.{AMO, IMO, FMO} bits
G1.13.2 Asynchronous exception routing controls
G1.13.3 Asynchronous exception masking controls
Asynchronous exception masking in an implementation that includes EL2 but not EL3
Asynchronous exception masking in an implementation that includes EL3 but not EL2
Asynchronous exception masking in an implementation that includes both EL2 and EL3
Summary of the asynchronous exception masking controls
G1.13.4 Asynchronous exception routing and masking with higher Exception levels using AArch64
Summary of physical interrupt routing
Summary of physical interrupt masking
G1.14 AArch32 state exception descriptions
G1.14.1 Undefined Instruction exception
The PE mode to which the Undefined Instruction exception is taken
Pseudocode description of taking the Undefined Instruction exception
Conditional execution of undefined instructions
Interaction of UNDEFINED instruction behavior with UNPREDICTABLE or CONSTRAINED UNPREDICTABLE instruction behavior
G1.14.2 Monitor Trap exception
The PE mode to which the Monitor Trap exception is taken
Pseudocode description of taking the Monitor Trap exception
G1.14.3 Hyp Trap exception
The PE mode to which the Hyp Trap exception is taken
Pseudocode description of taking the Hyp Trap exception
G1.14.4 Supervisor Call (SVC) exception
The PE mode to which the Supervisor Call exception is taken
Pseudocode description of taking the Supervisor Call exception
G1.14.5 Secure Monitor Call (SMC) exception
The PE mode to which the Secure Monitor Call exception is taken
Pseudocode description of taking the Secure Monitor Call exception
G1.14.6 Hypervisor Call (HVC) exception
The PE mode to which the Hypervisor Call exception is taken
Pseudocode description of taking the Hypervisor Call exception
G1.14.7 Prefetch Abort exception
Prefetch Abort exception reporting a Misaligned PC exception
The PE mode to which the Prefetch Abort exception is taken
Pseudocode description of taking the Prefetch Abort exception
G1.14.8 Data Abort exception
The PE mode to which the Data Abort exception is taken
Pseudocode description of taking the Data Abort exception
Effects of data-aborted instructions
The ARM abort model
G1.14.9 Virtual Abort exception
The PE mode to which the Virtual Abort exception is taken
Pseudocode description of taking the Virtual Asynchronous Abort exception
G1.14.10 IRQ exception
The PE mode to which the physical IRQ exception is taken
Pseudocode description of taking the IRQ exception
G1.14.11 Virtual IRQ exception
The PE mode to which the Virtual IRQ exception is taken
Pseudocode description of taking the Virtual IRQ exception
G1.14.12 FIQ exception
The PE mode to which the physical FIQ exception is taken
Pseudocode description of taking the FIQ exception
G1.14.13 Virtual FIQ exception
The PE mode to which the Virtual FIQ exception is taken
Pseudocode description of taking the Virtual FIQ exception
G1.14.14 Additional pseudocode functions for exception handling
G1.15 Reset into AArch32 state
G1.15.1 PE state on reset into AArch32 state
G1.15.2 Pseudocode descriptions of reset
G1.16 Mechanisms for entering a low-power state
G1.16.1 Wait For Event and Send Event
The Event Register
The Wait For Event instruction
WFE wake-up events
The Send Event instructions
Pseudocode description of the Wait For Event mechanism
G1.16.2 Wait For Interrupt
WFI wake-up events
Using WFI to indicate an idle state on bus interfaces
Pseudocode description of Wait For Interrupt
G1.17 The conceptual coprocessor interface and system control
G1.17.1 System registers in the CP14 and CP15 encoding spaces
Access to CP14 and CP15 registers
G1.17.2 Access controls on CP10 and CP11
G1.17.3 Pseudocode description of checking accesses to the conceptual coprocessors CP14 and CP15
G1.18 Advanced SIMD and floating-point support
G1.18.1 AArch32 implications of not including support for Advanced SIMD and floating-point
G1.18.2 Enabling Advanced SIMD and floating-point support
FPEXC control of access to Advanced SIMD and floating-point functionality
EL0 access to Advanced SIMD and floating-point functionality
G1.18.3 Advanced SIMD and floating-point System registers
Register map of the Advanced SIMD and floating-point System registers
Accessing the Advanced SIMD and floating-point System registers
G1.18.4 Context switching when using Advanced SIMD and floating-point functionality
G1.18.5 Floating-point exception traps
G1.19 Configurable instruction enables and disables, and trap controls
G1.19.1 Register access instructions
G1.19.2 PL1 configurable controls
Instructions that fail their condition code check
Trapping to PL1 of instructions that are UNPREDICTABLE
Traps to Undefined mode of EL0 execution of WFE and WFI instructions
Disabling or enabling PL0 and PL1 use of AArch32 deprecated functionality
Traps to Undefined mode of PL0 and PL1 System register accesses to trace registers
Enabling use of Advanced SIMD and floating-point functionality
Traps to Undefined mode of EL0 accesses to the Debug Communications Channel (DCC) registers
Traps to Undefined mode of EL0 accesses to the Generic Timer registers
Traps to Undefined mode of EL0 accesses to Performance Monitors registers
G1.19.3 EL2 configurable controls
Instructions that fail their condition code check
Trapping to EL2 of instructions that are UNPREDICTABLE
Disabling or enabling EL2 use of AArch32 deprecated functionality
Traps to Hyp mode of Non-secure EL1 accesses to virtual memory control registers
Disabling Non-secure state execution of HVC instructions
Traps to Hyp mode of Non-secure EL1 execution of TLB maintenance instructions
Traps to Hyp mode of Non-secure EL1 execution of cache maintenance instructions
Traps to Hyp mode of Non-secure EL1 accesses to the Auxiliary Control Register
Traps to Hyp mode of Non-secure EL0 and EL1 accesses to lockdown, DMA, and TCM operations
Traps to Hyp mode of Non-secure EL1 execution of SMC instructions
Traps to Hyp mode of Non-secure EL0 and EL1 accesses to the ID registers
Traps to Hyp mode of Non-secure EL0 and EL1 execution of WFE and WFI instructions
General trapping to Hyp mode of Non-secure accesses to the SIMD and floating-point registers
Enabling access to the SIMD and floating-point registers
Traps to Hyp mode of Non-secure accesses to Advanced SIMD functionality
Traps to Hyp mode of Non-secure EL1 accesses to the CPACR
Traps to Hyp mode of Non-secure System register accesses to trace registers
General trapping to Hyp mode of Non-secure EL0 and EL1 accesses to CP15 System registers
Traps to Hyp mode of Non-secure System register accesses to debug registers
Traps to Hyp mode of Non-secure EL0 and EL1 accesses to the Generic Timer registers
Traps to Hyp mode of Non-secure EL0 and EL1 accesses to Performance Monitors registers
G1.19.4 EL3 configurable controls
Instructions that fail their condition code check
Trapping to EL3 of instructions that are UNPREDICTABLE
Traps to Monitor mode of the execution of WFE and WFI instructions in modes other than Monitor mode
Enabling EL2 and Non-secure EL1 execution of HVC instructions
Disabling SMC instructions
Disabling Non-secure System register access to the trace registers
Enabling Non-secure access to SIMD and floating-point functionality
Disabling Non-secure access to Advanced SIMD functionality
G1.19.5 Pseudocode description of configurable instruction enables, disables, and traps
Pseudocode description of enabling SIMD and floating-point functionality
G2: AArch32 Self-hosted Debug
G2.1 About debug exceptions
G2.2 The debug exception enable controls
G2.3 Routing debug exceptions
G2.3.1 Pseudocode description of routing debug exceptions
G2.4 Enabling debug exceptions from the current Privilege level and Security state
G2.4.1 Disabling debug exceptions from Secure state
G2.4.2 Pseudocode description of enabling debug exceptions
G2.5 The effect of powerdown on debug exceptions
G2.6 Summary of permitted routing and enabling of debug exceptions
G2.7 Pseudocode description of debug exceptions
G2.8 Software Breakpoint Instruction exceptions
G2.8.1 About Software Breakpoint Instruction exceptions
G2.8.2 Breakpoint instruction in the A32 and T32 instruction sets
About whether the BKPT instruction is conditional
G2.8.3 BKPT instructions as the first instruction in an IT block
G2.8.4 Exception syndrome information and preferred return address
Exception syndrome information
Preferred return address
G2.8.5 Pseudocode description of Software Breakpoint Instruction exceptions
G2.9 Breakpoint exceptions
G2.9.1 About Breakpoint exceptions
G2.9.2 Breakpoint types and linking of breakpoints
Rules for linking breakpoints
Breakpoint types defined by DBGBCRn.BT
G2.9.3 Execution conditions for which a breakpoint generates Breakpoint exceptions
G2.9.4 Breakpoint instruction address comparisons
Address Match breakpoints
Address Mismatch breakpoints
Specifying the halfword-aligned address that an Address breakpoint matches on
G2.9.5 Context comparisons
G2.9.6 Using breakpoints
Using an Address Mismatch breakpoint to single-step an instruction
ITD control effects on address breakpoints on the first instruction in an IT block
Usage constraints
G2.9.7 Exception syndrome information and preferred return address
Exception syndrome information
Preferred return address
G2.9.8 Pseudocode description of Breakpoint exceptions taken from AArch32 state
G2.10 Watchpoint exceptions
G2.10.1 About Watchpoint exceptions
G2.10.2 Watchpoint types and linking of watchpoints
Rules for linking watchpoints
G2.10.3 Execution conditions for which a watchpoint generates Watchpoint exceptions
G2.10.4 Watchpoint data address comparisons
Size of the data access
Programming a watchpoint with eight bytes or fewer
Programming a watchpoint with eight or more bytes
G2.10.5 Determining the memory location that caused a Watchpoint exception
Address recorded for Watchpoint exceptions generated by instructions other than Data Cache instructions
Address recorded for Watchpoint exceptions generated by Data Cache instructions
G2.10.6 Watchpoint behavior on other instructions
Watchpoint behavior on accesses by Store-Exclusive instructions
Watchpoint behavior on accesses by DCIMVAC instructions
G2.10.7 Usage constraints
Reserved DBGWCR.{HMC, SSC, PAC} values
Reserved DBGWCR.LBN values
Programming dependencies of the BAS and MASK fields
Reserved DBGWCR.BAS values
Reserved DBGWCR.MASK values
Other usage constraints
G2.10.8 Exception syndrome information and preferred return address
Exception syndrome information
Preferred return address
G2.10.9 Pseudocode description of Watchpoint exceptions taken from AArch32 state
G2.11 Vector Catch exceptions
G2.11.1 About Vector Catch exceptions
G2.11.2 Exception vectors that Vector Catch exceptions can be enabled for
G2.11.3 Generation of Vector Catch exceptions
Address-matching form
Exception-trapping form
G2.11.4 Usage constraints
Usage constraints that apply to both forms of vector catch
Usage constraints that apply only to the address-matching form
G2.11.5 Exception syndrome information and preferred return address
Exception syndrome information
Preferred return address
G2.11.6 Pseudocode description of Vector Catch exceptions
G2.12 Synchronization and debug exceptions
G2.12.1 State and mode changes without explicit context synchronization operations
G3: The AArch32 System Level Memory Model
G3.1 About the memory system architecture
G3.1.1 Form of the memory system architecture
G3.1.2 Memory attributes
G3.2 Address space
G3.2.1 Address space overflow or underflow
Instruction address space overflow
Data address space overflow and underflow
G3.3 Mixed-endian support
G3.4 AArch32 cache and branch predictor support
G3.4.1 General behavior of the caches
G3.4.2 Cache identification
G3.4.3 Cacheability, cache allocation hints, and cache transient hints
G3.4.4 Behavior of caches at reset
G3.4.5 Cache enabling and disabling in AArch32 state
G3.4.6 The ARMv8 cache maintenance functionality
Terms used in describing the maintenance instructions
The ARMv8 abstraction of the cache hierarchy
G3.4.7 AArch32 cache and branch predictor maintenance instructions
AArch32 instruction cache maintenance instructions (IC*)
AArch32 data cache maintenance instructions (DC*)
Branch predictors
General requirements for the scope of cache and branch predictor maintenance instructions
Effects of instructions that operate by virtual address to the Point of Coherency
Effects of instructions that operate by virtual address but not to the Point of Coherency
Effects of All and set/way maintenance instructions
Effects of virtualization and security on the AArch32 cache maintenance instructions
Boundary conditions for cache maintenance instructions
Ordering of cache and branch predictor maintenance instructions
Performing cache maintenance instructions
G3.4.8 Cache lockdown
The interaction of cache lockdown with cache maintenance instructions
G3.4.9 System level caches
G3.5 System register support for IMPLEMENTATION DEFINED memory features
G3.6 External aborts
G3.6.1 External abort on instruction fetch
G3.6.2 External abort on data read or write
G3.6.3 Provision for classification of external aborts
G3.6.4 Parity or ECC error reporting
G3.7 Memory barrier instructions
G3.7.1 EL2 control of the Shareability of data barrier instructions executed at EL0 or EL1
G3.8 Pseudocode description of general memory system instructions
G3.8.1 Memory data type definitions
G3.8.2 Basic memory access
G3.8.3 Aligned memory access
G3.8.4 Unaligned memory access
G3.8.5 Exclusive monitors operations
G3.8.6 Access permission checking
G3.8.7 Abort exceptions
G3.8.8 Memory barriers
G4: The AArch32 Virtual Memory System Architecture
G4.1 Execution privilege, Exception levels, and AArch32 Privilege levels
G4.2 About VMSAv8-32
G4.2.1 Address types used in a VMSAv8-32 description
G4.2.2 Address spaces in VMSAv8-32
G4.2.3 About address translation for VMSAv8-32
Atomicity of register changes on changing virtual machine
Use of out-of-context translation regimes
G4.2.4 Organization of this chapter
G4.3 The effects of disabling address translation stages on VMSAv8-32 behavior
G4.3.1 VMSAv8-32 behavior when stage 1 address translation is disabled
Effect of the HCR.DC bit
Effect of disabling translation on maintenance and address translation instructions
G4.3.2 VMSAv8-32 behavior when stage 2 address translation is disabled
G4.3.3 Behavior of instruction fetches when all associated address translations are disabled
G4.3.4 Enabling stages of address translation
G4.4 Translation tables
G4.4.1 Translation table walks for memory accesses using VMSAv8-32 translation regimes
G4.4.2 Information returned by a translation table lookup
G4.4.3 Determining the translation table base address in the VMSAv8-32 translation regimes
G4.4.4 Control of translation table walks on a TLB miss
G4.4.5 Access to the Secure or Non-secure physical address map
Secure and Non-secure address spaces
G4.5 The VMSAv8-32 Short-descriptor translation table format
G4.5.1 VMSAv8-32 Short-descriptor translation table format descriptors
Short-descriptor translation table level 1 descriptor formats
Short-descriptor translation table level 2 descriptor formats
Additional requirements for Short-descriptor format translation tables
G4.5.2 Memory attributes in the VMSAv8-32 Short-descriptor translation table format descriptors
G4.5.3 Control of Secure or Non-secure memory access, VMSAv8-32 Short-descriptor format
G4.5.4 Selecting between TTBR0 and TTBR1, VMSAv8-32 Short-descriptor translation table format
G4.5.5 Translation table walks, when using the VMSAv8-32 Short-descriptor translation table format
Reading a level 1 translation table
The full translation flow for Sections, Supersections, Small pages and Large pages
G4.6 The VMSAv8-32 Long-descriptor translation table format
G4.6.1 Overview of VMSAv8-32 address translation using Long-descriptor translation tables
G4.6.2 VMSAv8-32 Long-descriptor translation table format descriptors
VMSAv8-32 Long-descriptor level 1 and level 2 descriptor formats
VMSAv8-32 Long-descriptor translation table level 3 descriptor formats
G4.6.3 Memory attributes in the VMSAv8-32 Long-descriptor translation table format descriptors
Next-level attributes in VMSAv8-32 Long-descriptor stage 1 Table descriptors
Attribute fields in VMSAv8-32 Long-descriptor stage 1 Block and Page descriptors
Attribute fields in VMSAv8-32 Long-descriptor stage 2 Block and Page descriptors
G4.6.4 Control of Secure or Non-secure memory access, VMSAv8-32 Long-descriptor format
Hierarchical control of Secure or Non-secure memory accesses, Long-descriptor format
G4.6.5 Selecting between TTBR0 and TTBR1, VMSAv8-32 Long-descriptor translation table format
Possible translation table registers programming errors
G4.6.6 VMSAv8-32 Long-descriptor translation table format address lookup levels
Use of concatenated translation tables for stage 2 translations
G4.6.7 Translation table walks, when using the VMSAv8-32 Long-descriptor translation table format
Determining the required initial lookup level for stage 1 translations
Determining the required initial lookup level for stage 2 translations
G4.6.8 The algorithm for finding the translation table entries, VMSAv8-32 Long-descriptor format
G4.7 Memory access control
G4.7.1 Access permissions
AP[2:1] access permissions model
AP[2:0] access permissions control, Short-descriptor format only
G4.7.2 Execute-never restrictions on instruction fetching
Hierarchical control of instruction fetching, Long-descriptor format
Restriction on Secure instruction fetch
Preventing execution from writable locations
G4.7.3 Domains, Short-descriptor format only
G4.7.4 The Access flag
Software management of the Access flag
G4.7.5 Hyp mode control of Non-secure access permissions
G4.8 Memory region attributes
G4.8.1 Overview of memory region attributes for stage 1 translations
G4.8.2 Short-descriptor format memory region attributes, without TEX remap
Cacheable memory attributes, without TEX remap
Shareability and the S bit, without TEX remap
G4.8.3 Short-descriptor format memory region attributes, with TEX remap
Determining the Shareability, with TEX remap
SCTLR.TRE, SCTLR.M, and the effect of the TEX remap registers
The OS managed translation table bits
The effect of EL3 on TEX remap
G4.8.4 VMSAv8-32 Long-descriptor format memory region attributes
Shareability, Long-descriptor format
Other fields in the Long-descriptor translation table format descriptors
G4.8.5 EL2 control of Non-secure memory region attributes
Combining the memory type attribute
Combining the Cacheability attribute
Combining the Shareability attribute
G4.9 Translation Lookaside Buffers (TLBs)
G4.9.1 Global and process-specific translation table entries
G4.9.2 TLB matching
G4.9.3 TLB behavior at reset
G4.9.4 TLB lockdown
G4.9.5 TLB conflict aborts
G4.10 TLB maintenance requirements
G4.10.1 General TLB maintenance requirements
Using break-before-make when updating translation table entries
The interaction of TLB lockdown with TLB maintenance instructions
Ordering and completion of TLB maintenance instructions
G4.10.2 Maintenance requirements on changing System register values
Changing the Access flag enable
Changing HCR.PTW
Changing the current Translation table format
G4.10.3 Atomicity of register changes on changing virtual machine
G4.10.4 Synchronization of changes of ASID and TTBR
G4.10.5 The scope of TLB maintenance instructions
EL2 upgrading of TLB maintenance instructions
TLB maintenance with different translation granule sizes
G4.11 Caches in VMSAv8-32
G4.11.1 Data and unified caches
G4.11.2 Instruction caches
PIPT instruction caches
VIPT instruction caches
ASID and VMID tagged VIVT instruction caches
The IVIPT architecture Extension
G4.11.3 Cache maintenance requirement created by changing translation table attributes
G4.12 VMSAv8-32 memory aborts
G4.12.1 Routing of aborts taken to AArch32 state
G4.12.2 VMSAv8-32 MMU fault terminology
G4.12.3 The MMU fault-checking sequence
Stage 2 fault on a stage 1 translation table walk
G4.12.4 Alignment faults
G4.12.5 MMU faults in AArch32 state
Permission fault
Translation fault
Address size fault
Access flag fault
Domain fault, Short-descriptor format translation tables only
G4.12.6 External abort on a translation table walk
Behavior of external aborts on a translation table walk caused by address translation instructions
G4.12.7 AArch32 prioritization of synchronous aborts from a single stage of address translation
G4.13 Exception reporting in a VMSAv8-32 implementation
G4.13.1 About exception reporting
Fault address reporting on synchronous external aborts
G4.13.2 Reporting exceptions taken to PL1 modes
Registers used for reporting exceptions taken to PL1 modes
Data Abort exceptions, taken to a PL1 mode
Prefetch Abort exceptions, taken to a PL1 mode
G4.13.3 Fault reporting in PL1 modes
Reporting of External aborts taken from Non-secure state to Monitor mode
PL1 fault reporting with the Short-descriptor translation table format
PL1 fault reporting with the Long-descriptor translation table format
Reserved encodings in the IFSR and DFSR encodings tables
G4.13.4 Summary of register updates on faults taken to PL1 modes
G4.13.5 Reporting exceptions taken to Hyp mode
Registers used for reporting exceptions taken to Hyp mode
Memory fault reporting in Hyp mode
Use of the HSR
G4.13.6 Summary of register updates on exceptions taken to Hyp mode
Classification of MMU faults taken to Hyp mode
G4.14 Address translation instructions
G4.14.1 Address translation instruction naming and operation summary
ATS1Cxx, Address translation stage 1, current security state
ATS12NSOxx, Address translation stages 1 and 2, Non-secure state only
ATS1Hx, Address translation stage 1, Hyp mode
G4.14.2 Encoding and availability of the address translation instructions
G4.14.3 Determining the PAR format
G4.14.4 Handling of faults and aborts during an address translation instruction
MMU fault on an address translation instruction
External abort during an address translation instruction
Stage 2 fault on a current state address translation instruction
G4.15 About the System registers for VMSAv8-32
G4.15.1 About System register accesses
Ordering of reads of System registers
Accessing 32-bit System registers
Accessing 64-bit System registers
G4.15.2 General behavior of System registers
Read-only bits in read/write registers
UNPREDICTABLE, CONSTRAINED UNPREDICTABLE, and UNDEFINED behavior for AArch32 System register accesses
Read-only and write-only register encodings
Reset behavior of System registers
G4.15.3 Classification of System registers
Banked System registers
Restricted access System registers
Configurable access System registers
EL2-mode System registers
Common System registers
Secure CP15 registers
The CP15SDISABLE input signal
Access to registers from Monitor mode
G4.15.4 Synchronization of changes to AArch32 System registers
Registers with some architectural guarantee of ordering or observability
Definitions of direct and indirect reads and writes and their side-effects
G4.15.5 Fixed values in register diagrams
G4.15.6 Principles of the ID scheme for fields in ID registers
AArch32 ID registers to which this scheme applies
G4.16 Organization of the CP14 registers in VMSAv8-32
G4.16.1 CP14 interface instruction arguments
G4.17 Organization of the CP15 registers in VMSAv8-32
G4.17.1 CP15 32-bit register summary by coprocessor register number, CRn
VMSAv8-32 CP15 c0 register summary
VMSAv8-32 CP15 c1 register summary
VMSAv8-32 CP15 c2 and c3 register summary
VMSAv8-32 CP15 c4 register summary
VMSAv8-32 CP15 c5 and c6 register summary
VMSAv8-32 CP15 c7 register summary
VMSAv8-32 CP15 c8 register summary
VMSAv8-32 CP15 c9 register summary
VMSAv8-32 CP15 c10 register summary
VMSAv8-32 CP15 c11 register summary
VMSAv8-32 CP15 c12 register summary
VMSAv8-32 CP15 c13 register summary
VMSAv8-32 CP15 c14 register summary
VMSAv8-32 CP15 c15 register summary
G4.17.2 Full list of VMSAv8-32 CP15 registers, by coprocessor register number
G4.17.3 AArch32 views of the CP15 registers
PL0 views of the CP15 registers
PL1 views of the CP15 registers
Non-secure PL2 view of the CP15 registers
G4.18 Functional grouping of VMSAv8-32 System registers
G4.18.1 Identification registers, functional group
The CPUID identification scheme
G4.18.2 Other System registers, functional group
G4.18.3 Virtual memory control registers, functional group
G4.18.4 Virtualization registers, functional group
G4.18.5 Security registers, functional group
G4.18.6 Exception and fault handling registers, functional group
G4.18.7 Reset management registers, functional group
G4.18.8 Thread and process ID registers, functional group
G4.18.9 Cache maintenance instructions, functional group
G4.18.10 TLB maintenance instructions, functional group
G4.18.11 Address translation instructions, functional group
G4.18.12 Lockdown, DMA, and TCM features, functional group
G4.18.13 Performance Monitors Extension registers, functional group
IMPLEMENTATION DEFINED performance monitors
G4.18.14 Generic Timer registers, functional group
G4.18.15 Generic Interrupt Controller System registers, functional groups
G4.18.16 Legacy feature registers, functional group
G4.18.17 IMPLEMENTATION DEFINED registers, functional group
G4.18.18 Advanced SIMD and floating-point registers, functional group
G4.18.19 Debug registers, functional group
G4.19 Pseudocode description of VMSAv8-32 memory system operations
G4.19.1 Alignment fault
G4.19.2 Address translation
Address translation when the stage 1 address translation is disabled
G4.19.3 Domain checking
G4.19.4 TLB operations
G4.19.5 Translation table walk
Translation table walk using the Short-descriptor translation table format for stage 1
Translation table walk using the Long-descriptor translation table format for stage 1
Stage 2 translation table walk
G4.19.6 Reporting syndrome information
G4.19.7 Memory access decode when TEX remap is enabled
G5: The Generic Timer in AArch32 state
G5.1 About the Generic Timer in AArch32 state
G5.1.1 The full set of Generic Timer components
G5.1.2 The system counter
Initializing and reading the system counter frequency
Memory-mapped controls of the system counter
G5.2 The AArch32 view of the Generic Timer
G5.2.1 The physical counter
Accessing the physical counter
G5.2.2 The virtual counter
Accessing the virtual counter
Status of the CNTVOFF register
G5.2.3 Event streams
G5.2.4 Timers
Accessing the timer registers
Operation of the CompareValue views of the timers
Operation of the TimerValue views of the timers
G6: AArch32 System Register Descriptions
G6.1 About the AArch32 System registers
G6.2 General system control registers
G6.2.1 ACTLR, Auxiliary Control Register
Field descriptions
Accessing the ACTLR:
G6.2.2 ACTLR2, Auxiliary Control Register 2
Field descriptions
Accessing the ACTLR2:
G6.2.3 ADFSR, Auxiliary Data Fault Status Register
Field descriptions
Accessing the ADFSR:
G6.2.4 AIDR, Auxiliary ID Register
Field descriptions
Accessing the AIDR:
G6.2.5 AIFSR, Auxiliary Instruction Fault Status Register
Field descriptions
Accessing the AIFSR:
G6.2.6 AMAIR0, Auxiliary Memory Attribute Indirection Register 0
Field descriptions
Accessing the AMAIR0:
G6.2.7 AMAIR1, Auxiliary Memory Attribute Indirection Register 1
Field descriptions
Accessing the AMAIR1:
G6.2.8 APSR, Application Program Status Register
Field descriptions
G6.2.9 ATS12NSOPR, Address Translate Stages 1 and 2 Non-secure Only PL1 Read
Field descriptions
Performing the ATS12NSOPR operation:
G6.2.10 ATS12NSOPW, Address Translate Stages 1 and 2 Non-secure Only PL1 Write
Field descriptions
Performing the ATS12NSOPW operation:
G6.2.11 ATS12NSOUR, Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read
Field descriptions
Performing the ATS12NSOUR operation:
G6.2.12 ATS12NSOUW, Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write
Field descriptions
Performing the ATS12NSOUW operation:
G6.2.13 ATS1CPR, Address Translate Stage 1 Current state PL1 Read
Field descriptions
Performing the ATS1CPR operation:
G6.2.14 ATS1CPW, Address Translate Stage 1 Current state PL1 Write
Field descriptions
Performing the ATS1CPW operation:
G6.2.15 ATS1CUR, Address Translate Stage 1 Current state Unprivileged Read
Field descriptions
Performing the ATS1CUR operation:
G6.2.16 ATS1CUW, Address Translate Stage 1 Current state Unprivileged Write
Field descriptions
Performing the ATS1CUW operation:
G6.2.17 ATS1HR, Address Translate Stage 1 Hyp mode Read
Field descriptions
Performing the ATS1HR operation:
G6.2.18 ATS1HW, Address Translate Stage 1 Hyp mode Write
Field descriptions
Performing the ATS1HW operation:
G6.2.19 BPIALL, Branch Predictor Invalidate All
Field descriptions
Performing the BPIALL operation:
G6.2.20 BPIALLIS, Branch Predictor Invalidate All, Inner Shareable
Field descriptions
Performing the BPIALLIS operation:
G6.2.21 BPIMVA, Branch Predictor Invalidate by VA
Field descriptions
Performing the BPIMVA operation:
G6.2.22 CCSIDR, Current Cache Size ID Register
Field descriptions
Accessing the CCSIDR:
G6.2.23 CLIDR, Cache Level ID Register
Field descriptions
Accessing the CLIDR:
G6.2.24 CONTEXTIDR, Context ID Register
Field descriptions
Accessing the CONTEXTIDR:
G6.2.25 CP15DMB, CP15 Data Memory Barrier operation
Field descriptions
Performing the CP15DMB operation:
G6.2.26 CP15DSB, CP15 Data Synchronization Barrier operation
Field descriptions
Performing the CP15DSB operation:
G6.2.27 CP15ISB, CP15 Instruction Synchronization Barrier operation
Field descriptions
Performing the CP15ISB operation:
G6.2.28 CPACR, Architectural Feature Access Control Register
Field descriptions
Accessing the CPACR:
G6.2.29 CPSR, Current Program Status Register
Field descriptions
G6.2.30 CSSELR, Cache Size Selection Register
Field descriptions
Accessing the CSSELR:
G6.2.31 CTR, Cache Type Register
Field descriptions
Accessing the CTR:
G6.2.32 DACR, Domain Access Control Register
Field descriptions
Accessing the DACR:
G6.2.33 DCCIMVAC, Data Cache line Clean and Invalidate by VA to PoC
Field descriptions
Performing the DCCIMVAC operation:
G6.2.34 DCCISW, Data Cache line Clean and Invalidate by Set/Way
Field descriptions
Performing the DCCISW operation:
G6.2.35 DCCMVAC, Data Cache line Clean by VA to PoC
Field descriptions
Performing the DCCMVAC operation:
G6.2.36 DCCMVAU, Data Cache line Clean by VA to PoU
Field descriptions
Performing the DCCMVAU operation:
G6.2.37 DCCSW, Data Cache line Clean by Set/Way
Field descriptions
Performing the DCCSW operation:
G6.2.38 DCIMVAC, Data Cache line Invalidate by VA to PoC
Field descriptions
Performing the DCIMVAC operation:
G6.2.39 DCISW, Data Cache line Invalidate by Set/Way
Field descriptions
Performing the DCISW operation:
G6.2.40 DFAR, Data Fault Address Register
Field descriptions
Accessing the DFAR:
G6.2.41 DFSR, Data Fault Status Register
Field descriptions
Accessing the DFSR:
G6.2.42 DTLBIALL, Data TLB Invalidate All
Field descriptions
Performing the DTLBIALL operation:
G6.2.43 DTLBIASID, Data TLB Invalidate by ASID match
Field descriptions
Performing the DTLBIASID operation:
G6.2.44 DTLBIMVA, Data TLB Invalidate by VA
Field descriptions
Performing the DTLBIMVA operation:
G6.2.45 ELR_hyp, Exception Link Register (Hyp mode)
Field descriptions
Accessing the ELR_hyp:
G6.2.46 FCSEIDR, FCSE Process ID register
Field descriptions
Accessing the FCSEIDR:
G6.2.47 FPEXC, Floating-Point Exception Control register
Field descriptions
Accessing the FPEXC:
G6.2.48 FPSCR, Floating-Point Status and Control Register
Field descriptions
Accessing the FPSCR:
G6.2.49 FPSID, Floating-Point System ID register
Field descriptions
Accessing the FPSID:
G6.2.50 HACR, Hyp Auxiliary Configuration Register
Field descriptions
Accessing the HACR:
G6.2.51 HACTLR, Hyp Auxiliary Control Register
Field descriptions
Accessing the HACTLR:
G6.2.52 HACTLR2, Hyp Auxiliary Control Register 2
Field descriptions
Accessing the HACTLR2:
G6.2.53 HADFSR, Hyp Auxiliary Data Fault Status Register
Field descriptions
Accessing the HADFSR:
G6.2.54 HAIFSR, Hyp Auxiliary Instruction Fault Status Register
Field descriptions
Accessing the HAIFSR:
G6.2.55 HAMAIR0, Hyp Auxiliary Memory Attribute Indirection Register 0
Field descriptions
Accessing the HAMAIR0:
G6.2.56 HAMAIR1, Hyp Auxiliary Memory Attribute Indirection Register 1
Field descriptions
Accessing the HAMAIR1:
G6.2.57 HCPTR, Hyp Architectural Feature Trap Register
Field descriptions
Accessing the HCPTR:
G6.2.58 HCR, Hyp Configuration Register
Field descriptions
Accessing the HCR:
G6.2.59 HCR2, Hyp Configuration Register 2
Field descriptions
Accessing the HCR2:
G6.2.60 HDFAR, Hyp Data Fault Address Register
Field descriptions
Accessing the HDFAR:
G6.2.61 HIFAR, Hyp Instruction Fault Address Register
Field descriptions
Accessing the HIFAR:
G6.2.62 HMAIR0, Hyp Memory Attribute Indirection Register 0
Field descriptions
Accessing the HMAIR0:
G6.2.63 HMAIR1, Hyp Memory Attribute Indirection Register 1
Field descriptions
Accessing the HMAIR1:
G6.2.64 HPFAR, Hyp IPA Fault Address Register
Field descriptions
Accessing the HPFAR:
G6.2.65 HRMR, Hyp Reset Management Register
Field descriptions
Accessing the HRMR:
G6.2.66 HSCTLR, Hyp System Control Register
Field descriptions
Accessing the HSCTLR:
G6.2.67 HSR, Hyp Syndrome Register
Field descriptions
Accessing the HSR:
G6.2.68 HSTR, Hyp System Trap Register
Field descriptions
Accessing the HSTR:
G6.2.69 HTCR, Hyp Translation Control Register
Field descriptions
Accessing the HTCR:
G6.2.70 HTPIDR, Hyp Software Thread ID Register
Field descriptions
Accessing the HTPIDR:
G6.2.71 HTTBR, Hyp Translation Table Base Register
Field descriptions
Accessing the HTTBR:
G6.2.72 HVBAR, Hyp Vector Base Address Register
Field descriptions
Accessing the HVBAR:
G6.2.73 ICIALLU, Instruction Cache Invalidate All to PoU
Field descriptions
Performing the ICIALLU operation:
G6.2.74 ICIALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
Field descriptions
Performing the ICIALLUIS operation:
G6.2.75 ICIMVAU, Instruction Cache line Invalidate by VA to PoU
Field descriptions
Performing the ICIMVAU operation:
G6.2.76 ID_AFR0, Auxiliary Feature Register 0
Field descriptions
Accessing the ID_AFR0:
G6.2.77 ID_DFR0, Debug Feature Register 0
Field descriptions
Accessing the ID_DFR0:
G6.2.78 ID_ISAR0, Instruction Set Attribute Register 0
Field descriptions
Accessing the ID_ISAR0:
G6.2.79 ID_ISAR1, Instruction Set Attribute Register 1
Field descriptions
Accessing the ID_ISAR1:
G6.2.80 ID_ISAR2, Instruction Set Attribute Register 2
Field descriptions
Accessing the ID_ISAR2:
G6.2.81 ID_ISAR3, Instruction Set Attribute Register 3
Field descriptions
Accessing the ID_ISAR3:
G6.2.82 ID_ISAR4, Instruction Set Attribute Register 4
Field descriptions
Accessing the ID_ISAR4:
G6.2.83 ID_ISAR5, Instruction Set Attribute Register 5
Field descriptions
Accessing the ID_ISAR5:
G6.2.84 ID_MMFR0, Memory Model Feature Register 0
Field descriptions
Accessing the ID_MMFR0:
G6.2.85 ID_MMFR1, Memory Model Feature Register 1
Field descriptions
Accessing the ID_MMFR1:
G6.2.86 ID_MMFR2, Memory Model Feature Register 2
Field descriptions
Accessing the ID_MMFR2:
G6.2.87 ID_MMFR3, Memory Model Feature Register 3
Field descriptions
Accessing the ID_MMFR3:
G6.2.88 ID_MMFR4, Memory Model Feature Register 4
Field descriptions
Accessing the ID_MMFR4:
G6.2.89 ID_PFR0, Processor Feature Register 0
Field descriptions
Accessing the ID_PFR0:
G6.2.90 ID_PFR1, Processor Feature Register 1
Field descriptions
Accessing the ID_PFR1:
G6.2.91 IFAR, Instruction Fault Address Register
Field descriptions
Accessing the IFAR:
G6.2.92 IFSR, Instruction Fault Status Register
Field descriptions
Accessing the IFSR:
G6.2.93 ISR, Interrupt Status Register
Field descriptions
Accessing the ISR:
G6.2.94 ITLBIALL, Instruction TLB Invalidate All
Field descriptions
Performing the ITLBIALL operation:
G6.2.95 ITLBIASID, Instruction TLB Invalidate by ASID match
Field descriptions
Performing the ITLBIASID operation:
G6.2.96 ITLBIMVA, Instruction TLB Invalidate by VA
Field descriptions
Performing the ITLBIMVA operation:
G6.2.97 JIDR, Jazelle ID Register
Field descriptions
Accessing the JIDR:
G6.2.98 JMCR, Jazelle Main Configuration Register
Field descriptions
Accessing the JMCR:
G6.2.99 JOSCR, Jazelle OS Control Register
Field descriptions
Accessing the JOSCR:
G6.2.100 MAIR0, Memory Attribute Indirection Register 0
Field descriptions
Accessing the MAIR0:
G6.2.101 MAIR1, Memory Attribute Indirection Register 1
Field descriptions
Accessing the MAIR1:
G6.2.102 MIDR, Main ID Register
Field descriptions
Accessing the MIDR:
G6.2.103 MPIDR, Multiprocessor Affinity Register
Field descriptions
Accessing the MPIDR:
G6.2.104 MVBAR, Monitor Vector Base Address Register
Field descriptions
Accessing the MVBAR:
G6.2.105 MVFR0, Media and VFP Feature Register 0
Field descriptions
Accessing the MVFR0:
G6.2.106 MVFR1, Media and VFP Feature Register 1
Field descriptions
Accessing the MVFR1:
G6.2.107 MVFR2, Media and VFP Feature Register 2
Field descriptions
Accessing the MVFR2:
G6.2.108 NMRR, Normal Memory Remap Register
Field descriptions
Accessing the NMRR:
G6.2.109 NSACR, Non-Secure Access Control Register
Field descriptions
Accessing the NSACR:
G6.2.110 PAR, Physical Address Register
Field descriptions
Accessing the PAR:
G6.2.111 PRRR, Primary Region Remap Register
Field descriptions
Accessing the PRRR:
G6.2.112 REVIDR, Revision ID Register
Field descriptions
Accessing the REVIDR:
G6.2.113 RMR (at EL1), Reset Management Register
Field descriptions
Accessing the RMR (at EL1):
G6.2.114 RMR (at EL3), Reset Management Register
Field descriptions
Accessing the RMR (at EL3):
G6.2.115 RVBAR, Reset Vector Base Address Register
Field descriptions
Accessing the RVBAR:
G6.2.116 SCR, Secure Configuration Register
Field descriptions
Accessing the SCR:
G6.2.117 SCTLR, System Control Register
Field descriptions
Accessing the SCTLR:
G6.2.118 SPSR, Saved Program Status Register
Field descriptions
G6.2.119 SPSR_abt, Saved Program Status Register (Abort mode)
Field descriptions
Accessing the SPSR_abt:
G6.2.120 SPSR_fiq, Saved Program Status Register (FIQ mode)
Field descriptions
Accessing the SPSR_fiq:
G6.2.121 SPSR_hyp, Saved Program Status Register (Hyp mode)
Field descriptions
Accessing the SPSR_hyp:
G6.2.122 SPSR_irq, Saved Program Status Register (IRQ mode)
Field descriptions
Accessing the SPSR_irq:
G6.2.123 SPSR_mon, Saved Program Status Register (Monitor mode)
Field descriptions
Accessing the SPSR_mon:
G6.2.124 SPSR_svc, Saved Program Status Register (Sup. Call mode)
Field descriptions
Accessing the SPSR_svc:
G6.2.125 SPSR_und, Saved Program Status Register (Undefined mode)
Field descriptions
Accessing the SPSR_und:
G6.2.126 TCMTR, TCM Type Register
Field descriptions
Accessing the TCMTR:
G6.2.127 TLBIALL, TLB Invalidate All
Field descriptions
Performing the TLBIALL operation:
G6.2.128 TLBIALLH, TLB Invalidate All, Hyp mode
Field descriptions
Performing the TLBIALLH operation:
G6.2.129 TLBIALLHIS, TLB Invalidate All, Hyp mode, Inner Shareable
Field descriptions
Performing the TLBIALLHIS operation:
G6.2.130 TLBIALLIS, TLB Invalidate All, Inner Shareable
Field descriptions
Performing the TLBIALLIS operation:
G6.2.131 TLBIALLNSNH, TLB Invalidate All, Non-Secure Non-Hyp
Field descriptions
Performing the TLBIALLNSNH operation:
G6.2.132 TLBIALLNSNHIS, TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
Field descriptions
Performing the TLBIALLNSNHIS operation:
G6.2.133 TLBIASID, TLB Invalidate by ASID match
Field descriptions
Performing the TLBIASID operation:
G6.2.134 TLBIASIDIS, TLB Invalidate by ASID match, Inner Shareable
Field descriptions
Performing the TLBIASIDIS operation:
G6.2.135 TLBIIPAS2, TLB Invalidate by Intermediate Physical Address, Stage 2
Field descriptions
Performing the TLBIIPAS2 operation:
G6.2.136 TLBIIPAS2IS, TLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable
Field descriptions
Performing the TLBIIPAS2IS operation:
G6.2.137 TLBIIPAS2L, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level
Field descriptions
Performing the TLBIIPAS2L operation:
G6.2.138 TLBIIPAS2LIS, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
Field descriptions
Performing the TLBIIPAS2LIS operation:
G6.2.139 TLBIMVA, TLB Invalidate by VA
Field descriptions
Performing the TLBIMVA operation:
G6.2.140 TLBIMVAA, TLB Invalidate by VA, All ASID
Field descriptions
Performing the TLBIMVAA operation:
G6.2.141 TLBIMVAAIS, TLB Invalidate by VA, All ASID, Inner Shareable
Field descriptions
Performing the TLBIMVAAIS operation:
G6.2.142 TLBIMVAAL, TLB Invalidate by VA, All ASID, Last level
Field descriptions
Performing the TLBIMVAAL operation:
G6.2.143 TLBIMVAALIS, TLB Invalidate by VA, All ASID, Last level, Inner Shareable
Field descriptions
Performing the TLBIMVAALIS operation:
G6.2.144 TLBIMVAH, TLB Invalidate by VA, Hyp mode
Field descriptions
Performing the TLBIMVAH operation:
G6.2.145 TLBIMVAHIS, TLB Invalidate by VA, Hyp mode, Inner Shareable
Field descriptions
Performing the TLBIMVAHIS operation:
G6.2.146 TLBIMVAIS, TLB Invalidate by VA, Inner Shareable
Field descriptions
Performing the TLBIMVAIS operation:
G6.2.147 TLBIMVAL, TLB Invalidate by VA, Last level
Field descriptions
Performing the TLBIMVAL operation:
G6.2.148 TLBIMVALH, TLB Invalidate by VA, Last level, Hyp mode
Field descriptions
Performing the TLBIMVALH operation:
G6.2.149 TLBIMVALHIS, TLB Invalidate by VA, Last level, Hyp mode, Inner Shareable
Field descriptions
Performing the TLBIMVALHIS operation:
G6.2.150 TLBIMVALIS, TLB Invalidate by VA, Last level, Inner Shareable
Field descriptions
Performing the TLBIMVALIS operation:
G6.2.151 TLBTR, TLB Type Register
Field descriptions
Accessing the TLBTR:
G6.2.152 TPIDRPRW, PL1 Software Thread ID Register
Field descriptions
Accessing the TPIDRPRW:
G6.2.153 TPIDRURO, PL0 Read-Only Software Thread ID Register
Field descriptions
Accessing the TPIDRURO:
G6.2.154 TPIDRURW, PL0 Read/Write Software Thread ID Register
Field descriptions
Accessing the TPIDRURW:
G6.2.155 TTBCR, Translation Table Base Control Register
Field descriptions
Accessing the TTBCR:
G6.2.156 TTBR0, Translation Table Base Register 0
Field descriptions
Accessing the TTBR0:
G6.2.157 TTBR1, Translation Table Base Register 1
Field descriptions
Accessing the TTBR1:
G6.2.158 VBAR, Vector Base Address Register
Field descriptions
Accessing the VBAR:
G6.2.159 VMPIDR, Virtualization Multiprocessor ID Register
Field descriptions
Accessing the VMPIDR:
G6.2.160 VPIDR, Virtualization Processor ID Register
Field descriptions
Accessing the VPIDR:
G6.2.161 VTCR, Virtualization Translation Control Register
Field descriptions
Accessing the VTCR:
G6.2.162 VTTBR, Virtualization Translation Table Base Register
Field descriptions
Accessing the VTTBR:
G6.3 Debug registers
G6.3.1 DBGAUTHSTATUS, Debug Authentication Status register
Field descriptions
Accessing the DBGAUTHSTATUS:
G6.3.2 DBGBCR, Debug Breakpoint Control Registers, n = 0 - 15
Field descriptions
Accessing the DBGBCR:
G6.3.3 DBGBVR, Debug Breakpoint Value Registers, n = 0 - 15
Field descriptions
Accessing the DBGBVR:
G6.3.4 DBGBXVR, Debug Breakpoint Extended Value Registers, n = 0 - 15
Field descriptions
Accessing the DBGBXVR:
G6.3.5 DBGCLAIMCLR, Debug Claim Tag Clear register
Field descriptions
Accessing the DBGCLAIMCLR:
G6.3.6 DBGCLAIMSET, Debug Claim Tag Set register
Field descriptions
Accessing the DBGCLAIMSET:
G6.3.7 DBGDCCINT, DCC Interrupt Enable Register
Field descriptions
Accessing the DBGDCCINT:
G6.3.8 DBGDEVID, Debug Device ID register 0
Field descriptions
Accessing the DBGDEVID:
G6.3.9 DBGDEVID1, Debug Device ID register 1
Field descriptions
Accessing the DBGDEVID1:
G6.3.10 DBGDEVID2, Debug Device ID register 2
Field descriptions
Accessing the DBGDEVID2:
G6.3.11 DBGDIDR, Debug ID Register
Field descriptions
Accessing the DBGDIDR:
G6.3.12 DBGDRAR, Debug ROM Address Register
Field descriptions
Accessing the DBGDRAR:
G6.3.13 DBGDSAR, Debug Self Address Register
Field descriptions
Accessing the DBGDSAR:
G6.3.14 DBGDSCRext, Debug Status and Control Register, External View
Field descriptions
Accessing the DBGDSCRext:
G6.3.15 DBGDSCRint, Debug Status and Control Register, Internal View
Field descriptions
Accessing the DBGDSCRint:
G6.3.16 DBGDTRRXext, Debug OS Lock Data Transfer Register, Receive, External View
Field descriptions
Accessing the DBGDTRRXext:
G6.3.17 DBGDTRRXint, Debug Data Transfer Register, Receive
Field descriptions
Accessing the DBGDTRRXint:
G6.3.18 DBGDTRTXext, Debug OS Lock Data Transfer Register, Transmit
Field descriptions
Accessing the DBGDTRTXext:
G6.3.19 DBGDTRTXint, Debug Data Transfer Register, Transmit
Field descriptions
Accessing the DBGDTRTXint:
G6.3.20 DBGOSDLR, Debug OS Double Lock Register
Field descriptions
Accessing the DBGOSDLR:
G6.3.21 DBGOSECCR, Debug OS Lock Exception Catch Control Register
Field descriptions
Accessing the DBGOSECCR:
G6.3.22 DBGOSLAR, Debug OS Lock Access Register
Field descriptions
Accessing the DBGOSLAR:
G6.3.23 DBGOSLSR, Debug OS Lock Status Register
Field descriptions
Accessing the DBGOSLSR:
G6.3.24 DBGPRCR, Debug Power Control Register
Field descriptions
Accessing the DBGPRCR:
G6.3.25 DBGVCR, Debug Vector Catch Register
Field descriptions
Accessing the DBGVCR:
G6.3.26 DBGWCR, Debug Watchpoint Control Registers, n = 0 - 15
Field descriptions
Accessing the DBGWCR:
G6.3.27 DBGWFAR, Debug Watchpoint Fault Address Register
Field descriptions
Accessing the DBGWFAR:
G6.3.28 DBGWVR, Debug Watchpoint Value Registers, n = 0 - 15
Field descriptions
Accessing the DBGWVR:
G6.3.29 DLR, Debug Link Register
Field descriptions
Accessing the DLR:
G6.3.30 DSPSR, Debug Saved Program Status Register
Field descriptions
Accessing the DSPSR:
G6.3.31 HDCR, Hyp Debug Control Register
Field descriptions
Accessing the HDCR:
G6.3.32 SDCR, Secure Debug Configuration Register
Field descriptions
Accessing the SDCR:
G6.3.33 SDER, Secure Debug Enable Register
Field descriptions
Accessing the SDER:
G6.4 Performance Monitors registers
G6.4.1 PMCCFILTR, Performance Monitors Cycle Count Filter Register
Field descriptions
Accessing the PMCCFILTR:
G6.4.2 PMCCNTR, Performance Monitors Cycle Count Register
Field descriptions
Accessing the PMCCNTR:
G6.4.3 PMCEID0, Performance Monitors Common Event Identification register 0
Field descriptions
Accessing the PMCEID0:
G6.4.4 PMCEID1, Performance Monitors Common Event Identification register 1
Field descriptions
Accessing the PMCEID1:
G6.4.5 PMCNTENCLR, Performance Monitors Count Enable Clear register
Field descriptions
Accessing the PMCNTENCLR:
G6.4.6 PMCNTENSET, Performance Monitors Count Enable Set register
Field descriptions
Accessing the PMCNTENSET:
G6.4.7 PMCR, Performance Monitors Control Register
Field descriptions
Accessing the PMCR:
G6.4.8 PMEVCNTR, Performance Monitors Event Count Registers, n = 0 - 30
Field descriptions
Accessing the PMEVCNTR:
G6.4.9 PMEVTYPER, Performance Monitors Event Type Registers, n = 0 - 30
Field descriptions
Accessing the PMEVTYPER:
G6.4.10 PMINTENCLR, Performance Monitors Interrupt Enable Clear register
Field descriptions
Accessing the PMINTENCLR:
G6.4.11 PMINTENSET, Performance Monitors Interrupt Enable Set register
Field descriptions
Accessing the PMINTENSET:
G6.4.12 PMOVSR, Performance Monitors Overflow Flag Status Register
Field descriptions
Accessing the PMOVSR:
G6.4.13 PMOVSSET, Performance Monitors Overflow Flag Status Set register
Field descriptions
Accessing the PMOVSSET:
G6.4.14 PMSELR, Performance Monitors Event Counter Selection Register
Field descriptions
Accessing the PMSELR:
G6.4.15 PMSWINC, Performance Monitors Software Increment register
Field descriptions
Accessing the PMSWINC:
G6.4.16 PMUSERENR, Performance Monitors User Enable Register
Field descriptions
Accessing the PMUSERENR:
G6.4.17 PMXEVCNTR, Performance Monitors Selected Event Count Register
Field descriptions
Accessing the PMXEVCNTR:
G6.4.18 PMXEVTYPER, Performance Monitors Selected Event Type Register
Field descriptions
Accessing the PMXEVTYPER:
G6.5 Generic Timer registers
G6.5.1 CNTFRQ, Counter-timer Frequency register
Field descriptions
Accessing the CNTFRQ:
G6.5.2 CNTHCTL, Counter-timer Hyp Control register
Field descriptions
Accessing the CNTHCTL:
G6.5.3 CNTHP_CTL, Counter-timer Hyp Physical Timer Control register
Field descriptions
Accessing the CNTHP_CTL:
G6.5.4 CNTHP_CVAL, Counter-timer Hyp Physical CompareValue register
Field descriptions
Accessing the CNTHP_CVAL:
G6.5.5 CNTHP_TVAL, Counter-timer Hyp Physical Timer TimerValue register
Field descriptions
Accessing the CNTHP_TVAL:
G6.5.6 CNTKCTL, Counter-timer Kernel Control register
Field descriptions
Accessing the CNTKCTL:
G6.5.7 CNTP_CTL, Counter-timer Physical Timer Control register
Field descriptions
Accessing the CNTP_CTL:
G6.5.8 CNTP_CVAL, Counter-timer Physical Timer CompareValue register
Field descriptions
Accessing the CNTP_CVAL:
G6.5.9 CNTP_TVAL, Counter-timer Physical Timer TimerValue register
Field descriptions
Accessing the CNTP_TVAL:
G6.5.10 CNTPCT, Counter-timer Physical Count register
Field descriptions
Accessing the CNTPCT:
G6.5.11 CNTV_CTL, Counter-timer Virtual Timer Control register
Field descriptions
Accessing the CNTV_CTL:
G6.5.12 CNTV_CVAL, Counter-timer Virtual Timer CompareValue register
Field descriptions
Accessing the CNTV_CVAL:
G6.5.13 CNTV_TVAL, Counter-timer Virtual Timer TimerValue register
Field descriptions
Accessing the CNTV_TVAL:
G6.5.14 CNTVCT, Counter-timer Virtual Count register
Field descriptions
Accessing the CNTVCT:
G6.5.15 CNTVOFF, Counter-timer Virtual Offset register
Field descriptions
Accessing the CNTVOFF:
Part H: External Debug
H1: Introduction to External Debug
H1.1 Introduction to external debug
H1.2 External debug
H2: Debug State
H2.1 About Debug state
H2.2 Halting the PE on debug events
H2.2.1 Halting allowed and halting prohibited
H2.2.2 Halting debug events
H2.2.3 Breakpoint and Watchpoint debug events
H2.2.4 Other debug exceptions
H2.2.5 Debug state entry and debug event prioritization
Breakpoint debug events and Vector Catch exception
H2.2.6 Forcing entry to Debug state
H2.2.7 Summary of actions from debug events
H2.2.8 Pseudocode description of Halting on debug events
H2.3 Entering Debug state
H2.3.1 Entering Debug state from AArch32 state
H2.3.2 Effect of entering Debug state on DLR and DSPSR
H2.3.3 Effect of Debug state entry on System registers, the Event register, and exclusive monitors
H2.3.4 Effect of entering Debug state on PSTATE
H2.3.5 Entering Debug state during loads and stores
H2.3.6 Entering Debug state and Software Step
H2.3.7 Pseudocode description of entering Debug state
H2.4 Behavior in Debug state
H2.4.1 Process state (PSTATE) in Debug state
H2.4.2 Executing instructions in Debug state
Executing A64 instructions in Debug state
Executing T32 instructions in Debug state
H2.4.3 Decode tables
H2.4.4 Security in Debug state
H2.4.5 Privilege in Debug state
H2.4.6 Debug state instructions, DCPS, DRPS, MRS, MSR
DCPS
DRPS
MRS and MSR instructions to access DLR_EL0 and DSPSR_EL0
H2.4.7 Exceptions in Debug state
Generating exceptions when in Debug state
Taking exceptions when in Debug state
Pseudocode description of taking exceptions in Debug state
Reset in Debug state
H2.4.8 Accessing registers in Debug state
General-purpose register access, other than SP access in AArch64 state
SIMD and floating-point register, System register, and SP accesses in AArch64 state
PC and PSTATE access
H2.4.9 Accessing memory in Debug state
Simple memory transfers
Bulk memory transfers
H2.5 Exiting Debug state
H3: Halting Debug Events
H3.1 Introduction to Halting debug events
H3.2 Halting Step debug events
H3.2.1 Overview of a Halting Step debug event
H3.2.2 The Halting Step state machine
H3.2.3 Using Halting Step
H3.2.4 Detailed Halting Step state machine behavior
Entering the active-not-pending state
PE behavior in the active-not-pending state
Entering the active-pending state
PE behavior in the inactive state when in Non-debug state
PE behavior in Debug state
H3.2.5 Synchronization and the Halting Step state machine
H3.2.6 Stepping T32 IT instructions
H3.2.7 Disabling interrupts while stepping
H3.2.8 Syndrome information on Halting Step
H3.2.9 Pseudocode description of Halting Step debug events
H3.3 Halt Instruction debug event
H3.3.1 HLT instructions as the first instruction in a T32 IT block
H3.4 Exception Catch debug event
H3.4.1 Prioritization of Exception Catch debug events
H3.4.2 CONSTRAINED UNPREDICTABLE generation of Exception Catch debug events
H3.4.3 Examples of Exception Catch debug events
H3.4.4 Pseudocode description of Exception Catch debug events
H3.5 External Debug Request debug event
H3.5.1 Pseudocode description of External Debug Request debug events
H3.6 OS Unlock Catch debug event
H3.6.1 Using the OS Unlock Catch debug event
H3.6.2 Pseudocode description of OS Unlock Catch debug event
H3.7 Reset Catch debug events
H3.7.1 Pseudocode description of Reset Catch debug event
H3.8 Software Access debug event
H3.8.1 Pseudocode description of Software Access debug event
H3.9 Synchronization and Halting debug events
H3.9.1 Pending Halting debug events
H3.9.2 Taking Halting debug events asynchronously
H4: The Debug Communication Channel and Instruction Transfer Register
H4.1 Introduction
H4.2 DCC and ITR registers
H4.3 DCC and ITR access modes
H4.3.1 Normal access mode
H4.3.2 Memory access mode
Ordering, access sizes and effect on exclusive monitors
Data Aborts in Memory access mode
Illegal Execution state exception
Alignment constraints
H4.3.3 Memory-mapped accesses to the DCC and ITR
H4.4 Flow control of the DCC and ITR registers
H4.4.1 Ready flags
H4.4.2 Buffering writes to EDITR
H4.4.3 Overrun and underrun flags
Accessing 64-bit data
H4.4.4 Cumulative error flag
Pseudocode description of clearing the error flag
H4.5 Synchronization of DCC and ITR accesses
H4.5.1 Summary of System register accesses to the DCC
H4.5.2 DCC accesses in Non-debug state
Derived requirements
H4.5.3 Synchronization of DCC interrupt request signals
H4.5.4 DCC and ITR access in Debug state
H4.6 Interrupt-driven use of the DCC
H4.7 Pseudocode description of the operation of the DCC and ITR registers
H5: The Embedded Cross-Trigger Interface
H5.1 About the Embedded Cross-Trigger (ECT)
H5.1.1 Implementation with a CoreSight CTI
H5.2 Basic operation on the ECT
H5.2.1 Multicycle events
An ECT that supports multicycle trigger events
An ECT that does not support multicycle trigger events
H5.3 Cross-triggers on a PE in an ARMv8 implementation
H5.4 Description and allocation of CTI triggers
H5.4.1 Debug request trigger event
H5.4.2 Restart request trigger event
H5.4.3 Cross-halt trigger event
H5.4.4 Performance Monitors overflow trigger event
H5.4.5 Generic trace external input trigger events
H5.4.6 Generic trace external output trigger events
H5.4.7 Generic CTI interrupt trigger event
H5.5 CTI registers programmers’ model
H5.5.1 CTI reset
H5.5.2 CTI authentication
H5.6 Examples
H6: Debug Reset and Powerdown Support
H6.1 About Debug over powerdown
H6.2 Power domains and debug
H6.3 Core power domain power states
H6.4 Emulating low-power states
H6.5 Debug OS Save and Restore sequences
H6.5.1 Debug registers to save over powerdown
H6.5.2 OS Save sequence
H6.5.3 OS Restore sequence
H6.5.4 Debug behavior when the OS Lock is locked
H6.5.5 Debug behavior when the OS Lock is unlocked
H6.5.6 Debug behavior when the OS Double Lock is locked
H6.6 Reset and debug
H6.6.1 External debug interface accesses to registers in reset
H7: The PC Sample-based Profiling Extension
H7.1 Sample-based profiling of the PC
H7.1.1 The implemented Sample-based Profiling registers
H7.1.2 Reads of the EDPCSRs
H7.1.3 Reads of the EDVCSR
H7.1.4 Accuracy of sampling
H7.1.5 PC Sample-based Profiling and security
H7.1.6 Pseudocode description of PC Sample-based Profiling
H8: About the External Debug Registers
H8.1 Relationship between external debug and System registers
H8.2 Supported access sizes
H8.3 Synchronization of changes to the external debug registers
H8.3.1 Synchronization and the authentication interface
H8.3.2 Examples of the synchronization of changes to the external debug registers
H8.4 Memory-mapped accesses to the external debug interface
H8.4.1 Register access permissions for memory-mapped accesses
Effect of the optional Software Lock on memory-mapped access
Behavior of a not permitted memory-mapped access
H8.4.2 Synchronization of memory-mapped accesses to external debug registers
H8.4.3 Access sizes for memory-mapped accesses
H8.5 External debug interface register access permissions
H8.5.1 External debug over powerdown and locks
H8.5.2 External access disabled
H8.5.3 Behavior of a not permitted access
H8.5.4 Trapping software access to debug registers
H8.5.5 External debug interface register access permissions summary
H8.5.6 IMPLEMENTATION DEFINED registers
H8.5.7 OPTIONAL CoreSight management registers
H8.5.8 Reserved and unallocated registers
H8.6 External debug interface registers
H8.6.1 Access permissions for the External debug interface registers
H8.7 Cross-trigger interface registers
H8.8 External debug register resets
H9: External Debug Register Descriptions
H9.1 Introduction
H9.2 Debug registers
H9.2.1 DBGAUTHSTATUS_EL1, Debug Authentication Status register
Field descriptions
Accessing the DBGAUTHSTATUS_EL1:
H9.2.2 DBGBCR_EL1, Debug Breakpoint Control Registers, n = 0 - 15
Field descriptions
Accessing the DBGBCR_EL1:
H9.2.3 DBGBVR_EL1, Debug Breakpoint Value Registers, n = 0 - 15
Field descriptions
Accessing the DBGBVR_EL1:
H9.2.4 DBGCLAIMCLR_EL1, Debug Claim Tag Clear register
Field descriptions
Accessing the DBGCLAIMCLR_EL1:
H9.2.5 DBGCLAIMSET_EL1, Debug Claim Tag Set register
Field descriptions
Accessing the DBGCLAIMSET_EL1:
H9.2.6 DBGDTRRX_EL0, Debug Data Transfer Register, Receive
Field descriptions
Accessing the DBGDTRRX_EL0:
H9.2.7 DBGDTRTX_EL0, Debug Data Transfer Register, Transmit
Field descriptions
Accessing the DBGDTRTX_EL0:
H9.2.8 DBGWCR_EL1, Debug Watchpoint Control Registers, n = 0 - 15
Field descriptions
Accessing the DBGWCR_EL1:
H9.2.9 DBGWVR_EL1, Debug Watchpoint Value Registers, n = 0 - 15
Field descriptions
Accessing the DBGWVR_EL1:
H9.2.10 EDAA32PFR, External Debug AArch32 Processor Feature Register
Field descriptions
Accessing the EDAA32PFR:
H9.2.11 EDACR, External Debug Auxiliary Control Register
Field descriptions
Accessing the EDACR:
H9.2.12 EDCIDR0, External Debug Component Identification Register 0
Field descriptions
Accessing the EDCIDR0:
H9.2.13 EDCIDR1, External Debug Component Identification Register 1
Field descriptions
Accessing the EDCIDR1:
H9.2.14 EDCIDR2, External Debug Component Identification Register 2
Field descriptions
Accessing the EDCIDR2:
H9.2.15 EDCIDR3, External Debug Component Identification Register 3
Field descriptions
Accessing the EDCIDR3:
H9.2.16 EDCIDSR, External Debug Context ID Sample Register
Field descriptions
Accessing the EDCIDSR:
H9.2.17 EDDEVAFF0, External Debug Device Affinity register 0
Field descriptions
Accessing the EDDEVAFF0:
H9.2.18 EDDEVAFF1, External Debug Device Affinity register 1
Field descriptions
Accessing the EDDEVAFF1:
H9.2.19 EDDEVARCH, External Debug Device Architecture register
Field descriptions
Accessing the EDDEVARCH:
H9.2.20 EDDEVID, External Debug Device ID register 0
Field descriptions
Accessing the EDDEVID:
H9.2.21 EDDEVID1, External Debug Device ID register 1
Field descriptions
Accessing the EDDEVID1:
H9.2.22 EDDEVID2, External Debug Device ID register 2
Field descriptions
Accessing the EDDEVID2:
H9.2.23 EDDEVTYPE, External Debug Device Type register
Field descriptions
Accessing the EDDEVTYPE:
H9.2.24 EDDFR, External Debug Feature Register
Field descriptions
Accessing the EDDFR:
H9.2.25 EDECCR, External Debug Exception Catch Control Register
Field descriptions
Accessing the EDECCR:
H9.2.26 EDECR, External Debug Execution Control Register
Field descriptions
Accessing the EDECR:
H9.2.27 EDESR, External Debug Event Status Register
Field descriptions
Accessing the EDESR:
H9.2.28 EDITCTRL, External Debug Integration mode Control register
Field descriptions
Accessing the EDITCTRL:
H9.2.29 EDITR, External Debug Instruction Transfer Register
Field descriptions
Accessing the EDITR:
H9.2.30 EDLAR, External Debug Lock Access Register
Field descriptions
Accessing the EDLAR:
H9.2.31 EDLSR, External Debug Lock Status Register
Field descriptions
Accessing the EDLSR:
H9.2.32 EDPCSR, External Debug Program Counter Sample Register
Field descriptions
Accessing the EDPCSR:
H9.2.33 EDPFR, External Debug Processor Feature Register
Field descriptions
Accessing the EDPFR:
H9.2.34 EDPIDR0, External Debug Peripheral Identification Register 0
Field descriptions
Accessing the EDPIDR0:
H9.2.35 EDPIDR1, External Debug Peripheral Identification Register 1
Field descriptions
Accessing the EDPIDR1:
H9.2.36 EDPIDR2, External Debug Peripheral Identification Register 2
Field descriptions
Accessing the EDPIDR2:
H9.2.37 EDPIDR3, External Debug Peripheral Identification Register 3
Field descriptions
Accessing the EDPIDR3:
H9.2.38 EDPIDR4, External Debug Peripheral Identification Register 4
Field descriptions
Accessing the EDPIDR4:
H9.2.39 EDPRCR, External Debug Power/Reset Control Register
Field descriptions
Accessing the EDPRCR:
H9.2.40 EDPRSR, External Debug Processor Status Register
Field descriptions
Accessing the EDPRSR:
H9.2.41 EDRCR, External Debug Reserve Control Register
Field descriptions
Accessing the EDRCR:
H9.2.42 EDSCR, External Debug Status and Control Register
Field descriptions
Accessing the EDSCR:
H9.2.43 EDVIDSR, External Debug Virtual Context Sample Register
Field descriptions
Accessing the EDVIDSR:
H9.2.44 EDWAR, External Debug Watchpoint Address Register
Field descriptions
Accessing the EDWAR:
H9.2.45 MIDR_EL1, Main ID Register
Field descriptions
Accessing the MIDR_EL1:
H9.2.46 OSLAR_EL1, OS Lock Access Register
Field descriptions
Accessing the OSLAR_EL1:
H9.3 Cross-Trigger Interface registers
H9.3.1 ASICCTL, CTI External Multiplexer Control register
Field descriptions
Accessing the ASICCTL:
H9.3.2 CTIAPPCLEAR, CTI Application Trigger Clear register
Field descriptions
Accessing the CTIAPPCLEAR:
H9.3.3 CTIAPPPULSE, CTI Application Pulse register
Field descriptions
Accessing the CTIAPPPULSE:
H9.3.4 CTIAPPSET, CTI Application Trigger Set register
Field descriptions
Accessing the CTIAPPSET:
H9.3.5 CTIAUTHSTATUS, CTI Authentication Status register
Field descriptions
Accessing the CTIAUTHSTATUS:
H9.3.6 CTICHINSTATUS, CTI Channel In Status register
Field descriptions
Accessing the CTICHINSTATUS:
H9.3.7 CTICHOUTSTATUS, CTI Channel Out Status register
Field descriptions
Accessing the CTICHOUTSTATUS:
H9.3.8 CTICIDR0, CTI Component Identification Register 0
Field descriptions
Accessing the CTICIDR0:
H9.3.9 CTICIDR1, CTI Component Identification Register 1
Field descriptions
Accessing the CTICIDR1:
H9.3.10 CTICIDR2, CTI Component Identification Register 2
Field descriptions
Accessing the CTICIDR2:
H9.3.11 CTICIDR3, CTI Component Identification Register 3
Field descriptions
Accessing the CTICIDR3:
H9.3.12 CTICLAIMCLR, CTI Claim Tag Clear register
Field descriptions
Accessing the CTICLAIMCLR:
H9.3.13 CTICLAIMSET, CTI Claim Tag Set register
Field descriptions
Accessing the CTICLAIMSET:
H9.3.14 CTICONTROL, CTI Control register
Field descriptions
Accessing the CTICONTROL:
H9.3.15 CTIDEVAFF0, CTI Device Affinity register 0
Field descriptions
Accessing the CTIDEVAFF0:
H9.3.16 CTIDEVAFF1, CTI Device Affinity register 1
Field descriptions
Accessing the CTIDEVAFF1:
H9.3.17 CTIDEVARCH, CTI Device Architecture register
Field descriptions
Accessing the CTIDEVARCH:
H9.3.18 CTIDEVID, CTI Device ID register 0
Field descriptions
Accessing the CTIDEVID:
H9.3.19 CTIDEVID1, CTI Device ID register 1
Field descriptions
Accessing the CTIDEVID1:
H9.3.20 CTIDEVID2, CTI Device ID register 2
Field descriptions
Accessing the CTIDEVID2:
H9.3.21 CTIDEVTYPE, CTI Device Type register
Field descriptions
Accessing the CTIDEVTYPE:
H9.3.22 CTIGATE, CTI Channel Gate Enable register
Field descriptions
Accessing the CTIGATE:
H9.3.23 CTIINEN, CTI Input Trigger to Output Channel Enable registers, n = 0 - 31
Field descriptions
Accessing the CTIINEN:
H9.3.24 CTIINTACK, CTI Output Trigger Acknowledge register
Field descriptions
Accessing the CTIINTACK:
H9.3.25 CTIITCTRL, CTI Integration mode Control register
Field descriptions
Accessing the CTIITCTRL:
H9.3.26 CTILAR, CTI Lock Access Register
Field descriptions
Accessing the CTILAR:
H9.3.27 CTILSR, CTI Lock Status Register
Field descriptions
Accessing the CTILSR:
H9.3.28 CTIOUTEN, CTI Input Channel to Output Trigger Enable registers, n = 0 - 31
Field descriptions
Accessing the CTIOUTEN:
H9.3.29 CTIPIDR0, CTI Peripheral Identification Register 0
Field descriptions
Accessing the CTIPIDR0:
H9.3.30 CTIPIDR1, CTI Peripheral Identification Register 1
Field descriptions
Accessing the CTIPIDR1:
H9.3.31 CTIPIDR2, CTI Peripheral Identification Register 2
Field descriptions
Accessing the CTIPIDR2:
H9.3.32 CTIPIDR3, CTI Peripheral Identification Register 3
Field descriptions
Accessing the CTIPIDR3:
H9.3.33 CTIPIDR4, CTI Peripheral Identification Register 4
Field descriptions
Accessing the CTIPIDR4:
H9.3.34 CTITRIGINSTATUS, CTI Trigger In Status register
Field descriptions
Accessing the CTITRIGINSTATUS:
H9.3.35 CTITRIGOUTSTATUS, CTI Trigger Out Status register
Field descriptions
Accessing the CTITRIGOUTSTATUS:
Part I: Memory-mapped Components of the ARMv8 Architecture
I1: System Level Implementation of the Generic Timer
I1.1 About the Generic Timer specification
I1.1.1 Registers in the system level implementation of the Generic Timer
I1.1.2 The system level components of the Generic Timer
I1.2 Memory-mapped counter module
I1.2.1 Control of counter operating frequency and increment
The frequency modes table
Changing the system counter and increment
I1.2.2 Counter module control and status register summary
I1.3 Memory-mapped timer components
I1.3.1 The CNTCTLBase frame
I1.3.2 The CNTBaseN and CNTEL0BaseN frames
The CNTEL0BaseN frame
I1.4 Providing a complete set of counter and timer features
I1.5 Gray-count scheme for timer distribution scheme
I2: Recommended Memory-mapped Interfaces to the Performance Monitors
I2.1 About the memory-mapped views of the Performance Monitors registers
I2.1.1 Differences in the memory-mapped views of the Performance Monitors registers
I2.1.2 Synchronization of changes to the memory-mapped views
I2.1.3 Access permissions for memory-mapped views of the Performance Monitors
I2.1.4 Power domains and Performance Monitors registers reset
I3: Memory-Mapped System Control Register Descriptions
I3.1 About the memory-mapped system control register descriptions
I3.2 Performance Monitors memory-mapped registers summary
I3.2.1 Performance Monitors memory-mapped register views
I3.3 Performance Monitors memory-mapped register descriptions
I3.3.1 PMAUTHSTATUS, Performance Monitors Authentication Status register
Field descriptions
Accessing the PMAUTHSTATUS:
I3.3.2 PMCCFILTR_EL0, Performance Monitors Cycle Counter Filter Register
Field descriptions
Accessing the PMCCFILTR_EL0:
I3.3.3 PMCCNTR_EL0, Performance Monitors Cycle Counter
Field descriptions
Accessing the PMCCNTR_EL0:
I3.3.4 PMCEID0_EL0, Performance Monitors Common Event Identification register 0
Field descriptions
Accessing the PMCEID0_EL0:
I3.3.5 PMCEID1_EL0, Performance Monitors Common Event Identification register 1
Field descriptions
Accessing the PMCEID1_EL0:
I3.3.6 PMCFGR, Performance Monitors Configuration Register
Field descriptions
Accessing the PMCFGR:
I3.3.7 PMCIDR0, Performance Monitors Component Identification Register 0
Field descriptions
Accessing the PMCIDR0:
I3.3.8 PMCIDR1, Performance Monitors Component Identification Register 1
Field descriptions
Accessing the PMCIDR1:
I3.3.9 PMCIDR2, Performance Monitors Component Identification Register 2
Field descriptions
Accessing the PMCIDR2:
I3.3.10 PMCIDR3, Performance Monitors Component Identification Register 3
Field descriptions
Accessing the PMCIDR3:
I3.3.11 PMCNTENCLR_EL0, Performance Monitors Count Enable Clear register
Field descriptions
Accessing the PMCNTENCLR_EL0:
I3.3.12 PMCNTENSET_EL0, Performance Monitors Count Enable Set register
Field descriptions
Accessing the PMCNTENSET_EL0:
I3.3.13 PMCR_EL0, Performance Monitors Control Register
Field descriptions
Accessing the PMCR_EL0:
I3.3.14 PMDEVAFF0, Performance Monitors Device Affinity register 0
Field descriptions
Accessing the PMDEVAFF0:
I3.3.15 PMDEVAFF1, Performance Monitors Device Affinity register 1
Field descriptions
Accessing the PMDEVAFF1:
I3.3.16 PMDEVARCH, Performance Monitors Device Architecture register
Field descriptions
Accessing the PMDEVARCH:
I3.3.17 PMDEVTYPE, Performance Monitors Device Type register
Field descriptions
Accessing the PMDEVTYPE:
I3.3.18 PMEVCNTR_EL0, Performance Monitors Event Count Registers, n = 0 - 30
Field descriptions
Accessing the PMEVCNTR_EL0:
I3.3.19 PMEVTYPER_EL0, Performance Monitors Event Type Registers, n = 0 - 30
Field descriptions
Accessing the PMEVTYPER_EL0:
I3.3.20 PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear register
Field descriptions
Accessing the PMINTENCLR_EL1:
I3.3.21 PMINTENSET_EL1, Performance Monitors Interrupt Enable Set register
Field descriptions
Accessing the PMINTENSET_EL1:
I3.3.22 PMITCTRL, Performance Monitors Integration mode Control register
Field descriptions
Accessing the PMITCTRL:
I3.3.23 PMLAR, Performance Monitors Lock Access Register
Field descriptions
Accessing the PMLAR:
I3.3.24 PMLSR, Performance Monitors Lock Status Register
Field descriptions
Accessing the PMLSR:
I3.3.25 PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear register
Field descriptions
Accessing the PMOVSCLR_EL0:
I3.3.26 PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set register
Field descriptions
Accessing the PMOVSSET_EL0:
I3.3.27 PMPIDR0, Performance Monitors Peripheral Identification Register 0
Field descriptions
Accessing the PMPIDR0:
I3.3.28 PMPIDR1, Performance Monitors Peripheral Identification Register 1
Field descriptions
Accessing the PMPIDR1:
I3.3.29 PMPIDR2, Performance Monitors Peripheral Identification Register 2
Field descriptions
Accessing the PMPIDR2:
I3.3.30 PMPIDR3, Performance Monitors Peripheral Identification Register 3
Field descriptions
Accessing the PMPIDR3:
I3.3.31 PMPIDR4, Performance Monitors Peripheral Identification Register 4
Field descriptions
Accessing the PMPIDR4:
I3.3.32 PMSWINC_EL0, Performance Monitors Software Increment register
Field descriptions
Accessing the PMSWINC_EL0:
I3.4 Generic Timer memory-mapped registers overview
I3.5 Generic Timer memory-mapped register descriptions
I3.5.1 CNTACR, Counter-timer Access Control Registers, n = 0 - 7
Field descriptions
Accessing the CNTACR:
I3.5.2 CNTCR, Counter Control Register
Field descriptions
Accessing the CNTCR:
I3.5.3 CNTCV, Counter Count Value register
Field descriptions
Accessing the CNTCV:
I3.5.4 CNTEL0ACR, Counter-timer EL0 Access Control Register
Field descriptions
Accessing the CNTEL0ACR:
I3.5.5 CNTFID0, Counter Frequency ID
Field descriptions
Accessing the CNTFID0:
I3.5.6 CNTFID, Counter Frequency IDs, n = 1 - 23
Field descriptions
Accessing the CNTFID:
I3.5.7 CNTFRQ, Counter-timer Frequency
Field descriptions
Accessing the CNTFRQ:
I3.5.8 CNTNSAR, Counter-timer Non-secure Access Register
Field descriptions
Accessing the CNTNSAR:
I3.5.9 CNTP_CTL, Counter-timer Physical Timer Control
Field descriptions
Accessing the CNTP_CTL:
I3.5.10 CNTP_CVAL, Counter-timer Physical Timer CompareValue
Field descriptions
Accessing the CNTP_CVAL:
I3.5.11 CNTP_TVAL, Counter-timer Physical Timer TimerValue
Field descriptions
Accessing the CNTP_TVAL:
I3.5.12 CNTPCT, Counter-timer Physical Count
Field descriptions
Accessing the CNTPCT:
I3.5.13 CNTSR, Counter Status Register
Field descriptions
Accessing the CNTSR:
I3.5.14 CNTTIDR, Counter-timer Timer ID Register
Field descriptions
Accessing the CNTTIDR:
I3.5.15 CNTV_CTL, Counter-timer Virtual Timer Control
Field descriptions
Accessing the CNTV_CTL:
I3.5.16 CNTV_CVAL, Counter-timer Virtual Timer CompareValue
Field descriptions
Accessing the CNTV_CVAL:
I3.5.17 CNTV_TVAL, Counter-timer Virtual Timer TimerValue
Field descriptions
Accessing the CNTV_TVAL:
I3.5.18 CNTVCT, Counter-timer Virtual Count
Field descriptions
Accessing the CNTVCT:
I3.5.19 CNTVOFF{}, Counter-timer Virtual Offset
Field descriptions
Accessing the CNTVOFF{}:
I3.5.20 CounterID, Counter ID registers, n = 0 - 11
Field descriptions
Accessing the CounterID:
Part J: Architectural Pseudocode
J1: ARMv8 Pseudocode
J1.1 Pseudocode for AArch64 operations
J1.1.1 aarch64/debug
aarch64/debug/breakpoint/AArch64.BreakpointMatch
aarch64/debug/breakpoint/AArch64.BreakpointValueMatch
aarch64/debug/breakpoint/AArch64.StateMatch
aarch64/debug/enables/AArch64.GenerateDebugExceptions
aarch64/debug/enables/AArch64.GenerateDebugExceptionsFrom
aarch64/debug/pmu/AArch64.CheckForPMUOverflow
aarch64/debug/pmu/AArch64.CountEvents
aarch64/debug/pmu/AArch64.ProfilingProhibited
aarch64/debug/takeexceptiondbg/AArch64.TakeExceptionInDebugState
aarch64/debug/watchpoint/AArch64.WatchpointByteMatch
aarch64/debug/watchpoint/AArch64.WatchpointMatch
J1.1.2 aarch64/exceptions
aarch64/exceptions/aborts/AArch64.Abort
aarch64/exceptions/aborts/AArch64.AbortSyndrome
aarch64/exceptions/aborts/AArch64.CheckPCAlignment
aarch64/exceptions/aborts/AArch64.DataAbort
aarch64/exceptions/aborts/AArch64.InstructionAbort
aarch64/exceptions/aborts/AArch64.PCAlignmentFault
aarch64/exceptions/aborts/AArch64.SPAlignmentFault
aarch64/exceptions/asynch/AArch64.TakePhysicalFIQException
aarch64/exceptions/asynch/AArch64.TakePhysicalIRQException
aarch64/exceptions/asynch/AArch64.TakePhysicalSystemErrorException
aarch64/exceptions/asynch/AArch64.TakeVirtualFIQException
aarch64/exceptions/asynch/AArch64.TakeVirtualIRQException
aarch64/exceptions/asynch/AArch64.TakeVirtualSystemErrorException
aarch64/exceptions/debug/AArch64.BreakpointException
aarch64/exceptions/debug/AArch64.SoftwareBreakpoint
aarch64/exceptions/debug/AArch64.SoftwareStepException
aarch64/exceptions/debug/AArch64.VectorCatchException
aarch64/exceptions/debug/AArch64.WatchpointException
aarch64/exceptions/exceptions/AArch64.ExceptionClass
aarch64/exceptions/exceptions/AArch64.ReportException
aarch64/exceptions/exceptions/AArch64.ResetControlRegisters
aarch64/exceptions/exceptions/AArch64.TakeReset
aarch64/exceptions/ieeefp/AArch64.FPTrappedException
aarch64/exceptions/syscalls/AArch64.CallHypervisor
aarch64/exceptions/syscalls/AArch64.CallSecureMonitor
aarch64/exceptions/syscalls/AArch64.CallSupervisor
aarch64/exceptions/takeexception/AArch64.TakeException
aarch64/exceptions/traps/AArch64.AdvSIMDFPAccessTrap
aarch64/exceptions/traps/AArch64.CPRegTrap
aarch64/exceptions/traps/AArch64.CPRegTrapSyndrome
aarch64/exceptions/traps/AArch64.CheckCP15InstrCoarseTraps
aarch64/exceptions/traps/AArch64.CheckCoprocInstr
aarch64/exceptions/traps/AArch64.CheckCoprocInstrTraps
aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDEnabled
aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDTrap
aarch64/exceptions/traps/AArch64.CheckForSMCTrap
aarch64/exceptions/traps/AArch64.CheckForWFxTrap
aarch64/exceptions/traps/AArch64.CheckIllegalState
aarch64/exceptions/traps/AArch64.MonitorModeTrap
aarch64/exceptions/traps/AArch64.SystemRegisterTrap
aarch64/exceptions/traps/AArch64.UndefinedFault
aarch64/exceptions/traps/AArch64.WFxTrap
aarch64/exceptions/traps/CheckFPAdvSIMDEnabled64
J1.1.3 aarch64/functions
aarch64/functions/aborts/AArch64.CreateFaultRecord
aarch64/functions/exclusive/AArch64.ExclusiveMonitorsPass
aarch64/functions/exclusive/AArch64.IsExclusiveVA
aarch64/functions/exclusive/AArch64.MarkExclusiveVA
aarch64/functions/exclusive/AArch64.SetExclusiveMonitors
aarch64/functions/fusedrstep/FPRSqrtStepFused
aarch64/functions/fusedrstep/FPRecipStepFused
aarch64/functions/memory/AArch64.CheckAlignment
aarch64/functions/memory/AArch64.MemSingle
aarch64/functions/memory/CheckSPAlignment
aarch64/functions/memory/Mem
aarch64/functions/registers/AArch64.MaybeZeroRegisterUppers
aarch64/functions/registers/AArch64.ResetGeneralRegisters
aarch64/functions/registers/AArch64.ResetSIMDFPRegisters
aarch64/functions/registers/AArch64.ResetSpecialRegisters
aarch64/functions/registers/AArch64.ResetSystemRegisters
aarch64/functions/registers/PC
aarch64/functions/registers/SP
aarch64/functions/registers/V
aarch64/functions/registers/Vpart
aarch64/functions/registers/X
aarch64/functions/sysregisters/ELR
aarch64/functions/sysregisters/ESR
aarch64/functions/sysregisters/ESRType
aarch64/functions/sysregisters/FAR
aarch64/functions/sysregisters/MAIR
aarch64/functions/sysregisters/MAIRType
aarch64/functions/sysregisters/SCTLR
aarch64/functions/sysregisters/SCTLRType
aarch64/functions/sysregisters/VBAR
aarch64/functions/system/AArch64.CheckAdvSIMDFPSystemRegisterTraps
aarch64/functions/system/AArch64.CheckSystemRegisterTraps
aarch64/functions/system/AArch64.CheckUnallocatedSystemAccess
aarch64/functions/system/CheckSystemAccess
aarch64/functions/system/SysOp_R
aarch64/functions/system/SysOp_W
aarch64/functions/system/System_Get
aarch64/functions/system/System_Put
J1.1.4 aarch64/instrs
aarch64/instrs/branch/eret/AArch64.ExceptionReturn
aarch64/instrs/countop/CountOp
aarch64/instrs/extendreg/DecodeRegExtend
aarch64/instrs/extendreg/ExtendReg
aarch64/instrs/extendreg/ExtendType
aarch64/instrs/float/arithmetic/max-min/fpmaxminop/FPMaxMinOp
aarch64/instrs/float/arithmetic/unary/fpunaryop/FPUnaryOp
aarch64/instrs/float/convert/fpconvop/FPConvOp
aarch64/instrs/integer/bitfield/bfxpreferred/BFXPreferred
aarch64/instrs/integer/bitmasks/DecodeBitMasks
aarch64/instrs/integer/ins-ext/insert/movewide/movewideop/MoveWideOp
aarch64/instrs/integer/logical/movwpreferred/MoveWidePreferred
aarch64/instrs/integer/shiftreg/DecodeShift
aarch64/instrs/integer/shiftreg/ShiftReg
aarch64/instrs/integer/shiftreg/ShiftType
aarch64/instrs/logicalop/LogicalOp
aarch64/instrs/memory/memop/MemOp
aarch64/instrs/memory/prefetch/Prefetch
aarch64/instrs/system/barriers/barrierop/MemBarrierOp
aarch64/instrs/system/hints/syshintop/SystemHintOp
aarch64/instrs/system/register/cpsr/pstatefield/PSTATEField
aarch64/instrs/system/sysops/sysop/SysOp
aarch64/instrs/system/sysops/sysop/SystemOp
aarch64/instrs/vector/arithmetic/binary/uniform/logical/bsl-eor/vbitop/VBitOp
aarch64/instrs/vector/arithmetic/unary/cmp/compareop/CompareOp
aarch64/instrs/vector/crypto/enabled/CheckCryptoEnabled64
aarch64/instrs/vector/logical/immediateop/ImmediateOp
aarch64/instrs/vector/reduce/reduceop/Reduce
aarch64/instrs/vector/reduce/reduceop/ReduceOp
J1.1.5 aarch64/translation
aarch64/translation/attrs/AArch64.InstructionDevice
aarch64/translation/attrs/AArch64.S1AttrDecode
aarch64/translation/attrs/AArch64.TranslateAddressS1Off
aarch64/translation/checks/AArch64.CheckPermission
aarch64/translation/checks/AArch64.CheckS2Permission
aarch64/translation/debug/AArch64.CheckBreakpoint
aarch64/translation/debug/AArch64.CheckDebug
aarch64/translation/debug/AArch64.CheckWatchpoint
aarch64/translation/faults/AArch64.AccessFlagFault
aarch64/translation/faults/AArch64.AddressSizeFault
aarch64/translation/faults/AArch64.AlignmentFault
aarch64/translation/faults/AArch64.AsynchExternalAbort
aarch64/translation/faults/AArch64.DebugFault
aarch64/translation/faults/AArch64.NoFault
aarch64/translation/faults/AArch64.PermissionFault
aarch64/translation/faults/AArch64.TranslationFault
aarch64/translation/translation/AArch64.FirstStageTranslate
aarch64/translation/translation/AArch64.FullTranslate
aarch64/translation/translation/AArch64.SecondStageTranslate
aarch64/translation/translation/AArch64.SecondStageWalk
aarch64/translation/translation/AArch64.TranslateAddress
aarch64/translation/walk/AArch64.TranslationTableWalk
J1.2 Pseudocode for AArch32 operation
J1.2.1 aarch32/debug
aarch32/debug/VCRMatch/AArch32.VCRMatch
aarch32/debug/authentication/AArch32.SelfHostedSecurePrivilegedInvasiveDebugEna bled
aarch32/debug/breakpoint/AArch32.BreakpointMatch
aarch32/debug/breakpoint/AArch32.BreakpointValueMatch
aarch32/debug/breakpoint/AArch32.StateMatch
aarch32/debug/enables/AArch32.GenerateDebugExceptions
aarch32/debug/enables/AArch32.GenerateDebugExceptionsFrom
aarch32/debug/pmu/AArch32.CheckForPMUOverflow
aarch32/debug/pmu/AArch32.CountEvents
aarch32/debug/pmu/AArch32.ProfilingProhibited
aarch32/debug/takeexceptiondbg/AArch32.EnterHypModeInDebugState
aarch32/debug/takeexceptiondbg/AArch32.EnterModeInDebugState
aarch32/debug/takeexceptiondbg/AArch32.EnterMonitorModeInDebugState
aarch32/debug/watchpoint/AArch32.WatchpointByteMatch
aarch32/debug/watchpoint/AArch32.WatchpointMatch
J1.2.2 aarch32/exceptions
aarch32/exceptions/aborts/AArch32.Abort
aarch32/exceptions/aborts/AArch32.AbortSyndrome
aarch32/exceptions/aborts/AArch32.CheckPCAlignment
aarch32/exceptions/aborts/AArch32.ReportDataAbort
aarch32/exceptions/aborts/AArch32.ReportPrefetchAbort
aarch32/exceptions/aborts/AArch32.TakeDataAbortException
aarch32/exceptions/aborts/AArch32.TakePrefetchAbortException
aarch32/exceptions/asynch/AArch32.TakePhysicalAsynchAbortException
aarch32/exceptions/asynch/AArch32.TakePhysicalFIQException
aarch32/exceptions/asynch/AArch32.TakePhysicalIRQException
aarch32/exceptions/asynch/AArch32.TakeVirtualAsynchAbortException
aarch32/exceptions/asynch/AArch32.TakeVirtualFIQException
aarch32/exceptions/asynch/AArch32.TakeVirtualIRQException
aarch32/exceptions/debug/AArch32.SoftwareBreakpoint
aarch32/exceptions/debug/DebugException
aarch32/exceptions/exceptions/AArch32.ExceptionClass
aarch32/exceptions/exceptions/AArch32.GeneralExceptionsToAArch64
aarch32/exceptions/exceptions/AArch32.ReportHypEntry
aarch32/exceptions/exceptions/AArch32.ResetControlRegisters
aarch32/exceptions/exceptions/AArch32.TakeReset
aarch32/exceptions/exceptions/ExcVectorBase
aarch32/exceptions/ieeefp/AArch32.FPTrappedException
aarch32/exceptions/syscalls/AArch32.CallHypervisor
aarch32/exceptions/syscalls/AArch32.CallSupervisor
aarch32/exceptions/syscalls/AArch32.TakeHVCException
aarch32/exceptions/syscalls/AArch32.TakeSMCException
aarch32/exceptions/syscalls/AArch32.TakeSVCException
aarch32/exceptions/takeexception/AArch32.EnterHypMode
aarch32/exceptions/takeexception/AArch32.EnterMode
aarch32/exceptions/takeexception/AArch32.EnterMonitorMode
aarch32/exceptions/traps/AArch32.CPRegTrap
aarch32/exceptions/traps/AArch32.CPRegTrapSyndrome
aarch32/exceptions/traps/AArch32.CheckAdvSIMDOrFPEnabled
aarch32/exceptions/traps/AArch32.CheckFPAdvSIMDTrap
aarch32/exceptions/traps/AArch32.CheckForSMCTrap
aarch32/exceptions/traps/AArch32.CheckForWFxTrap
aarch32/exceptions/traps/AArch32.CheckITEnabled
aarch32/exceptions/traps/AArch32.CheckIllegalState
aarch32/exceptions/traps/AArch32.CheckSETENDEnabled
aarch32/exceptions/traps/AArch32.TakeHypTrapException
aarch32/exceptions/traps/AArch32.TakeMonitorTrapException
aarch32/exceptions/traps/AArch32.TakeUndefInstrException
aarch32/exceptions/traps/AArch32.UndefinedFault
J1.2.3 aarch32/functions
aarch32/functions/aborts/AArch32.CreateFaultRecord
aarch32/functions/aborts/AArch32.DomainValid
aarch32/functions/aborts/AArch32.FaultStatusLD
aarch32/functions/aborts/AArch32.FaultStatusSD
aarch32/functions/aborts/EncodeSDFSC
aarch32/functions/common/A32ExpandImm
aarch32/functions/common/A32ExpandImm_C
aarch32/functions/common/DecodeImmShift
aarch32/functions/common/DecodeRegShift
aarch32/functions/common/RRX
aarch32/functions/common/RRX_C
aarch32/functions/common/SRType
aarch32/functions/common/Shift
aarch32/functions/common/Shift_C
aarch32/functions/common/T32ExpandImm
aarch32/functions/common/T32ExpandImm_C
aarch32/functions/coproc/AArch32.CheckCP15InstrCoarseTraps
aarch32/functions/coproc/AArch32.CheckCoprocInstrTraps
aarch32/functions/coproc/CP14DebugInstrDecode
aarch32/functions/coproc/CP14JazelleInstrDecode
aarch32/functions/coproc/CP14TraceInstrDecode
aarch32/functions/coproc/CP15InstrDecode
aarch32/functions/coproc/Coproc_CanWriteAPSR
aarch32/functions/coproc/Coproc_CheckInstr
aarch32/functions/coproc/Coproc_DoneLoading
aarch32/functions/coproc/Coproc_DoneStoring
aarch32/functions/coproc/Coproc_GetOneWord
aarch32/functions/coproc/Coproc_GetTwoWords
aarch32/functions/coproc/Coproc_GetWordToStore
aarch32/functions/coproc/Coproc_InternalOperation
aarch32/functions/coproc/Coproc_SendLoadedWord
aarch32/functions/coproc/Coproc_SendOneWord
aarch32/functions/coproc/Coproc_SendTwoWords
aarch32/functions/exclusive/AArch32.ExclusiveMonitorsPass
aarch32/functions/exclusive/AArch32.IsExclusiveVA
aarch32/functions/exclusive/AArch32.MarkExclusiveVA
aarch32/functions/exclusive/AArch32.SetExclusiveMonitors
aarch32/functions/float/CheckAdvSIMDEnabled
aarch32/functions/float/CheckAdvSIMDOrVFPEnabled
aarch32/functions/float/CheckCryptoEnabled32
aarch32/functions/float/CheckVFPEnabled
aarch32/functions/float/FPHalvedSub
aarch32/functions/float/FPRSqrtStep
aarch32/functions/float/FPRecipStep
aarch32/functions/float/StandardFPSCRValue
aarch32/functions/memory/AArch32.CheckAlignment
aarch32/functions/memory/AArch32.MemSingle
aarch32/functions/memory/Hint_PreloadData
aarch32/functions/memory/Hint_PreloadDataForWrite
aarch32/functions/memory/Hint_PreloadInstr
aarch32/functions/memory/MemA
aarch32/functions/memory/MemO
aarch32/functions/memory/MemU
aarch32/functions/memory/MemU_unpriv
aarch32/functions/memory/Mem_with_type
aarch32/functions/registers/AArch32.ResetGeneralRegisters
aarch32/functions/registers/AArch32.ResetSIMDFPRegisters
aarch32/functions/registers/AArch32.ResetSpecialRegisters
aarch32/functions/registers/AArch32.ResetSystemRegisters
aarch32/functions/registers/ALUExceptionReturn
aarch32/functions/registers/ALUWritePC
aarch32/functions/registers/BXWritePC
aarch32/functions/registers/BranchWritePC
aarch32/functions/registers/D
aarch32/functions/registers/Din
aarch32/functions/registers/LR
aarch32/functions/registers/LoadWritePC
aarch32/functions/registers/LookUpRIndex
aarch32/functions/registers/Monitor_mode_registers
aarch32/functions/registers/PC
aarch32/functions/registers/PCStoreValue
aarch32/functions/registers/Q
aarch32/functions/registers/Qin
aarch32/functions/registers/R
aarch32/functions/registers/RBankSelect
aarch32/functions/registers/Rmode
aarch32/functions/registers/S
aarch32/functions/registers/SP
aarch32/functions/registers/_Dclone
aarch32/functions/system/AArch32.ExceptionReturn
aarch32/functions/system/AArch32.ITAdvance
aarch32/functions/system/AArch32.WriteMode
aarch32/functions/system/BadMode
aarch32/functions/system/BankedRegisterAccessValid
aarch32/functions/system/CPSRWriteByInstr
aarch32/functions/system/ConditionPassed
aarch32/functions/system/CurrentCond
aarch32/functions/system/InITBlock
aarch32/functions/system/LastInITBlock
aarch32/functions/system/SPSRWriteByInstr
aarch32/functions/system/SPSRaccessValid
aarch32/functions/system/SelectInstrSet
aarch32/functions/v6simd/Sat
aarch32/functions/v6simd/SignedSat
aarch32/functions/v6simd/UnsignedSat
J1.2.4 aarch32/translation
aarch32/translation/attrs/AArch32.DefaultTEXDecode
aarch32/translation/attrs/AArch32.InstructionDevice
aarch32/translation/attrs/AArch32.RemappedTEXDecode
aarch32/translation/attrs/AArch32.S1AttrDecode
aarch32/translation/attrs/AArch32.TranslateAddressS1Off
aarch32/translation/checks/AArch32.CheckDomain
aarch32/translation/checks/AArch32.CheckPermission
aarch32/translation/checks/AArch32.CheckS2Permission
aarch32/translation/debug/AArch32.CheckBreakpoint
aarch32/translation/debug/AArch32.CheckDebug
aarch32/translation/debug/AArch32.CheckVectorCatch
aarch32/translation/debug/AArch32.CheckWatchpoint
aarch32/translation/faults/AArch32.AccessFlagFault
aarch32/translation/faults/AArch32.AddressSizeFault
aarch32/translation/faults/AArch32.AlignmentFault
aarch32/translation/faults/AArch32.AsynchExternalAbort
aarch32/translation/faults/AArch32.DebugFault
aarch32/translation/faults/AArch32.DomainFault
aarch32/translation/faults/AArch32.NoFault
aarch32/translation/faults/AArch32.PermissionFault
aarch32/translation/faults/AArch32.TranslationFault
aarch32/translation/translation/AArch32.FirstStageTranslate
aarch32/translation/translation/AArch32.FullTranslate
aarch32/translation/translation/AArch32.SecondStageTranslate
aarch32/translation/translation/AArch32.SecondStageWalk
aarch32/translation/translation/AArch32.TranslateAddress
aarch32/translation/walk/AArch32.TranslationTableWalkLD
aarch32/translation/walk/AArch32.TranslationTableWalkSD
aarch32/translation/walk/RemapRegsHaveResetValues
J1.3 Shared pseudocode
J1.3.1 shared/debug
shared/debug/ClearStickyErrors/ClearStickyErrors
shared/debug/DebugTarget/DebugTarget
shared/debug/DebugTarget/DebugTargetFrom
shared/debug/DoubleLockStatus/DoubleLockStatus
shared/debug/FindWatchpoint/FindWatchpoint
shared/debug/authentication/AllowExternalDebugAccess
shared/debug/authentication/AllowExternalPMUAccess
shared/debug/authentication/Debug_authentication
shared/debug/authentication/ExternalInvasiveDebugEnabled
shared/debug/authentication/ExternalNoninvasiveDebugAllowed
shared/debug/authentication/ExternalNoninvasiveDebugEnabled
shared/debug/authentication/ExternalSecureInvasiveDebugEnabled
shared/debug/authentication/ExternalSecureNoninvasiveDebugEnabled
shared/debug/cti/CTI_SetEventLevel
shared/debug/cti/CTI_SignalEvent
shared/debug/cti/CrossTrigger
shared/debug/dccanditr/CheckForDCCInterrupts
shared/debug/dccanditr/DBGDTRRX_EL0
shared/debug/dccanditr/DBGDTRTX_EL0
shared/debug/dccanditr/DBGDTR_EL0
shared/debug/dccanditr/DTR
shared/debug/dccanditr/EDITR
shared/debug/halting/DCPSInstruction
shared/debug/halting/DRPSInstruction
shared/debug/halting/DebugHalt
shared/debug/halting/DisableITRAndResumeInstructionPrefetch
shared/debug/halting/ExecuteA64
shared/debug/halting/ExecuteT32
shared/debug/halting/ExitDebugState
shared/debug/halting/Halt
shared/debug/halting/HaltOnBreakpointOrWatchpoint
shared/debug/halting/Halted
shared/debug/halting/HaltingAllowed
shared/debug/halting/Restarting
shared/debug/halting/StopInstructionPrefetchAndEnableITR
shared/debug/halting/UpdateEDSCRFields
shared/debug/haltingevents/CheckExceptionCatch
shared/debug/haltingevents/CheckHaltingStep
shared/debug/haltingevents/CheckOSUnlockCatch
shared/debug/haltingevents/CheckPendingOSUnlockCatch
shared/debug/haltingevents/CheckPendingResetCatch
shared/debug/haltingevents/CheckResetCatch
shared/debug/haltingevents/CheckSoftwareAccessToDebugRegisters
shared/debug/haltingevents/ExternalDebugRequest
shared/debug/haltingevents/HaltingStep_DidNotStep
shared/debug/haltingevents/HaltingStep_SteppedEX
shared/debug/haltingevents/RunHaltingStep
shared/debug/interrupts/InterruptID
shared/debug/interrupts/SetInterruptRequestLevel
shared/debug/samplebasedprofiling/CreatePCSample
shared/debug/samplebasedprofiling/EDPCSRlo
shared/debug/samplebasedprofiling/PCSample
shared/debug/softwarestep/CheckSoftwareStep
shared/debug/softwarestep/DebugExceptionReturnSS
shared/debug/softwarestep/SSAdvance
shared/debug/softwarestep/SoftwareStep_DidNotStep
shared/debug/softwarestep/SoftwareStep_SteppedEX
J1.3.2 shared/exceptions
shared/exceptions/exceptions/Exception
shared/exceptions/exceptions/ExceptionRecord
shared/exceptions/exceptions/ExceptionSyndrome
shared/exceptions/traps/ReservedValue
shared/exceptions/traps/UnallocatedEncoding
J1.3.3 shared/functions
shared/functions/aborts/EncodeLDFSC
shared/functions/aborts/FaultSyndrome
shared/functions/aborts/IPAValid
shared/functions/aborts/IsAsyncAbort
shared/functions/aborts/IsDebugException
shared/functions/aborts/IsExternalAbort
shared/functions/aborts/IsFault
shared/functions/aborts/IsSecondStage
shared/functions/aborts/LSInstructionSyndrome
shared/functions/common/ASR
shared/functions/common/ASR_C
shared/functions/common/Abs
shared/functions/common/Align
shared/functions/common/BitCount
shared/functions/common/CountLeadingSignBits
shared/functions/common/CountLeadingZeroBits
shared/functions/common/Elem
shared/functions/common/Extend
shared/functions/common/HighestSetBit
shared/functions/common/Int
shared/functions/common/IsOnes
shared/functions/common/IsZero
shared/functions/common/IsZeroBit
shared/functions/common/LSL
shared/functions/common/LSL_C
shared/functions/common/LSR
shared/functions/common/LSR_C
shared/functions/common/LowestSetBit
shared/functions/common/Max
shared/functions/common/Min
shared/functions/common/NOT
shared/functions/common/Ones
shared/functions/common/ROR
shared/functions/common/ROR_C
shared/functions/common/Replicate
shared/functions/common/RoundDown
shared/functions/common/RoundTowardsZero
shared/functions/common/RoundUp
shared/functions/common/SInt
shared/functions/common/SignExtend
shared/functions/common/UInt
shared/functions/common/ZeroExtend
shared/functions/common/Zeros
shared/functions/crc/BitReverse
shared/functions/crc/HaveCRCExt
shared/functions/crc/Poly32Mod2
shared/functions/crypto/AESInvMixColumns
shared/functions/crypto/AESInvShiftRows
shared/functions/crypto/AESInvSubBytes
shared/functions/crypto/AESMixColumns
shared/functions/crypto/AESShiftRows
shared/functions/crypto/AESSubBytes
shared/functions/crypto/HaveCryptoExt
shared/functions/crypto/ROL
shared/functions/crypto/SHA256hash
shared/functions/crypto/SHAchoose
shared/functions/crypto/SHAhashSIGMA0
shared/functions/crypto/SHAhashSIGMA1
shared/functions/crypto/SHAmajority
shared/functions/crypto/SHAparity
shared/functions/exclusive/ClearExclusiveByAddress
shared/functions/exclusive/ClearExclusiveLocal
shared/functions/exclusive/ClearExclusiveMonitors
shared/functions/exclusive/ExclusiveMonitorsStatus
shared/functions/exclusive/IsExclusiveGlobal
shared/functions/exclusive/IsExclusiveLocal
shared/functions/exclusive/MarkExclusiveGlobal
shared/functions/exclusive/MarkExclusiveLocal
shared/functions/exclusive/ProcessorID
shared/functions/float/fixedtofp/FixedToFP
shared/functions/float/fpabs/FPAbs
shared/functions/float/fpadd/FPAdd
shared/functions/float/fpcompare/FPCompare
shared/functions/float/fpcompareeq/FPCompareEQ
shared/functions/float/fpcomparege/FPCompareGE
shared/functions/float/fpcomparegt/FPCompareGT
shared/functions/float/fpconvert/FPConvert
shared/functions/float/fpconvertnan/FPConvertNaN
shared/functions/float/fpcrtype/FPCRType
shared/functions/float/fpdecoderm/FPDecodeRM
shared/functions/float/fpdecoderounding/FPDecodeRounding
shared/functions/float/fpdefaultnan/FPDefaultNaN
shared/functions/float/fpdiv/FPDiv
shared/functions/float/fpexc/FPExc
shared/functions/float/fpinfinity/FPInfinity
shared/functions/float/fpmax/FPMax
shared/functions/float/fpmaxnormal/FPMaxNormal
shared/functions/float/fpmaxnum/FPMaxNum
shared/functions/float/fpmin/FPMin
shared/functions/float/fpminnum/FPMinNum
shared/functions/float/fpmul/FPMul
shared/functions/float/fpmuladd/FPMulAdd
shared/functions/float/fpmulx/FPMulX
shared/functions/float/fpneg/FPNeg
shared/functions/float/fponepointfive/FPOnePointFive
shared/functions/float/fpprocessexception/FPProcessException
shared/functions/float/fpprocessnan/FPProcessNaN
shared/functions/float/fpprocessnans/FPProcessNaNs
shared/functions/float/fpprocessnans3/FPProcessNaNs3
shared/functions/float/fprecipestimate/FPRecipEstimate
shared/functions/float/fprecpx/FPRecpX
shared/functions/float/fpround/FPRound
shared/functions/float/fprounding/FPRounding
shared/functions/float/fproundingmode/FPRoundingMode
shared/functions/float/fproundint/FPRoundInt
shared/functions/float/fprsqrtestimate/FPRSqrtEstimate
shared/functions/float/fpsqrt/FPSqrt
shared/functions/float/fpsub/FPSub
shared/functions/float/fpthree/FPThree
shared/functions/float/fptofixed/FPToFixed
shared/functions/float/fptwo/FPTwo
shared/functions/float/fptype/FPType
shared/functions/float/fpunpack/FPUnpack
shared/functions/float/fpzero/FPZero
shared/functions/float/vfpexpandimm/VFPExpandImm
shared/functions/integer/AddWithCarry
shared/functions/memory/AccType
shared/functions/memory/AddrTop
shared/functions/memory/AddressDescriptor
shared/functions/memory/Allocation
shared/functions/memory/BigEndian
shared/functions/memory/BigEndianReverse
shared/functions/memory/BranchAddr
shared/functions/memory/Cacheability
shared/functions/memory/DataMemoryBarrier
shared/functions/memory/DataSynchronizationBarrier
shared/functions/memory/DeviceType
shared/functions/memory/Fault
shared/functions/memory/FaultRecord
shared/functions/memory/FullAddress
shared/functions/memory/Hint_Prefetch
shared/functions/memory/MBReqDomain
shared/functions/memory/MBReqTypes
shared/functions/memory/MemAttrHints
shared/functions/memory/MemType
shared/functions/memory/MemoryAttributes
shared/functions/memory/Permissions
shared/functions/memory/PrefetchHint
shared/functions/memory/TLBRecord
shared/functions/memory/_Mem
shared/functions/registers/BranchTo
shared/functions/registers/BranchToAddr
shared/functions/registers/BranchType
shared/functions/registers/Hint_Branch
shared/functions/registers/NextInstrAddr
shared/functions/registers/ResetExternalDebugRegisters
shared/functions/registers/ThisInstrAddr
shared/functions/registers/_PC
shared/functions/registers/_R
shared/functions/registers/_V
shared/functions/sysregisters/SPSR
shared/functions/system/ArchVersion
shared/functions/system/ClearEventRegister
shared/functions/system/ConditionHolds
shared/functions/system/CurrentInstrSet
shared/functions/system/CurrentPL
shared/functions/system/EL0
shared/functions/system/ELFromM32
shared/functions/system/ELFromSPSR
shared/functions/system/ELStateUsingAArch32
shared/functions/system/ELStateUsingAArch32K
shared/functions/system/ELUsingAArch32
shared/functions/system/ELUsingAArch32K
shared/functions/system/EndOfInstruction
shared/functions/system/EventRegisterSet
shared/functions/system/EventRegistered
shared/functions/system/GetPSRFromPSTATE
shared/functions/system/HasArchVersion
shared/functions/system/HaveAArch32EL
shared/functions/system/HaveAnyAArch32
shared/functions/system/HaveEL
shared/functions/system/HighestEL
shared/functions/system/HighestELUsingAArch32
shared/functions/system/Hint_Debug
shared/functions/system/Hint_Yield
shared/functions/system/IllegalExceptionReturn
shared/functions/system/InstrSet
shared/functions/system/InstructionSynchronizationBarrier
shared/functions/system/InterruptPending
shared/functions/system/IsSecure
shared/functions/system/IsSecureBelowEL3
shared/functions/system/Mode_Bits
shared/functions/system/PLOfEL
shared/functions/system/PSTATE
shared/functions/system/PrivilegeLevel
shared/functions/system/ProcState
shared/functions/system/RestoredITBits
shared/functions/system/SCRType
shared/functions/system/SCR_GEN
shared/functions/system/SendEvent
shared/functions/system/SetPSTATEFromPSR
shared/functions/system/SynchronizeContext
shared/functions/system/ThisInstr
shared/functions/system/ThisInstrLength
shared/functions/system/Unreachable
shared/functions/system/UsingAArch32
shared/functions/system/WaitForEvent
shared/functions/system/WaitForInterrupt
shared/functions/unpredictable/ConstrainUnpredictable
shared/functions/unpredictable/ConstrainUnpredictableBits
shared/functions/unpredictable/ConstrainUnpredictableBool
shared/functions/unpredictable/ConstrainUnpredictableInteger
shared/functions/unpredictable/Constraint
shared/functions/vector/AdvSIMDExpandImm
shared/functions/vector/PolynomialMult
shared/functions/vector/SatQ
shared/functions/vector/SignedSatQ
shared/functions/vector/UnsignedRSqrtEstimate
shared/functions/vector/UnsignedRecipEstimate
shared/functions/vector/UnsignedSatQ
J1.3.4 shared/translation
shared/translation/attrs/CombineS1S2AttrHints
shared/translation/attrs/CombineS1S2Desc
shared/translation/attrs/CombineS1S2Device
shared/translation/attrs/LongConvertAttrsHints
shared/translation/attrs/MemAttrDefaults
shared/translation/attrs/S1CacheDisabled
shared/translation/attrs/S2AttrDecode
shared/translation/attrs/S2CacheDisabled
shared/translation/attrs/S2ConvertAttrsHints
shared/translation/attrs/ShortConvertAttrsHints
shared/translation/attrs/WalkAttrDecode
shared/translation/translation/PAMax
shared/translation/translation/S1TranslationRegime
Part K: Appendixes
K1: Architectural Constraints on UNPREDICTABLE behaviors
K1.1 AArch32 CONSTRAINED UNPREDICTABLE behaviors
K1.1.1 Overview of the constraints on ARMv7 UNPREDICTABLE behaviors
K1.1.2 Using R13
K1.1.3 Using R15
K1.1.4 Branching into an IT block
K1.1.5 Branching to an unaligned PC
K1.1.6 Loads and Stores to unaligned locations
K1.1.7 CONSTRAINED UNPREDICTABLE behavior associated with IT instructions and PSTATE.IT
K1.1.8 Unallocated CP14 and CP15 instructions
K1.1.9 SBZ or SBO fields in instructions
K1.1.10 UNPREDICTABLE cases in immediate constants in T32 data-processing instructions
K1.1.11 UNPREDICTABLE cases in immediate constants in Advanced SIMD instructions
K1.1.12 CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values
K1.1.13 CONSTRAINED UNPREDICTABLE behavior due to inadequate context synchronization
K1.1.14 Translation Table Base Address alignment
K1.1.15 Handling of conceptual coprocessors CP10 and CP11
CONSTRAINED UNPREDICTABLE CPACR and NSACR settings
K1.1.16 The Performance Monitors Extension
CONSTRAINED UNPREDICTABLE accesses to PMXEVTYPER or PMXEVCNTR
CONSTRAINED UNPREDICTABLE accesses to PMEVCNTR and PMEVTYPER
CONSTRAINED UNPREDICTABLE behavior caused by HDCR.HPMN
K1.1.17 Syndrome register handling for CONSTRAINED UNPREDICTABLE instructions treated as UNDEFINED
K1.1.18 Out of range virtual address
K1.1.19 Instruction fetches from Device memory
K1.1.20 Multi-access instructions that load the PC from Device memory
K1.1.21 Programming CSSELR.Level for a cache level that is not implemented
K1.1.22 Crossing a page boundary with different memory types or Shareability attributes
K1.1.23 Crossing a 4KB boundary with a Device access
K1.1.24 CONSTRAINED UNPREDICTABLE behavior for A32 memory hints, Advanced SIMD instructions, and miscellaneous instructions
K1.1.25 Out of range values of the Set/Way/Index fields in cache maintenance instructions
K1.1.26 CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instructions in the base instruction set
BFC
BFI
BKPT
CLZ
CMP (register)
CRC32, CRC32C
HLT
IT
LDAEX
LDAEXB
LDAEXD
LDAEXH
LDC/LDC2 (literal)
LDM/LDMIA/LDMFD (A32)
LDM/LDMIA/LDMFD (T32)
LDMDA/LDMFA
LDMIB/LDMED
LDMDB/LDMEA
LDR (immediate, A32)
LDR (immediate, T32)
LDR (literal)
LDR (register, A32)
LDRB (immediate, A32)
LDRB (immediate, T32)
LDRB (literal)
LDRB (register)
LDRBT
LDRD (immediate)
LDRD (literal)
LDRD (register)
LDREX
LDREXB
LDREXD
LDREXH
LDRH (immediate, A32)
LDRH (immediate, T32)
LDRH (literal)
LDRH (register)
LDRHT
LDRSB (immediate)
LDRSB (literal)
LDRSB (register)
LDRSBT
LDRSH (immediate)
LDRSH (literal)
LDRSH (register)
LDRSHT
LDRT
MOV (register, T32)
MRRC, MRRC2
MSR (register)
POP (A32)
POP (T32)
PUSH
RBIT
REV
REV16
REVSH
SBFX
SDIV
SMLAL
SMLALBB, SMLALBT, SMLALTB, SMLALTT
SMLALD
SMLSLD
SMULL
STC, STC2
STLEX
STLEXB
STLEXD
STLEXH
STM (STMIA, STMEA)
STMDB (STMFD)
STMDA (STMED)
STMIB (STMFA)
STR (immediate, A32)
STR (immediate, T32)
STR (register)
STRB (immediate, A32)
STRB (immediate), T32
STRB (register)
STRBT
STRD (immediate)
STRD (register)
STREX
STREXB
STREXD
STREXH
STRH (immediate, A32)
STRH (immediate, T32)
STRH (register)
STRHT
STRT
UBFX
UDIV
UMAAL
UMLAL
UMULL
K1.1.27 CONSTRAINED UNPREDICTABLE behavior for A32 and T32 system instructions in the base instruction set
CPS (A32)
CPS (T32)
LDM (exception return)
LDM (User registers)
MRS
MSR (immediate)
MSR (register)
RFE
SRS (T32)
SRS (A32)
STM (User registers)
SUBS PC, LR and related instructions (T32)
SUBS PC. LR and related instructions (A32)
K1.1.28 CONSTRAINED UNPREDICTABLE behavior, A32 and T32 Advanced SIMD and floating-point instructions
VCVT (between floating-point and fixed-point)
VLD1 (multiple single elements)
VLD1 (single element to all lanes)
VLD2 (multiple 2-element structures)
VLD2 (single 2-element structure to one lane)
VLD2 (single 2-element structure to all lanes)
VLD3 (multiple 3-element structures)
VLD3 (single 3-element structure to one lane)
VLD3 (single 3-element structure to all lanes)
VLD4 (multiple 4-element structures)
VLD4 (single 4-element structure to one lane)
VLD4 (single 4-element structure to all lanes)
VLDM
VMOV (between two general-purpose registers and two single-precision registers)
VMOV (between two general-purpose registers and a doubleword floating-point register)
VMRS
VMSR
VPOP
VPUSH
VST1 (multiple single elements)
VST2 (multiple 2-element structures)
VST2 (single 2-element structure from one lane)
VST3 (multiple 3-element structures)
VST3 (single 3-element structure from one lane)
VST4 (multiple 4-element structures)
VST4 (single 4-element structure from one lane)
VSTM
VTBL, VTBX
K1.1.29 CONSTRAINED UNPREDICTABLE behaviors associated with the VTCR
Misprogramming VTCR.S
CONSTRAINED UNPREDICTABLE combinations of the starting level and size fields
K1.1.30 CONSTRAINED UNPREDICTABLE behavior of EL2 features
ERET in User mode or System mode
Accessing Hyp mode from outside Hyp mode
Modifying PSTATE.M when in Hyp mode
Use of Hyp mode in Secure state
Execution of Load/Store unprivileged instructions in Hyp mode
Exception return to Hyp mode
Accessing registers that cannot be accessed using MSR/MRS instructions
Memory type handling
Hyp mode TLB maintenance instructions
Hyp mode VA to PA address translation instructions
Stage 1 default memory type
Trapping of general exceptions to Hyp mode
Prevention of rootskits using Hyp mode or Secure state
HVC
MSR/MRS Banked registers
K1.1.31 Reserved values in System and memory-mapped registers and translation table entries
K1.1.32 CONSTRAINED UNPREDICTABLE behavior in Debug state
K1.2 AArch64 CONSTRAINED UNPREDICTABLE behaviors
K1.2.1 Overview of the constraints on AArch64 UNPREDICTABLE behaviors
K1.2.2 CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values
K1.2.3 CONSTRAINED UNPREDICTABLE behavior due to inadequate context synchronization
K1.2.4 Translation table base address alignment
K1.2.5 The Performance Monitors Extension
K1.2.6 Syndrome register handling for CONSTRAINED UNPREDICTABLE instructions treated as UNDEFINED
K1.2.7 Out of range virtual address
K1.2.8 Instruction fetches from Device memory
K1.2.9 Programming the CSSELR_EL1.Level for a cache level that is not implemented
K1.2.10 Crossing a page boundary with different memory types or Shareability attributes
K1.2.11 Crossing a peripheral boundary with a Device access
K1.2.12 CONSTRAINED UNPREDICTABLE behaviors associated with the VTCR_EL2
K1.2.13 CONSTRAINED UNPREDICTABLE behavior for A64 instructions
LDAXP
LDNP (SIMD&FP)
LDP
LDP (SIMD&FP)
LDPSW
LDR (immediate)
LDRB (immediate)
LDRH (immediate)
LDRSB (immediate)
LDRSH (immediate)
LDRSW (immediate)
LDXP
STP
STLXP
STLXR
STLXRB
STLXRH
STR (immediate)
STRB (immediate)
STRH (immediate)
STXP
STXR
STXRB
STXRH
K1.2.14 Out of range values of the Set/Way/Index fields in cache maintenance instructions
K1.2.15 Reserved values in System and memory-mapped registers and translation table entries
K1.2.16 Setting the value of EDECR.SS to 1 when not in Debug state
K1.2.17 CONSTRAINED UNPREDICTABLE behavior in Debug state
K2: Recommended External Debug Interface
K2.1 About the recommended external debug interface
K2.2 PMUEVENT bus
K2.3 Recommended authentication interface
K2.4 Management registers and CoreSight compliance
K2.4.1 Coresight interface register map
K2.4.2 Management register access permissions
K2.4.3 Management register resets
K3: Recommendations for Performance Monitors Event Numbers for IMPLEMENTATION DEFINED Events
K3.1 ARM recommendations for IMPLEMENTATION DEFINED event numbers
K3.1.1 Relationship between REFILL events and associated access events.
K3.2 Summary of events for exceptions taken to an Exception Level using AArch64
K4: Recommendations for reporting memory attributes on an interconnect
K4.1 ARM recommendations for reporting memory attributes on an interconnect
K4.1.1 Effect of microarchitectural choices on memory attributes
Effect when the cache is disabled
K5: ARMv8 Changes to the T32 and A32 Instruction Sets
K5.1 The A32 and T32 instruction sets
K5.2 Partial deprecation of IT
K5.3 New A32 and T32 Load-Acquire/Store-Release instructions
K5.3.1 A32 and T32 Load-Acquire/Store-Release (non-exclusive) instructions
K5.3.2 A32 and T32 Load-Acquire/Store-Release Exclusive instructions
K5.4 New A32 and T32 scalar floating-point instructions
K5.4.1 A32 and T32 floating-point conditional select
K5.4.2 A32 and T32 floating-point minimum and maximum numeric
K5.4.3 A32 and T32 floating-point to integer conversion
K5.4.4 A32 and T32 floating-point conversion between half-precision and double-precision
K5.4.5 A32 and T32 floating-point round to integer
K5.5 New A32 and T32 Advanced SIMD floating-point instructions
K5.5.1 A32 and T32 floating-point minimum and maximum numeric
K5.5.2 A32 and T32 floating-point conversion
K5.5.3 A32 and T32 floating-point round to integral
K5.6 New A32 and T32 instructions provided by the Cryptographic Extension
K5.7 New A32 and T32 System instructions
K5.7.1 External Debug
K5.7.2 Barriers and hints
K5.7.3 TLB Maintenance
K5.8 CRC32 instructions
K6: Legacy Instruction Syntax for AArch32 Instruction Sets
K6.1 Legacy Instruction Syntax
K6.1.1 Pre-UAL instruction syntax for the A32 base instructions
K6.1.2 Pre-UAL instruction syntax for the A32 floating-point instructions
K6.1.3 FCONST
K7: Address translation examples
K7.1 AArch64 Address translation examples
K7.1.1 Examples of performing the initial lookup
Performing the initial lookup using the 4KB translation granule
Performing the initial lookup using the 16KB granule
Performing the initial lookup using the 64KB translation granule
K7.1.2 Full translation flows for VMSAv8-64 address translation
The address and properties fields shown in the translation flows
Full translation flow using the 4KB granule and starting at level 0
Full translation flow using the 4KB granule and starting at level 1
Full translation flow using the 64KB granule and starting at level 1
Full translation flow using the 64KB granule and starting at level 2
K7.2 AArch32 Address translation examples
K7.2.1 Address translation examples using the VMSAv8-32 Short descriptor translation table format
Translation flow for a Supersection
Translation flow for a Section
Translation flow for a Large page
Translation flow for a Small page
The address and Properties fields shown in the translation flows
K7.2.2 Address translation examples using the VMSAv8-32 Long descriptor translation table format
Full translation flow, starting at level 1 lookup
Full translation flow, starting at level 2 lookup
The address and Properties fields shown in the translation flows
K8: Example OS Save and Restore Sequences
K8.1 Save Debug registers
K8.2 Restore Debug registers
K9: Recommended Upload and Download Processes for External Debug
K9.1 Using memory access mode in AArch64 state
K10: Barrier Litmus Tests
K10.1 Introduction
K10.1.1 Overview of memory consistency
K10.1.2 Barrier operation definitions
K10.1.3 Conventions
K10.2 Load-Acquire, Store-Release and barriers
K10.2.1 Message passing
Resolving weakly-ordered message passing by using Acquire and Release
Resolving message passing by the use of Store-Release and address dependency
K10.2.2 Address dependency with object construction
K10.2.3 Causal consistency issues with multiple observers
Using multi-copy atomicity of the Store-Release when observed by Load-Acquire
Using ordering property of Store-Release on stores observed by the PE
K10.2.4 Multiple observers of writes to multiple locations
K10.2.5 WFE and WFI and barriers
K10.3 Load-Acquire Exclusive, Store-Release Exclusive and barriers
K10.3.1 Acquiring a lock
K10.3.2 Releasing a lock
K10.3.3 Ticket locks
K10.3.4 Use of Wait For Event (WFE) and Send Event (SEV) with locks
Simple lock
Ticket lock
K10.4 Using a mailbox to send an interrupt
K10.5 Cache and TLB maintenance instructions and barriers
K10.5.1 Data cache maintenance instructions
Message passing to non-caching observers
Multiprocessing message passing to non-caching observers
Invalidating DMA buffers, non-functional example
Invalidating DMA buffers, functional example with single PE
Invalidating DMA buffers, functional example with multiple coherent PEs
K10.5.2 Instruction cache maintenance instructions
Ensuring the visibility of updates to instructions for a uniprocessor
Ensuring the visibility of updates to instructions for a multiprocessor
K10.5.3 TLB maintenance instructions and barriers
Ensuring the visibility of updates to translation tables for a uniprocessor
Ensuring the visibility of updates to translation tables for a multiprocessor
Paging memory in and out
Break-before-make updates to translation table entries
K10.5.4 Ordering of Memory-mapped device control with payloads
K10.6 ARMv7 compatible approaches for ordering, using DMB and DSB barriers
K10.6.1 Simple ordering and barrier cases
Simple weakly consistent ordering example
Message passing
Address dependency with object construction
Causal consistency issues with multiple observers
Multiple observers of writes to multiple locations
Posting a store before polling for acknowledgement
WFE and WFI and barriers
K10.6.2 Load-Exclusive, Store-Exclusive and barriers
Acquiring a lock
Releasing a lock
Use of Wait For Event (WFE) and Send Event (SEV) with locks
K10.6.3 Using a mailbox to send an interrupt
K10.6.4 Cache and TLB maintenance instructions and barriers
Data cache maintenance instructions
Instruction cache maintenance instructions
TLB maintenance instructions and barriers
K11: ARM Pseudocode Definition
K11.1 About the ARM pseudocode
K11.1.1 General limitations of ARM pseudocode
K11.2 Pseudocode for instruction descriptions
K11.2.1 Instruction encoding diagrams and instruction pseudocode
K11.2.2 Limitations of the instruction pseudocode
K11.3 Data types
K11.3.1 General data type rules
K11.3.2 Bitstrings
Syntax
Description
K11.3.3 Integers
Syntax
Description
K11.3.4 Reals
Syntax
Description
K11.3.5 Booleans
Syntax
Description
K11.3.6 Enumerations
Syntax and examples
Description
K11.3.7 Structures
Syntax and examples
Description
K11.3.8 Tuples
Examples
Description
K11.3.9 Arrays
Syntax
Description
K11.4 Operators
K11.4.1 Relational operators
Equality and non-equality
Comparisons
Set membership with IN
K11.4.2 Boolean operators
K11.4.3 Bitstring operators
Logical operations on bitstrings
Bitstring concatenation and slicing
K11.4.4 Arithmetic operators
Unary plus and minus
Addition and subtraction
Multiplication
Division and modulo
Scaling
Raising to a power
K11.4.5 The assignment operator
General expression syntax
K11.4.6 Precedence rules
K11.4.7 Conditional expressions
K11.4.8 Operator polymorphism
K11.5 Statements and control structures
K11.5.1 Statements and Indentation
K11.5.2 Function and procedure calls
Procedure and function definitions
Procedure calls
Return statements
K11.5.3 Conditional control structures
if … then … else …
case … of …
K11.5.4 Loop control structures
repeat … until …
while … do
for …
K11.5.5 Special statements
UNDEFINED
UNPREDICTABLE
SEE…
IMPLEMENTATION_DEFINED
K11.5.6 Comments
K11.6 Built-in functions
K11.6.1 Bitstring manipulation functions
Bitstring length and most significant bit
Bitstring concatenation and replication
Bitstring count
Testing a bitstring for being all zero or all ones
Lowest and highest set bits of a bitstring
Zero-extension and sign-extension of bitstrings
Converting bitstrings to integers
K11.6.2 Arithmetic functions
Absolute value
Rounding and aligning
Maximum and minimum
K11.7 Miscellaneous helper procedures and functions
K11.7.1 EndOfInstruction()
K11.7.2 Hint_Debug()
K11.7.3 Hint_PreloadData()
K11.7.4 Hint_PreloadDataForWrite()
K11.7.5 Hint_PreloadInstr()
K11.7.6 Hint_Yield()
K11.7.7 IsExternalAbort()
K11.7.8 IsAsyncAbort()
K11.7.9 LSInstructionSyndrome()
K11.7.10 ProcessorID()
K11.7.11 RemapRegsHaveResetValues()
K11.7.12 ResetControlRegisters()
K11.7.13 ThisInstr()
K11.7.14 ThisInstrLength()
K11.8 ARM pseudocode definition index
K12: Pseudocode Index
K12.1 Pseudocode operators and keywords
K12.2 Pseudocode index
K13: Registers Index
K13.1 Introduction and register disambiguation
K13.1.1 Register name disambiguation by Execution state
K13.1.2 Register name disambiguation by Exception level
K13.2 Alphabetical index of AArch64 registers and system instructions
K13.3 Functional index of AArch64 registers and system instructions
K13.3.1 Special-purpose registers
K13.3.2 VMSA-specific registers
K13.3.3 ID registers
K13.3.4 Performance monitors registers
K13.3.5 Debug registers
K13.3.6 Generic timer registers
K13.3.7 Cache maintenance system instructions
K13.3.8 Address translation system instructions
K13.3.9 TLB maintenance system instructions
K13.3.10 Base system registers
K13.4 Alphabetical index of AArch32 registers and system instructions
K13.5 Functional index of AArch32 registers and system instructions
K13.5.1 Special-purpose registers
K13.5.2 VMSA-specific registers
K13.5.3 ID registers
K13.5.4 Performance monitors registers
K13.5.5 Debug registers
K13.5.6 Generic timer registers
K13.5.7 Cache maintenance system instructions
K13.5.8 Address translation system instructions
K13.5.9 TLB maintenance system instructions
K13.5.10 Legacy feature registers and system instructions
K13.5.11 Base system registers
K13.6 Alphabetical index of memory-mapped registers
K13.7 Functional index of memory-mapped registers
K13.7.1 ID registers
K13.7.2 Performance monitors registers
K13.7.3 Debug registers
K13.7.4 Cross-trigger interface registers
Glossary
ARM® Architecture Reference Manual
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have only a minimal introduction.
Appendix K11 ARM Pseudocode Definition has been updated and extensively restructured. These changes have
had very limited review.
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iii
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Contents
ARM Architecture Reference Manual ARMv8, for
ARMv8-A architecture profile
Preface
About this manual ..................................................................................................... xvi
Using this manual .................................................................................................... xviii
Conventions ............................................................................................................ xxiii
Additional reading .................................................................................................... xxv
Feedback ................................................................................................................ xxvi
ARMv8 Architecture Introduction and Overview
Introduction to the ARMv8 Architecture
A1.1
A1.2
A1.3
A1.4
A1.5
A1.6
A1.7
About the ARM architecture ................................................................................ A1-30
Architecture profiles ............................................................................................ A1-32
ARMv8 architectural concepts ............................................................................ A1-33
Supported data types .......................................................................................... A1-36
Floating-point and Advanced SIMD support ....................................................... A1-46
Cryptographic Extension ..................................................................................... A1-52
The ARM memory model .................................................................................... A1-53
The AArch64 Application Level Architecture
The AArch64 Application Level Programmers’ Model
B1.1
B1.2
B1.3
About the Application level programmers’ model ................................................ B1-58
Registers in AArch64 Execution state ................................................................. B1-59
Software control features and EL0 ...................................................................... B1-64
Part A
Chapter A1
Part B
Chapter B1
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v
Contents
Chapter B2
Part C
Chapter C1
Chapter C2
Chapter C3
Chapter C4
Chapter C5
Chapter C6
The AArch64 Application Level Memory Model
Address space .................................................................................................... B2-68
B2.1
Memory type overview ........................................................................................ B2-69
B2.2
Caches and memory hierarchy ........................................................................... B2-70
B2.3
Alignment support ............................................................................................... B2-75
B2.4
Endian support .................................................................................................... B2-77
B2.5
Atomicity in the ARM architecture ....................................................................... B2-80
B2.6
Memory ordering ................................................................................................. B2-83
B2.7
Memory types and attributes ............................................................................... B2-93
B2.8
Mismatched memory attributes ......................................................................... B2-104
B2.9
B2.10 Synchronization and semaphores ..................................................................... B2-107
The AArch64 Instruction Set
The A64 Instruction Set
C1.1
C1.2
C1.3
C1.4
Introduction ....................................................................................................... C1-120
Structure of the A64 assembler language ......................................................... C1-121
Address generation ........................................................................................... C1-126
Instruction aliases ............................................................................................. C1-129
About the A64 Instruction Descriptions
C2.1
C2.2
Understanding the A64 instruction descriptions ................................................ C2-132
Conventions used in AArch64 instruction and System register descriptions .... C2-135
A64 Instruction Set Overview
C3.1
C3.2
C3.3
C3.4
C3.5
Branches, Exception generating, and System instructions ............................... C3-138
Loads and stores ............................................................................................... C3-142
Data processing - immediate ............................................................................ C3-153
Data processing - register ................................................................................. C3-158
Data processing - SIMD and floating-point ....................................................... C3-165
A64 Instruction Set Encoding
C4.1
C4.2
C4.3
C4.4
C4.5
C4.6
A64 instruction index by encoding .................................................................... C4-186
Data processing - immediate ............................................................................ C4-187
Branches, exception generating and system instructions ................................. C4-191
Loads and stores ............................................................................................... C4-196
Data processing - register ................................................................................. C4-218
Data processing - SIMD and floating point ........................................................ C4-227
The A64 System Instruction Class
C5.1
C5.2
C5.3
C5.4
C5.5
The System instruction class encoding space .................................................. C5-264
Special-purpose registers ................................................................................. C5-287
A64 system instructions for cache maintenance ............................................... C5-340
A64 system instructions for address translation ................................................ C5-357
A64 system instructions for TLB maintenance .................................................. C5-370
A64 Base Instruction Descriptions
C6.1
C6.2
C6.3
C6.4
C6.5
C6.6
Introduction ....................................................................................................... C6-424
Register size ..................................................................................................... C6-425
Use of the PC .................................................................................................... C6-426
Use of the stack pointer .................................................................................... C6-427
Condition flags and related instructions ............................................................ C6-428
Alphabetical list of instructions .......................................................................... C6-429
Chapter C7
A64 Advanced SIMD and Floating-point Instruction Descriptions
C7.1
Introduction ....................................................................................................... C7-764
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Contents
C7.2
C7.3
About the SIMD and floating-point instructions ................................................. C7-765
Alphabetical list of floating-point and Advanced SIMD instructions .................. C7-767
The AArch64 System Level Architecture
The AArch64 System Level Programmers’ Model
Exception levels .............................................................................................. D1-1428
D1.1
Exception terminology ..................................................................................... D1-1429
D1.2
Execution state ................................................................................................ D1-1431
D1.3
Security state .................................................................................................. D1-1432
D1.4
Virtualization .................................................................................................... D1-1434
D1.5
Registers for instruction processing and exception handling .......................... D1-1437
D1.6
Process state, PSTATE .................................................................................. D1-1443
D1.7
Program counter and stack pointer alignment ................................................ D1-1445
D1.8
D1.9
Reset ............................................................................................................... D1-1447
D1.10 Exception entry ............................................................................................... D1-1451
D1.11 Exception return .............................................................................................. D1-1466
D1.12
The Exception level hierarchy ......................................................................... D1-1470
D1.13 Synchronous exception types, routing and priorities ....................................... D1-1477
D1.14 Asynchronous exception types, routing, masking and priorities ..................... D1-1485
D1.15 Configurable instruction enables and disables, and trap controls ................... D1-1491
D1.16 System calls .................................................................................................... D1-1527
D1.17 Mechanisms for entering a low-power state .................................................... D1-1528
D1.18 Self-hosted debug ........................................................................................... D1-1533
The Performance Monitors Extension ............................................................. D1-1535
D1.19
Interprocessing ................................................................................................ D1-1536
D1.20
D1.21
The effect of implementation choices on the programmers’ model ................. D1-1548
AArch64 Self-hosted Debug
D2.1
D2.2
D2.3
D2.4
About debug exceptions .................................................................................. D2-1555
The debug exception enable controls ............................................................. D2-1558
Routing debug exceptions ............................................................................... D2-1559
Enabling debug exceptions from the current Exception level and Security state ...........
D2-1561
The effect of powerdown on debug exceptions ............................................... D2-1563
D2.5
Summary of the routing and enabling of debug exceptions ............................ D2-1564
D2.6
Pseudocode description of debug exceptions ................................................. D2-1566
D2.7
Software Breakpoint Instruction exceptions .................................................... D2-1567
D2.8
D2.9
Breakpoint exceptions ..................................................................................... D2-1569
D2.10 Watchpoint exceptions .................................................................................... D2-1584
D2.11 Vector Catch exceptions ................................................................................. D2-1597
D2.12 Software Step exceptions ............................................................................... D2-1598
D2.13 Synchronization and debug exceptions .......................................................... D2-1612
The AArch64 System Level Memory Model
D3.1
D3.2
D3.3
D3.4
D3.5
D3.6
D3.7
About the memory system architecture ........................................................... D3-1614
Address space ................................................................................................ D3-1615
Mixed-endian support ...................................................................................... D3-1616
Cache support ................................................................................................. D3-1617
External aborts ................................................................................................ D3-1638
Memory barrier instructions ............................................................................. D3-1640
Pseudocode description of general memory system instructions ................... D3-1641
The AArch64 Virtual Memory System Architecture
D4.1
D4.2
D4.3
About the Virtual Memory System Architecture (VMSA) ................................. D4-1646
The VMSAv8-64 address translation system .................................................. D4-1649
VMSAv8-64 translation table format descriptors ............................................. D4-1693
Part D
Chapter D1
Chapter D2
Chapter D3
Chapter D4
ARM DDI 0487A.i
ID012816
Copyright © 2013-2016 ARM Limited or its affiliates. All rights reserved.
Non-Confidential - Beta
vii
Contents
Chapter D5
Chapter D6
Chapter D7
Part E
Chapter E1
Chapter E2
D4.4
D4.5
D4.6
D4.7
D4.8
Access controls and memory region attributes ............................................... D4-1702
MMU faults ...................................................................................................... D4-1718
Translation Lookaside Buffers (TLBs) ............................................................. D4-1727
TLB maintenance requirements and the TLB maintenance instructions ......... D4-1731
Caches in a VMSA implementation ................................................................. D4-1745
The Performance Monitors Extension
About the Performance Monitors .................................................................... D5-1750
D5.1
Accuracy of the Performance Monitors ........................................................... D5-1752
D5.2
Behavior on overflow ....................................................................................... D5-1754
D5.3
Attributability .................................................................................................... D5-1756
D5.4
Effect of EL3 and EL2 ..................................................................................... D5-1757
D5.5
Event filtering .................................................................................................. D5-1759
D5.6
Performance Monitors and Debug state ......................................................... D5-1761
D5.7
Counter enables .............................................................................................. D5-1762
D5.8
D5.9
Counter access ............................................................................................... D5-1763
D5.10 Events, event numbers, and mnemonics ........................................................ D5-1764
D5.11 Performance Monitors Extension registers ..................................................... D5-1786
The Generic Timer in AArch64 state
D6.1
D6.2
About the Generic Timer ................................................................................. D6-1790
The AArch64 view of the Generic Timer ......................................................... D6-1794
AArch64 System Register Descriptions
D7.1
D7.2
D7.3
D7.4
D7.5
About the AArch64 System registers .............................................................. D7-1802
General system control registers .................................................................... D7-1809
Debug registers ............................................................................................... D7-2062
Performance Monitors registers ...................................................................... D7-2132
Generic Timer registers ................................................................................... D7-2172
The AArch32 Application Level Architecture
The AArch32 Application Level Programmers’ Model
E1.1
E1.2
E1.3
E1.4
E1.5
About the Application level programmers’ model ............................................ E1-2206
Additional information about the programmers’ model in AArch32 state ........ E1-2207
Advanced SIMD and floating-point instructions .............................................. E1-2217
Conceptual coprocessor support .................................................................... E1-2229
Exceptions ...................................................................................................... E1-2230
The AArch32 Application Level Memory Model
Address space ................................................................................................ E2-2232
E2.1
Memory type overview .................................................................................... E2-2233
E2.2
Caches and memory hierarchy ....................................................................... E2-2234
E2.3
Alignment support ........................................................................................... E2-2239
E2.4
Endian support ................................................................................................ E2-2241
E2.5
Atomicity in the ARM architecture ................................................................... E2-2244
E2.6
Memory ordering ............................................................................................. E2-2248
E2.7
Memory types and attributes ........................................................................... E2-2258
E2.8
Mismatched memory attributes ....................................................................... E2-2268
E2.9
E2.10 Synchronization and semaphores ................................................................... E2-2271
Part F
Chapter F1
The AArch32 Instruction Sets
The AArch32 Instruction Sets Overview
F1.1
F1.2
Support for instructions in different versions of the ARM architecture ............. F1-2284
Unified Assembler Language ........................................................................... F1-2285
viii
Copyright © 2013-2016 ARM Limited or its affiliates. All rights reserved.
Non-Confidential - Beta
ARM DDI 0487A.i
ID012816
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