Introduction 1
1.1 Scope
1.2 Reference Documents
1.2.1 Reference specifications
1.2.2 Environment and Regulatory Documents
1.3 Contributors
1.4 AMC.1 officers
1.5 Special Word Usage
1.6 Name and Logo Usage
1.6.1 Logo Usage
1.6.2 Trademark Policy
1.7 Signal Naming Conventions
1.8 Intellectual Property
1.9 Acronyms and Definitions
PICMG® AMC.1 Compliance 2
AMC.0 3
3.1 AMC.0 Compliance
3.2 AMC.0 Port Mapping
3.3 Port Definition
Common Fabric I/O Specification 4
4.1 Common Electrical and Link Layer Rules
4.2 Dual-Mode Support
4.3 Ports and Link Widths
4.4 AMC.0 Basic and Extended Connector Support
PCI Express 5
5.1 Introduction
5.2 PCI Express Compliance
5.3 PCI Express Parameters
5.3.1 Primary and Secondary PCI Express ports
5.3.2 Multiple Hosts
5.4 Type P Control Path Support
Advanced Switching 6
6.1 Introduction
6.2 Advanced Switching Compliance
Signal Integrity 7
7.1 PCI Express @ 2.5 Gbps
7.1.1 Minimum Receiver Requirements at 2.5 Gbps
7.1.2 AMC Signal Integrity Requirements and Results for 2.5 Gbps
7.2 PCI Express at 5 Gbps
7.2.1 Minimum Receiver Requirements at 5 Gbps
7.2.2 AMC Signal Integrity Requirements and Results at 5 Gbps
Management and E-Keying 8
8.1 AMC E-Keying Introduction
8.1.1 Carrier Point-to-Point Connectivity Record
8.2 Record Type
8.3 AMC Channel Descriptor Count
8.4 AMC Channel Descriptors
8.5 AMC Link Descriptors
8.5.1 AMC Link Designator
8.5.2 AMC Link Type
8.5.3 Asymmetric Match
8.5.4 Link Grouping ID
AMC.0 Pin Assignments A
Carrier Topologies (Informative) B
B.1 Basic PCI-E I/O Carrier, or With RC on the Carrier
B.2 Basic AS Carrier
B.3 PCI-E Carrier Which Supports an RC on a Module
B.4 PCI-E Carrier Which Supports Primary and Secondary RC With NTB and Failover Support
B.5 Mixed-mode AS and PCI-E Carrier
B.6 Basic PCI-E Carrier with private busses
B.7 Carrier populated with NTB-isolated RC Modules creating a compute farm
B.8 Carrier using Type P PCI-E x1 Control Bus and Some Other Fabric e.g., AMC.3 FC
Signal Integrity Analysis C
C.1 Signal Integrity Analysis Overview
C.1.1 Modeling Parameters
C.1.2 Module Stackup and Via Details
C.1.3 Carrier Stackup and Via Details
C.2 Simulation Models
C.2.1 Module to Carrier and Carrier to Module Serial Link
C.2.2 Module to Carrier to Module Serial Link
C.2.3 Representative Eye Patterns