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赛灵思Zynq-7000-PCB设计指导.pdf
Zynq-7000 SoC PCB Design Guide
Revision History
Table of Contents
Ch. 1: Introduction
About This Guide
Additional Support Resources
Ch. 2: PCB Technology Basics
Introduction
PCB Structures
Traces
Planes
Vias
Pads and Antipads
Lands
Dimensions
Transmission Lines
Return Currents
Ch. 3: Power Distribution System
Introduction
PCB Decoupling Capacitors
Recommended PCB Capacitors per Device
Required PCB Capacitor Quantities
Capacitor Specifications
PCB Bulk Capacitors
PCB High-Frequency Capacitors
Bulk Capacitor Consolidation Rules
PCB Capacitor Placement and Mounting Techniques
PCB Bulk Capacitors
Mid and High Frequency Capacitors
Basic PDS Principles
Noise Limits
Role of Inductance
Capacitor Parasitic Inductance
PCB Current Path Inductance
Capacitor Mounting Inductance
Plane Inductance
SoC Mounting Inductance
PCB Stackup and Layer Order
Capacitor Effective Frequency
Capacitor Anti-Resonance
Capacitor Placement Background
VREF Stabilization Capacitors
Power Supply Consolidation
Unconnected VCCO Pins
Simulation Methods
PDS Measurements
Noise Magnitude Measurement
Oscilloscope Measurement Methods
3.0.1 Noise Spectrum Measurements
Optimum Decoupling Network Design
Troubleshooting
Possibility 1: Excessive Noise from Other Devices on the PCB
Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces
Possibility 3: I/O Signals in PCB are Stronger Than Necessary
Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal Paths
Ch. 4: SelectIO Signaling
Introduction
Interface Types
Single-Ended versus Differential Interfaces
SDR versus DDR Interfaces
Single-Ended Signaling
Modes and Attributes
Input Thresholds
Topographies and Termination
Unidirectional Topographies and Termination
Bidirectional Topography and Termination
Bidirectional Multi-Point Topographies
Ch. 5: Processing System (PS) Power and Signaling
Power
Main Power Supplies
VCCPINT – PS Internal Logic Supply
VCCPAUX – PS Auxiliary Logic Supply
VCCPLL – PS PLL Supply
PS DDR Power Supplies
VCCO_DDR – PS DDR I/O Supply
PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference Voltage
PS_DDR_VRN, PS_DDR_VRP – PS DDR Termination Voltage
Unused DDR Memory
PS MIO Power Supplies
VCCO_MIO0 – PS MIO Bank 0 I/O Supply
VCCO_MIO1 – PS MIO Bank 1 I/O Supply
Configuring the VCCO_MIO0, VCCO_MIO1 Voltage Mode
PS_MIO_VREF – RGMII Reference Voltage
Power Sequencing
Power Supply Ramp Requirements
PCB Decoupling Capacitors
PS Clock and Reset
PS_CLK – Processor Clock
PS_POR_B – Power on Reset
PS_SRST_B – External System Reset
Boot Mode Pins
Dynamic Memory
DDR Interface Signal Pins
Dynamic Memory Implementation
DDR Supply Voltages
DDR Termination
DDR Trace Length
DDR Trace Impedance
DDR Routing Topology
MIO/EMIO IP Layout Guidelines
CAN (Controller Area Network)
Ethernet GEM
IIC
SDIO
Temperature Sensing Diodes
Trace Port Interface Unit (TPIU)
Trace B
USB ULPI
QSPI
Maximum Operating Frequency (Feedback Mode Enabled)
Ch. 6: Migration from XC7Z030-SBG485/SBV485 to XC7Z015-CLG485 and XC7Z012S-CLG485 Devices
Introduction
Differences between XC7Z030-SBG485/SBV485, XC7Z015-CLG485, and XC7Z012S-CLG485 Devices
Functional and Performance Differences
Package Differences
Processor Differences
Transceiver Differences
PCB Layout Considerations
Software Considerations
Appx. A: Processing System Memory Derating Tables
Appx. B: Additional Resources and Legal Notices
Xilinx Resources
Product Support and Documentation
Device User Guides
Xilinx Design Tools: Release Notes, Installation, and Licensing
Xilinx Forums and Wiki Links
Xilinx git Websites
Solution Centers
Documentation Navigator and Design Hubs
References
Zynq-7000 SoC Documents
PL Documents – Device and Boards
Advanced eXtensible Interface (AXI) Documents
Software Documents
git Information
Design Tool Documents
Xilinx Vivado Design Suite
Xilinx ISE Design Suite
Xilinx Embedded Development Kit (EDK)
ChipScope Pro Documentation
Third-Party IP and Standards Documents
Please Read: Important Legal Notices
Zynq-7000 SoC
PCB Design Guide
UG933 (v1.13) July 1, 2018
Revision History
The following table shows the revision history for this document.
Date
06/04/2012
06/06/2012
08/29/2012
10/11/2012
11/05/2012
02/12/2013
Version
1.0
1.1
1.2
1.2.1
1.2.2
1.3
04/01/2013
1.4
09/26/2013
1.5
Revision
Initial Xilinx release.
Corrected format issue.
Updated Table 3-1 and Table 3-2 for additional devices/packages. Added 680 µF
capacitor specification to Table 3-3.
Corrected document number (changed UG993 to UG933).
Corrected sizing problem in PDF (no content change).
Added Note (2) to Table 3-2. Added suggested part numbers to Table 3-3. Modified
paragraph under VCCPAUX – PS Auxiliary Logic Supply. Modified paragraph under
VCCPLL – PS PLL Supply. Added Figure 5-3. Modified second to last sentence and
added last sentence under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference
Voltage. Modified CAUTION! under Configuring the VCCO_MIO0, VCCO_MIO1 Voltage
Mode and Note under DDR Supply Voltages. Changed Cke connection from a
pull-down resistor to a pull-up resistor in Figure 5-5 through Figure 5-7. Updated
entire MIO/EMIO IP Layout Guidelines section.
Added XC7Z100 devices to Table 3-1 and Table 3-2. Updated ESR range values in
Table 3-3. Changed “0805 Ceramic Capacitor” section heading to Mid and High
Frequency Capacitors and modified first paragraph. Removed dimensions, changed
“0805” to “0402” in Figure 3-1 and deleted “0402 Ceramic Capacitor” subsection.
Deleted last sentence under , Modes and Attributes. Changed “minimum” to
“maximum” in third sentence of second paragraph under VCCPLL – PS PLL Supply.
Added second to last sentence under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR
Reference Voltage. Changed “Rup” to “Rterm” in Figure 5-5 and Figure 5-6. Deleted
Drst_b from Figure 5-6 and Figure 5-7. Changed Rup pull-up resistor to Rdown
pull-down resistor in Figure 5-7. Changed LPDDR2 setting in last row of Table 5-6 to
N/A. Updated values in first row of Table 5-9. Changed “Three” different topologies
to “two” under DDR Routing Topology. Removed Fly-by topology from Figure 5-8 and
Table 5-12. Deleted “NAND (ONFI),” “NOR/Flash/SRAM,” “SPI Master,” “SWDT (System
Watch Dog Timer),” and “TTC (Triple Time Counter” subsections from MIO/EMIO IP
Layout Guidelines and modified remaining subsections. Changed “EN208” to “EN247”
and “DS821” to “PG054” under Additional Resources and Legal Notices in Appendix B.
Added XC7Z010, XC7Z015, and XC7Z030 packages/devices to Table 3-1 and Table 3-2.
Changed suggested part number for the 4.7 µF capacitor in Table 3-3. Added DDR ECC
unused pins to Table 5-5. Modified Figure 5-6 (Cke pins are now applied to GND via
resistor Rdown instead of VTT via Rterm). Expanded first paragraph under DDR
Termination. Clarified DDR Termination paragraph. Added fly-by routing to DDR
Routing Topology section. Deleted SD/SDIO Peripheral Controller section. Added last
sentence under sections IIC and SDIO and second sentence under QSPI. Added
Chapter 6, Migration from XC7Z030-SBG485/SBV485 to XC7Z015-CLG485 and
XC7Z012S-CLG485 Devices.
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Date
12/04/2013
Version
1.6
08/01/2014
1.7
08/05/2014
11/07/2014
05/22/2015
1.7.1
1.8
1.9
09/25/2015
1.10
03/31/2016
1.11
Revision
Changed “DDR3” to “DDR3/3L” throughout document. Updated capacitor quantities
and packages in Table 3-1 and Table 3-2. Updated capacitor specifications in
Table 3-3. Updated descriptions for VCCPINT – PS Internal Logic Supply and VCCPAUX –
PS Auxiliary Logic Supply. Deleted “Capacitor Consolidation Rules” section. Modified
next-to-last sentence under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference
Voltage. Added paragraph preceding Table 5-5 and updated Table 5-5. Updated Addr,
Command, Contrl output name in Figure 5-7. Deleted last sentence under DDR Trace
Length.
Removed “and Pin Planning Guide” from title. Added recommendation to
Recommended PCB Capacitors per Device. Changed VCCO per Bank sub-heading from
“100 µF” to 47 µF” in Table 3-1. Removed values for VCCPLL and replaced with
reference (Note 3) in Table 3-2. Changed “Terminal” type to “Terminal Tantalum” and
added “X7U” to 100 µF capacitor in Table 3-3. Modified first paragraph under Noise
Limits by removing specifications and adding a reference to the data sheet. Updated
second paragraph under Unconnected VCCO Pins. Changed Murata part number from
“GRM155R60J475ME47D” to “GRM155R60J474KE19” under Unconnected VCCO Pins.
Updated first paragraph under PS_DDR_VRN, PS_DDR_VRP – PS DDR Termination
Voltage. Updated Unused DDR Memory. Deleted last two sentences under PS_POR_B
– Power on Reset and last sentence under PS_SRST_B – External System Reset.
Changed “Boot Mode Pins” section (pins MIO[2] to MIO[8] to Boot Mode Pins.
Modified Figure 5-5 (CKE resistor layout). Modified Figure 5-6 (changed clk signal to
differential signals CLK_P/CLK_N and added pull-down resistor to ODT). Added
separate column for DDR3L to Table 5-6 and modified values. Clarified DDR Trace
Length and DDR Trace Impedance sections. Clarified byte swapping under DDR
Routing Topology. Added last paragraph under Ethernet GEM. Deleted “Lower
Operating Frequencies (without Feedback Mode)” section from Chapter 6.
Updated document to latest user guide template.
Added XC7Z035 device to Table 3-1 and Table 3-2. Added 10 µF capacitor to Table 3-3.
Updated Table 5-5.
Added Note under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference Voltage.
Added Caution following Table 5-3. Clarified Boot Mode Pins (changed first instance
of MIO[8] to MIO[8:2]. Updated Table 5-8. Clarified paragraph following Table 5-9.
Deleted last sentence under IIC. Clarified first paragraph under SDIO and second
sentence under UART. Deleted the word “maximum” preceding “hold time” in the
Important notice under QSPI.
Added packages SBV485, FBV484, FBV676, and FFV676 to device XC7Z030, packages
FBV676, FFV676 and FFV900 to device XC7Z035, packages FBV676, FFV676, RFG676,
and FFV900 to device Z-7045, and packages FFV900, RF900, FFV1156, and RF1156 to
device XC7Z100 in Table 3-2. Added Bulk Capacitor Consolidation Rules in Chapter 3.
Deleted caution preceding Table 5-3. Updated requirements for PS_POR_B – Power on
Reset in Chapter 5. Updated DDR Routing Topology in Chapter 5. Added package
SBV485 to device Z-7100 in Differences between XC7Z030-SBG485/SBV485,
XC7Z015-CLG485, and XC7Z012S-CLG485 Devices in Chapter 6. Added Appendix A,
Processing System Memory Derating Tables.
Added recommendations to IIC and SDIO in Chapter 5.
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Date
09/27/2016
Version
1.12
07/01/2018
1.13
Revision
Added single core devices XC7Z007S, XC7Z012S, and XC7Z014S to Table 3-1,
Table 3-2, and throughout text. Added migration information from XC7Z030-SBG485
to XC7012S-CLG485 devices in Chapter 6, updated Table 6-1, and added Processor
Differences in Chapter 6.
Updated recommendations under SDIO and clarified Trace B in Chapter 5. Changed
DDR maximum recommended trace lengths from 5 inches to 8.55 inches in Table 5-8
and TL0 maximum in a point-to-point configuration from 5.3 inches to 8.55 inches
under DDR Routing Topology.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: PCB Technology Basics
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PCB Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 3: Power Distribution System
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PCB Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Basic PDS Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Simulation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PDS Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Troubleshooting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 4: SelectIO Signaling
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interface Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Single-Ended Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 5: Processing System (PS) Power and Signaling
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PS Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Boot Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Dynamic Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
MIO/EMIO IP Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Chapter 6: Migration from XC7Z030-SBG485/SBV485 to XC7Z015-CLG485 and
XC7Z012S-CLG485 Devices
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Differences between XC7Z030-SBG485/SBV485, XC7Z015-CLG485,
and XC7Z012S-CLG485 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Appendix A: Processing System Memory Derating Tables
Appendix B: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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Chapter 1
Introduction
About This Guide
This guide provides information on PCB design for the Zynq®-7000 SoC, with a focus on
strategies for making design decisions at the PCB and interface level.
This Zynq-7000 SoC PCB Design Guide, part of an overall set of documentation on the
Zynq-7000 SoC, is available on the Xilinx website at www.xilinx.com/zynq.
Additional Support Resources
For additional information regarding PCB materials, traces, and design techniques for high
speed signals, refer to chapters four and five of UG483, 7 Series FPGAs PCB Guide. A
comprehensive list of all additional resources is provided in Appendix B, Additional
Resources and Legal Notices.
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PCB Technology Basics
Chapter 2
Introduction
Printed circuit boards (PCBs) are electrical systems, with electrical properties as complicated
as the discrete components and devices mounted to them. The PCB designer has complete
control over many aspects of the PCB; however, current technology places constraints and
limits on the geometries and resulting electrical properties. The following information is
provided as a guide to the freedoms, limitations, and techniques for PCB designs using
Zynq-7000 SoC devices.
This chapter contains the following sections:
•
•
•
PCB Structures
Transmission Lines
Return Currents
PCB Structures
PCB technology has not changed significantly in the last few decades. An insulator
substrate material (usually FR4, an epoxy/glass composite) with copper plating on both
sides has portions of copper etched away to form conductive paths. Layers of plated and
etched substrates are glued together in a stack with additional insulator substrates between
the etched substrates. Holes are drilled through the stack. Conductive plating is applied to
these holes, selectively forming conductive connections between the etched copper of
different layers.
While there are advancements in PCB technology, such as material properties, the number
of stacked layers used, geometries, and drilling techniques (allowing holes that penetrate
only a portion of the stackup), the basic structures of PCBs have not changed. The
structures formed through the PCB technology are abstracted to a set of physical/electrical
structures: traces, planes (or planelets), vias, and pads.
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