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Lontium Semiconductor LT9211 Datasheet R2.0 LONTIUM SEMICONDUCTOR CORPORATION ClearEdge Technology 2-Port LVDS/MIPI/TTL to 2-Port LVDS/MIPI/TTL LT9211 Converter Datasheet We produce mixed-signal products for a better digital world! Confidential 1

Lontium Semiconductor LT9211 Datasheet R2.0 1. Features  MIPI Transmitter  Compliant with DCS1.02, D-PHY1.2 ,DSI1.2 and CSI-2 1.00  1 Clock Lane and 1~4 Configurable Data Lanes  Two Port Simultaneous Display Supported  Up to 1.8Gb/s per Data Lane  Resolution Up to 1080P 60Hz  Data Lane and Polarity Swapping  Both Non-Burst and Burst Video Mode Supported  Support RGB666, Loosely RGB666, RGB888, RGB565, 16-bit YCbCr4:2:2, 24-bit YCbCr 4:2:2 Video Format  Dual-Port LVDS Transmitter  Compatible with VESA and JEIDA standard  1~2 Configurable Port  Two Port Simultaneous Display Supported  Up to 1080P 60Hz  Data Port ,Data Lane and Polarity Swapping  Programmable Pre-emphasis  Support output SSC(30KHz±5%)  TTL Output  Support 24-bit RGB and BT656/BT1120  Both DDR and SDR supported  Support both 1.8V and 3.3V Voltage Output  Resolution up to 1080P 60Hz  MIPI Receiver  Compliant with DCS1.02, D-PHY1.2 ,DSI1.2 and CSI-2 1.00  1 Clock Lane and 1~4 Configurable Data Lanes  Two Port Input switchable  Up to 1.8Gb/s per Data Lane  Resolution Up to 1080P 60Hz  Data Lane and Polarity Swapping  Both Non-Burst and Burst Video Mode Supported  Support RGB666, Loosely RGB666, RGB888, RGB565, 16-bit YCbCr4:2:2, 24-bit YCbCr 4:2:2 Video Format  Dual-Port LVDS Receiver  Compatible with VESA and JEIDA standard  1~2 Configurable Port  Up to 1080P 60Hz  Data Port ,Data Lane and Polarity Swapping  Internal Rterm Calibration with Less than 5% Error  Programmable Equalization  Support input Dessc(30KHz±5%)  TTL Input  Support 24-bit RGB and BT656/BT1120  Both DDR and SDR supported  Support both 1.8V and 3.3V Input Voltage  Resolution up to 1080P 60Hz  Miscellaneous  1.8V and 3.3V Power Supply  Alternative Input and Output configuration for LVDS/TTL/MIPI  MIPI/LVDS muxer and splitter supported  MIPI-LVDS Levelshifter for FPGA  Support 100KHz and 400KHz I2C Slave  External 25MHz Crystal Reference Clock  Temperature Range: -40°C ~ +85°C  Packaged in QFN64 7.5mm x 7.5mm 2. General Description The Lontium LT9211 is a high performance convertor which interconvertible between MIPI DSI/CSI-2/Dual-Port LVDS and TTL except for TTL to TTL. The LT9211 deserializes input MIPI/LVDS/TTL video data, decodes packets, and converts the formatted video data stream to MIPI/LVDS/TTL transmitter output between AP and mobile display panel or camera. The LT9211 can be used as 2-Port MIPI/LVDS Repeater which support maximum 14dB input equalization and programmable pre-emphasis to improve performance. The LT9211 can also be used as MIPI/LVDS Muxer and Splitter. The LT9211 is fabricated in advanced CMOS process and implemented in 7.5x7.5mm QFN64 package. This package is RoHS compliant and specified to operate from -40°C to +85°C. We produce mixed-signal products for a better digital world! Confidential 2

Lontium Semiconductor LT9211 Datasheet R2.0 3. Applications  Mobile systems  Cellular handsets  Digital video cameras  Digital still cameras  Tablet PC, Notebook PC  Car Display and Camera System MIPI/LVDS/TTL Source / / LT9211 / / MIPI/LVDS/TTL Sink Figure 3.1 LT9211 Typical Application Diagram 4. Ordering Information Table 4.1 Ordering Information Part Number Operating Temperature Range Package Packing Method LT9211 -40°C to +85°C QFN64 (7.5*7.5) 5. IC Version Information Table 5.1 IC Version Information Mark Version LT9211 We produce mixed-signal products for a better digital world! Confidential 3

LT9211 Datasheet R2.0 Lontium Semiconductor Table of Contents 1. Features ................................................................................................................................ 2 2. General Description ............................................................................................................. 2 3. Applications ......................................................................................................................... 3 4. Ordering Information ........................................................................................................... 3 5. IC Version Information ........................................................................................................ 3 6. Revision History .................................................................................................................. 5 7. Pinning Information ............................................................................................................. 6 7.1 Pin Configuration.............................................................................................................. 6 7.2 Pin Description ................................................................................................................. 7 8. Function Description ......................................................................................................... 10 8.1 Function Block Diagram ................................................................................................. 10 9. Specification ...................................................................................................................... 11 9.1 Absolute Maximum Conditions ....................................................................................... 11 9.2 Normal Operating Conditions ......................................................................................... 11 9.3 DC Characteristics ......................................................................................................... 11 9.4 AC Characteristics ......................................................................................................... 12 9.5 Power Consumption ....................................................................................................... 14 9.6 Power-up and Reset Sequence ..................................................................................... 16 10. Package Information ....................................................................................................... 17 10.1 ePad Enhancement ...................................................................................................... 17 10.2 Package Dimensions ................................................................................................... 17 We produce mixed-signal products for a better digital world! Confidential 4

Lontium Semiconductor LT9211 Datasheet R2.0 6. Revision History Version Owner R1.0 R2.0 Y C Y C Content Initial datasheet creation Change input and output data format Date 03/30/2018 07/10/2018 We produce mixed-signal products for a better digital world! Confidential 5

Lontium Semiconductor LT9211 Datasheet R2.0 7. Pinning Information 7.1 Pin Configuration To improve signal integrity, all differential pairs should be routed with 100Ω±10% differential impedance a. Maximum trace length mismatch should be less than 2.5mil and keep total trace length to a minimum for all differential traces. It is highly recommended to route differential pairs on top or bottom layer with no vias on signal path. 4 1 D R _ P 3 L 0 M _ A X R L M 62 5 1 D R _ N 3 L 0 M _ A X R L M 61 6 1 D R _ P C L 1 M _ A X R L M 60 7 1 D R _ N C L 1 M _ A X R L M 59 8 1 D R _ P 2 L C M _ A X R L M 58 9 1 D R _ N 2 L C M _ A X R L M 57 0 2 D R _ P 1 L 2 M _ A X R L M 56 1 2 D R _ N 1 L 2 M _ A X R L M 55 2 2 D R _ P 0 L 3 M _ A X R L M 54 3 2 D R _ N 0 L 3 M _ A X R L M 53 X R _ 8 1 C C V 64 T X E R 63 L C S C 51 A D S C 50 T N I 52 N _ T S R 49 LT9211 QFN64-EPAD (Top View) VDD MLRXB_M3L0N_RD13 MLRXB_M3L0P_RD12 MLRXB_M2L1N_RD11 MLRXB_M2L1P_RD10 MLRXB_MCL2N_RD9 MLRXB_MCL2P_RDCK MLRXB_M1LCN_RD8 MLRXB_M1LCP_RD7 MLRXB_M0L3N_RD6 MLRXB_M0L3P_RD5 VCC18_RX XTALI XTALO VDD RD4_TVS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC18 MLTXA_M3L0N_TD23 MLTXA_M3L0P_TD22 MLTXA_M2L1N_TD21 MLTXA_M2L1P_TD20 MLTXA_MCL2N_TD19 MLTXA_MCL2P_TD18 MLTXA_M1LCN_TD17 MLTXA_M1LCP_TD16 MLTXA_M0L3N_TD15 MLTXA_M0L3P_TD14 VCCIO VCC18_TX VDD MLTXB_M3L0N_TD13 MLTXB_M3L0P_TD12 17 18 S H T _ 3 D R E D T _ 2 D R 19 0 D T _ 1 D R 20 21 22 1 D T _ 0 D R 2 D T _ E D R 3 D T _ S H R 23 4 D T _ S V R 24 I O C C V 25 26 27 28 29 30 31 32 5 D T _ P 3 L 0 M _ B X T L M 6 D T _ N 3 L 0 M _ B X T L M 7 D T _ P C L 1 M _ B X T L M 8 D T _ N C L 1 M _ B X T L M K C D T _ P 2 L C M _ B X T L M 9 D T _ N 2 L C M _ B X T L M 0 1 D T _ P 1 L 2 M _ B X T L M 1 1 D T _ N 1 L 2 M _ B X T L M To minimize the power supply noise floor, at least one 0.1μF and one 0.01μF decoupling capacitor is recommended to be installed near all the LT9211 1.8V/3.3V power pins. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power input pins must be minimized. Figure 7.1.1 QFN64 Pin Configuration We produce mixed-signal products for a better digital world! Confidential 6

Lontium Semiconductor LT9211 Datasheet R2.0 7.2 Pin Description PIN# PIN NAME DESCRIPTION Table 7.2.1 QFN64 Pin Description I/O TYPE I/O DIR 53,54 MLRXA_M3L0N_RD23 MLRXA_M3L0P_RD22 Analog 55,56 MLRXA_M2L1N_RD21 MLRXA_M2L1P_RD20 Analog 57,58 MLRXA_MCL2N_RD19 MLRXA_MCL2P_RD18 Analog 59,60 MLRXA_M1LCN_RD17 MLRXA_M1LCP_RD16 Analog 61,62 MLRXA_M0L3N_RD15 MLRXA_M0L3P_RD14 Analog 2,3 MLRXB_M3L0N_RD13 MLRXB_M3L0P_RD12 Analog 4,5 MLRXB_M2L1N_RD11 MLRXB_M2L1P_RD10 Analog 6,7 MLRXB_MCL2N_RD9 MLRXB_MCL2P_RDCK Analog 8,9 MLRXB_M1LCN_RD8 Analog I I I I I I I I I Port-A MIPIRX Lane-3/LVDSRX Lane-0 and TTL Input MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. Port-A MIPIRX Lane-2/LVDSRX Lane-1 and TTL Input MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. Port-A MIPIRX Lane-C/LVDSRX Lane-2 and TTL Input MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. Port-A MIPIRX Lane-1/LVDSRX Lane-C and TTL Input MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. Port-A MIPIRX Lane-0/LVDSRX Lane-3 and TTL Input MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. Port-B MIPIRX Lane-3/LVDSRX Lane-0 and TTL Input MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. Port-B MIPIRX Lane-2/LVDSRX Lane-1 and TTL Input MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. Port-B MIPIRX Lane-C/LVDSRX Lane-2 and TTL Input MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. Port-B MIPIRX Lane-1/LVDSRX Lane-C and TTL Input We produce mixed-signal products for a better digital world! Confidential 7

LT9211 Datasheet R2.0 Lontium Semiconductor PIN# PIN NAME MLRXB_M1LCP_RD7 I/O TYPE I/O DIR 10,11 MLRXB_M0L3N_RD6 MLRXB_M0L3P_RD5 Analog I 16,17 18,19 20,21 22,23 RD4_TVS,RD3_THS RD2_TDE,RD1_TD0 RD0_TD1,RDE_TD2 RHS_TD3,RVS_TD4 Analog I/O 38,39 MLTXA_M0L3P_TD14 MLTXA_M0L3N_TD15 Analog O 40,41 MLTXA_M1LCP_TD16 MLTXA_M1LCN_TD17 Analog O 42,43 MLTXA_MCL2P_TD18 MLTXA_MCL2N_TD19 Analog O 44,45 MLTXA_M2L1P_TD20 MLTXA_M2L1N_TD21 Analog O 46,47 MLTXA_M3L0P_TD22 MLTXA_M3L0N_TD23 Analog O 25,26 MLTXB_M0L3P_TD5 MLTXB_M0L3N_TD6 Analog O 27,28 MLTXB_M1LCP_TD7 MLTXB_M1LCN_TD8 Analog O DESCRIPTION MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. Port-B MIPIRX Lane-0/LVDSRX Lane-3 and TTL Input MIPI input of polarity swappable differential pairs up to 1.8Gb/s ; LVDS input of polarity swappable differential pairs up to 1.2Gb/s ; TTL input up to 200Mbps. TTL Data and Control Signal and Debug Gpo Output These Pins can be selected as TTL input or output. Also, they can be configured as outputs for debug function. Port-A MIPITX Lane-0/LVDSTX Lane-3 and TTL Output MIPI output of polarity swappable differential pairs up to 1.8Gb/s ; LVDS output of polarity swappable differential pairs up to 1.2Gb/s ; TTL output up to 200Mbps. Port-A MIPITX Lane-1/LVDSTX Lane-C and TTL Output MIPI output of polarity swappable differential pairs up to 1.8Gb/s ; LVDS output of polarity swappable differential pairs up to 1.2Gb/s ; TTL output up to 200Mbps. Port-A MIPITX Lane-C/LVDSTX Lane-2 and TTL Output MIPI output of polarity swappable differential pairs up to 1.8Gb/s ; LVDS output of polarity swappable differential pairs up to 1.2Gb/s ; TTL output up to 200Mbps. Port-A MIPITX Lane-2/LVDSTX Lane-1 and TTL Output MIPI output of polarity swappable differential pairs up to 1.8Gb/s ; LVDS output of polarity swappable differential pairs up to 1.2Gb/s ; TTL output up to 200Mbps. Port-A MIPITX Lane-3/LVDSTX Lane-0 and TTL Output MIPI output of polarity swappable differential pairs up to 1.8Gb/s ; LVDS output of polarity swappable differential pairs up to 1.2Gb/s ; TTL output up to 200Mbps. Port-B MIPITX Lane-0/LVDSTX Lane-3 and TTL Output MIPI output of polarity swappable differential pairs up to 1.8Gb/s ; LVDS output of polarity swappable differential pairs up to 1.2Gb/s ; TTL output up to 200Mbps. Port-B MIPITX Lane-1/LVDSTX Lane-C and TTL Output MIPI output of polarity swappable differential pairs up to We produce mixed-signal products for a better digital world! Confidential 8

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