ECTE 364
Data Communications
Lecture 3
Course Structure
Part I
Lecture
Content
1
2
3
4
5
6
Overview, introduction to computer networks, signal
l
d
encoding methods
k
Data link control protocols: HDLC, ARQ, Error Detection
Error correction (CRC Digital Logic, Hamming, Packet‐
Based FEC, Convolutional Codes)
Medium Access Control Protocol
Ethernet and IEEE 802.11
Hubs/Bridges/Switches
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1
The Data Link Layer
Packets from network layer
Addressing
Error Control
r
e
y
a
L
k
n
i
L
a
t
a
D
Flow Control
Packetizing
Media Access
Control
Physical Layer
3
CRC
Review
General Steps
1. Choose a width W, and a poly‐G
2. Add W zero bits to the message D, called D’
3. Divide D’ by G using CRC arithmetic.
4. Remainder is the CRC,
5. XOR with D’, and send resulting message (D’’).
D” = 101110011
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2
CRC Digital Logic
Linear Feedback Shift Register
D Flip Flop (1 bit shift register)
Cx
+ XOR
Cn‐1
+
Cn‐2
an‐1
+
+
an‐2
C1
a2
+
C0
a1
n
X
Xa
n
1
n
1
....
2
Xa
2
Xa
1
1
Input
+
Rules
•
•
•
There are n registers, equal to the length of the Frame Check Sum (FCS).
There are up to n XOR gates
The presence or absence of a gate corresponds to the presence or absence of a
term in the divisor polynomial P(X), excluding terms 1 and Xn.
CRC Digital Logic
Linear Feedback Shift Register
C2
C1
+
C0
+
Input
3
X
X
1
C4
+
C3
C2
+
C1
C0
+
Input
Polynomial?
X5 + X4 + X2 + 1
X10+X9+X5+X4+X+1
How many registers (FFs) and XOR gates?
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3
CRC Digital Logic
Linear Feedback Shift Register
Output (15 bits)
A
Switch 1
B
Input (10 bits)
C4
+
C3
C2
+
C1
C0
+
A
Switch 2
B
X5 + X4 + X2 + 1
Output (15 bits)
A
Switch 1
B
Initially, both switches are at A
Input (10 bits)
Input (10 bits)
C4
+
C3
C2
+
C1
C0
+
A
B
Switch 2
M=1010001101
C4
C3
C2
C1
C0
C
4
3
C
I
C
4
1
C
I
C 4
I
I=Input
Initial
Step‐1
Step‐2
Step‐3
Step‐4
0
1
1
1
0
0
0
1
1
1
0
1
1
1
0
0
0
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
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Output (15 bits)
A
Switch 1
B
Initially, both switches are at A
Input (10 bits)
C4
+
C3
C2
+
C1
C0
+
A
B
Switch 2
M=1010001101
C4
C3
C2
C1
C0
C
4
3
C
I
C
4
1
C
I
C 4
I
I=Input
Step‐4
Step‐5
Step‐6
Step‐7
Step‐8
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
0
0
0
0
1
0
1
0
1
1
0
0
1
1
0
Output (15 bits)
A
Switch 1
B
After Step‐9, both switches go to B
Input (10 bits)
Input (10 bits)
C4
+
C3
C2
+
C1
C0
+
A
B
Switch 2
M=1010001101
C4
C3
C2
C1
C0
C
4
3
C
I
C
4
1
C
I
C 4
I
I=Input
Step 8
Step‐8
Step‐9
Step‐10
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
0
1
1
0
1
1
1
1
1
0
0
0
1
Flip switches
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A
B
Input
C2
C1
+
C0
+
C2
0
0
1
1
0
1
C1
0
1
1
0
1
1
Initial
Step‐1
Step‐2
Step‐3
Step‐4
Step‐5
M=10100
I
I=Input
1
0
1
0
0
C
2
I
C
0
1
1
0
1
1
C 2
1
0
0
1
0
C0
0
1
0
0
1
0
Error Correction
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Forward Error Correction
(Overview)
Sender
Encoder
Noise
Channel
Receiver
Decoder
Idea: insert redundant information (bits/bytes) into
bit stream to allow recovery in case of errors.
(3 1) code
(3,1) code
1 111
0 000
101 111 000 111
Channel
13
101
Decoder
110 010 111
Hamming Codes
Overview
• Work with 4‐bits at a time. These bits are then written into the
intersection of three circles.
Fill in non‐intersecting area of each circle using the rule: each circle
must contain an even number of 1s
must contain an even number of 1s
•
0
1
1
0
1
1
1
0
0
Example: 1011
0
1
1
0
1
1
1
1
0
Received: 1111000
Transmit:
1011000
Parity bits
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Hamming Code (12,8)
Another Example
Message: 1100 1110
1
0
2
1
3
1
4
1
5
1
6
0
7
0
8
1
9
1
10
1
11
1
12
0
1st bit set
2nd bit set
3rd bit set
4th bit set
Next step, calculate even or odd parity for each check bit
Decimal
1
2
3
4
5
6
7
8
9
10
11
12
Binary
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Hamming Code (12,8)
0
1
1
0
0
1
1
1
1
0
1
0
Assume even parity
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