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OV7251完整说明书.pdf
applications
features
key specifications (typical)
table of contents
list of figures
list of tables
1 signal descriptions
table 1-1 signal descriptions (sheet 1 of 2)
table 1-2 configuration under various conditions
figure 1-1 pin diagram
table 1-3 pad symbol and equivalent circuit (sheet 1 of 2)
2 system level description
2.1 overview
2.2 architecture
figure 2-1 OV7251 block diagram
figure 2-2 reference design schematic
2.3 format and frame
table 2-1 supported resolution and frame rate
2.3.1 MIPI interface
figure 2-3 MIPI timing
table 2-2 MIPI timing specifications
2.3.2 VSYNC timing in MIPI mode
figure 2-4 VSYNC timing in mode 1
figure 2-5 VSYNC timing in mode 2
figure 2-6 VSYNC timing in mode 3
2.4 I/O control
table 2-3 I/O control registers
2.5 power management
2.5.1 power up sequence
table 2-4 power up sequence
table 2-5 power up sequence timing constraints
figure 2-7 power up sequence (case 1)
figure 2-8 power up sequence (case 2)
2.5.2 power down sequence
table 2-6 power down sequence
table 2-7 power down sequence timing constraints
figure 2-9 power down sequence (case 1)
figure 2-10 power down sequence (case 2)
figure 2-11 standby sequence
2.6 reset
2.6.1 power ON reset generation
2.7 hardware and software standby
table 2-8 hardware and software standby description
2.8 system clock control
2.8.1 PLL configuration
figure 2-12 OV7251 PLL1 clock diagram
figure 2-13 OV7251 PLL2 clock diagram
table 2-9 PLL control registers (sheet 1 of 3)
table 2-10 sample PLL configuration
figure 2-14 clock connection diagram
table 2-11 PLL speed limitation
2.9 serial camera control bus (SCCB) interface
2.9.1 data transfer protocol
2.9.2 message format
figure 2-15 message type
2.9.3 read / write operation
figure 2-16 SCCB single read from random location
figure 2-17 SCCB single read from current location
figure 2-18 SCCB sequential read from random location
figure 2-19 SCCB sequential read from current location
figure 2-20 SCCB single write to random location
figure 2-21 SCCB sequential write to random location
2.9.4 SCCB timing
figure 2-22 SCCB interface timing
table 2-12 SCCB interface timing specifications
2.9.5 group write and fast mode switching
table 2-13 context switching control
3 block level description
3.1 pixel array structure
figure 3-1 sensor array region color filter layout
3.2 subsampling
figure 3-2 example of 2x2 binning
figure 3-3 example of 2:1 subsampling
figure 3-4 example of 4:1 subsampling
table 3-1 binning-related registers
4 image sensor core digital functions
4.1 mirror and flip
figure 4-1 mirror and flip samples
table 4-1 mirror and flip registers
4.2 image windowing
figure 4-2 image windowing
table 4-2 image windowing control functions
4.3 test pattern
4.3.1 general test pattern bar
figure 4-3 test pattern
table 4-3 general test pattern bar selection control
4.3.2 solid test pattern
table 4-4 solid test pattern control (sheet 1 of 2)
4.4 black level calibration (BLC)
table 4-5 BLC control functions (sheet 1 of 2)
table 4-6 ALS algorithm control registers (sheet 1 of 3)
4.5 one time programmable (OTP) memory
4.5.1 OTP memory structure
table 4-7 OTP memory structure
4.5.2 accessing the OTP memory
figure 4-4 OTP access
4.5.3 procedure for accessing OTP memory
4.5.4 procedure to read OTP content
4.5.5 procedure to program OTP content
4.5.6 power supply requirement for OTP memory programming
4.6 pulse width modulation (PWM)
figure 4-5 PWM output timing
table 4-8 PWM registers
4.7 strobe
table 4-9 strobe control registers
4.8 low power modes
table 4-10 low power mode control registers
4.8.1 low frame rate mode
figure 4-6 low frame rate mode timing
4.8.2 snapshot mode
figure 4-7 snapshot mode timing
4.8.3 external trigger snapshot mode
figure 4-8 external snapshot mode timing
figure 4-9 frame triggered by red pulse diagram
5 image sensor processor digital functions
5.1 ISP general controls
table 5-1 ISP top registers
5.2 manual white balance (MWB)
table 5-2 manual AWB_gain registers
5.3 manual exposure and gain control
table 5-3 manual exposure and gain control registers
6 system control
6.1 mobile industry processor interface (MIPI)
table 6-1 MIPI top control registers (sheet 1 of 9)
6.2 low-voltage differential signaling (LVDS)
table 6-2 LVDS registers (sheet 1 of 2)
6.2.1 output modes
figure 6-1 LVDS 1-lane mode
6.2.2 PHY specification
figure 6-2 PHY specification diagram
table 6-3 PHY specifications
6.2.3 LVDS lane configuration and sync
figure 6-3 LVDS lane configuration and sync
7 register tables
7.1 system control [0x0100 ~ 0x010A, 0x3001 ~ 0x301F, 0x3023 ~ 0x303B, 0x4501]
table 7-1 system control registers (sheet 1 of 7)
7.2 PLL control [0x3080 ~ 0x3083, 0x3098 ~ 0x309F, 0x30B0 ~ 0x30B6]
table 7-2 PLL control registers
7.3 SCCB and group hold control [0x3100 ~ 0x3106, 0x31FF ~ 0x320F]
table 7-3 SCCB and group hold registers (sheet 1 of 2)
7.4 manual AWB_gain control [0x3400 ~ 0x3406]
table 7-4 manual AWB_gain registers
7.5 manual AEC/AGC [0x3500 ~ 0x350B, 0x5D00 ~ 0x5D01, 0x5F00 ~ 0x5F05]
table 7-5 manual AEC/AGC registers (sheet 1 of 3)
7.6 analog control [0x3600 ~ 0x3684]
table 7-6 analog control registers (sheet 1 of 2)
7.7 sensor control [0x3700 ~ 0x37AF]
table 7-7 sensor control registers
7.8 timing control [0x3800 ~ 0x3835, 0x3837]
table 7-8 timing control registers (sheet 1 of 4)
7.9 PWM and strobe control [0x3B80 ~ 0x3B97]
table 7-9 PWM and strobe control registers (sheet 1 of 2)
7.10 low power mode control [0x3C00 ~ 0x3C0F, 0x4A47 ~ 0x4A49]
table 7-10 low power mode control registers (sheet 1 of 2)
7.11 OTP control [0x3D80 ~ 0x3D87, 0x3D8B]
table 7-11 OTP control registers (sheet 1 of 2)
7.12 BLC control [0x4000 ~ 0x4051]
table 7-12 BLC control registers (sheet 1 of 4)
7.13 frame control [0x4240 ~ 0x4244]
table 7-13 frame registers
7.14 format control [0x4300 ~ 0x4307, 0x4310 ~ 0x4316, 0x4320 ~ 0x4329]
table 7-14 format control registers (sheet 1 of 3)
7.15 VFIFO control [0x4600 ~ 0x4604]
table 7-15 VFIFO control registers
7.16 MIPI top [0x4800 ~ 0x4806, 0x4810 ~ 0x4849, 0x4850 ~ 0x4854, 0x4860 ~ 0x4865]
table 7-16 MIPI top control registers (sheet 1 of 9)
7.17 LVDS control [0x4A00, 0x4A02 ~ 0x4A0F]
table 7-17 LVDS registers
7.18 ISP top [0x5000 ~ 0x5017, 0x5E00 ~ 0x5E08]
table 7-18 ISP top registers (sheet 1 of 2)
7.19 window control [0x5A00 ~ 0x5A0C]
table 7-19 window control registers
8 operating specifications
8.1 absolute maximum ratings
table 8-1 absolute maximum ratings
8.2 functional temperature
table 8-2 functional temperature
8.3 DC characteristics
table 8-3 DC characteristics (TA = 23°C ± 2°C)
8.4 timing characteristics
table 8-4 timing characteristics
9 mechanical specifications
9.1 physical specifications
figure 9-1 package specifications
table 9-1 package dimensions
9.2 IR reflow specifications
figure 9-2 IR reflow ramp rate requirements
table 9-2 reflow conditions
10 optical specifications
10.1 sensor array center
figure 10-1 sensor array center
10.2 lens chief ray angle (CRA)
figure 10-2 chief ray angle (CRA)
table 10-1 CRA versus image height plot
10.3 IR cut off wavelength
10.4 spectrum response
figure 10-3 spectrum response curve
revision history
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datasheet
PRELIMINARY SPECIFICATION
1/7.5" b&w CMOS VGA (640 x 480) image sensor
with OmniPixel3-GS™ technology
1
OV7251
b&w CMOS VGA (640 x 480) image sensor with OmniPixel3-GS™ technology
00Copyright ©2015 OmniVision Technologies, Inc. All rights reserved.
This document is provided “as is” with no warranties whatsoever, including any warranty of merchantability,
non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification,
or sample.
OmniVision Technologies, Inc. and all its affiliates disclaim all liability, including liability for infringement of any proprietary
rights, relating to the use of information in this document. No license, expressed or implied, by estoppel or otherwise, to
any intellectual property rights is granted herein.
The information contained in this document is considered proprietary to OmniVision Technologies, Inc. and all its
affiliates. This information may be distributed to individuals or organizations authorized by OmniVision Technologies, Inc.
to receive said information. Individuals and/or organizations are not allowed to re-distribute said information.
Trademark Information
OmniVision and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. OmniPixel3-GS is a
trademark of OmniVision Technologies, Inc.
All other trademarks used herein are the property of their respective owners.
b&w CMOS VGA (640 x 480) image sensor with OmniPixel3-GS™ technology
datasheet (CSP3)
PRELIMINARY SPECIFICATION
version 1.01
october 2015
To learn more about OmniVision Technologies, visit www.ovt.com.
OmniVision Technologies is publicly traded on NASDAQ under the symbol OVTI.
2
i
ordering information
OV07251-A35A-1G (b&w, lead-free)
35-pin CSP3
00applications
cellular phones
digital still cameras (DSC)
digital video camcorders (DVC)
PC multimedia
tablets
00features
3 µm x 3 µm pixel with OmniPixel3-GS™ technology
automatic black level calibration (ABLC)
programmable controls for frame rate, mirror and flip,
cropping and windowing
support output formats: 8/10-bit RAW
support for image sizes: 640x480, 320x240, 160x120
fast mode switching
supports horizontal and vertical 2:1 and 4:1
monochrome subsampling
supports 2x2 monochrome binning
one-lane MIPI serial output interface
one-lane LVDS serial output interface
embedded 256 bits of one-time programmable (OTP)
memory for part identification
two on-chip phase lock loops (PLLs)
built-in 1.5V regulator for core
PWM
built-in strobe control
00key specifications (typical)
active array size: 640 x 480
power supply:
analog: 2.8V (nominal)
core: 1.5V (optional)
I/O: 1.8V (nominal)
power requirements:
active: 117 mW @ 100fps, VGA output
standby: 15 µA for AVDD, 40 µA for DOVDD
without input clock, 700 µA for DOVDD with input
clock
XSHUTDOWN: 5 µA for AVDD, 5 µA for DOVDD
temperature range:
operating: -30°C to 70°C junction temperature
stable image: 0°C to 50°C junction temperature
output interface: 1-lane MIPI/LVDS serial output
output formats: 10-bit RGB RAW or BW
lens size: 1/7.5"
input clock frequency: 6~27 MHz
lens chief ray angle: 29° non-linear
max S/N ratio: 39 dB
dynamic range: 69.6 dB @ 8x gain
maximum image transfer rate:
640 x 480: 100 fps (see table 2-1)
sensitivity: 10,800mV/(µW.cm-2.sec) @ 850nm
scan mode: progressive
maximum exposure interval: 502 x tROW
pixel size: 3 µm x 3 µm
dark current: 350 e-/s @ 50°C junction temperature
image area: 1968 µm x 1488 µm
package dimensions: 3910 µm x 3410 µm
note
Maximum
integration time of dark
current depends on
read out speed (e.g., for
100fps, max dark
current is around 3.5e-
at 50°C).
10.12.2015
PRELIMINARY SPECIFICATION
proprietary to OmniVision Technologies
3
OV7251
b&w CMOS VGA (640 x 480) image sensor with OmniPixel3-GS™ technology
proprietary to OmniVision Technologies
PRELIMINARY SPECIFICATION
version 1.01
4
00table of contents
1 signal descriptions
2 system level description
2.1 overview
2.2 architecture
2.3 format and frame
2.3.1 MIPI interface
2.3.2 VSYNC timing in MIPI mode
2.4 I/O control
2.5 power management
2.5.1 power up sequence
2.5.2 power down sequence
2.6 reset
2.6.1 power ON reset generation
2.7 hardware and software standby
2.8 system clock control
2.8.1 PLL configuration
2.9 serial camera control bus (SCCB) interface
2.9.1 data transfer protocol
2.9.2 message format
2.9.3 read / write operation
2.9.4 SCCB timing
2.9.5 group write and fast mode switching
3 block level description
3.1 pixel array structure
3.2 subsampling
4 image sensor core digital functions
4.1 mirror and flip
4.2 image windowing
4.3 test pattern
4.3.1 general test pattern bar
4.3.2 solid test pattern
4.4 black level calibration (BLC)
iii
1-1
2-1
2-1
2-1
2-3
2-4
2-5
2-6
2-7
2-7
2-10
2-14
2-14
2-14
2-15
2-15
2-18
2-18
2-18
2-19
2-22
2-23
3-1
3-1
3-2
4-1
4-1
4-2
4-3
4-3
4-3
4-4
10.12.2015
PRELIMINARY SPECIFICATION
proprietary to OmniVision Technologies
5
OV7251
b&w CMOS VGA (640 x 480) image sensor with OmniPixel3-GS™ technology
4.5 one time programmable (OTP) memory
4.5.1 OTP memory structure
4.5.2 accessing the OTP memory
4.5.3 procedure for accessing OTP memory
4.5.4 procedure to read OTP content
4.5.5 procedure to program OTP content
4.5.6 power supply requirement for OTP memory programming
4.6 pulse width modulation (PWM)
4.7 strobe
4.8 low power modes
4.8.1 low frame rate mode
4.8.2 snapshot mode
4.8.3 external trigger snapshot mode
5 image sensor processor digital functions
5.1 ISP general controls
5.2 manual white balance (MWB)
5.3 manual exposure and gain control
6 system control
6.1 mobile industry processor interface (MIPI)
6.2 low-voltage differential signaling (LVDS)
6.2.1 output modes
6.2.2 PHY specification
6.2.3 LVDS lane configuration and sync
7 register tables
7.1 system control [0x0100 ~ 0x010A, 0x3001 ~ 0x301F, 0x3023 ~ 0x303B, 0x4501]
7.2 PLL control [0x3080 ~ 0x3083, 0x3098 ~ 0x309F, 0x30B0 ~ 0x30B6]
7.3 SCCB and group hold control [0x3100 ~ 0x3106, 0x31FF ~ 0x320F]
7.4 manual AWB_gain control [0x3400 ~ 0x3406]
7.5 manual AEC/AGC [0x3500 ~ 0x350B, 0x5D00 ~ 0x5D01, 0x5F00 ~ 0x5F05]
7.6 analog control [0x3600 ~ 0x3684]
7.7 sensor control [0x3700 ~ 0x37AF]
7.8 timing control [0x3800 ~ 0x3835, 0x3837]
7.9 PWM and strobe control [0x3B80 ~ 0x3B97]
7.10 low power mode control [0x3C00 ~ 0x3C0F, 0x4A47 ~ 0x4A49]
7.11 OTP control [0x3D80 ~ 0x3D87, 0x3D8B]
7.12 BLC control [0x4000 ~ 0x4051]
4-7
4-7
4-7
4-9
4-9
4-9
4-9
4-10
4-11
4-12
4-13
4-13
4-14
5-1
5-1
5-1
5-2
6-1
6-1
6-9
6-10
6-11
6-11
7-1
7-1
7-8
7-9
7-10
7-11
7-13
7-14
7-15
7-18
7-20
7-21
7-22
proprietary to OmniVision Technologies
PRELIMINARY SPECIFICATION
version 1.01
6
7.13 frame control [0x4240 ~ 0x4244]
7.14 format control [0x4300 ~ 0x4307, 0x4310 ~ 0x4316, 0x4320 ~ 0x4329]
7.15 VFIFO control [0x4600 ~ 0x4604]
7.16 MIPI top [0x4800 ~ 0x4806, 0x4810 ~ 0x4849, 0x4850 ~ 0x4854, 0x4860 ~ 0x4865]
7.17 LVDS control [0x4A00, 0x4A02 ~ 0x4A0F]
7.18 ISP top [0x5000 ~ 0x5017, 0x5E00 ~ 0x5E08]
7.19 window control [0x5A00 ~ 0x5A0C]
8 operating specifications
8.1 absolute maximum ratings
8.2 functional temperature
8.3 DC characteristics
8.4 timing characteristics
9 mechanical specifications
9.1 physical specifications
9.2 IR reflow specifications
10 optical specifications
10.1 sensor array center
10.2 lens chief ray angle (CRA)
10.3 IR cut off wavelength
10.4 spectrum response
v
7-26
7-26
7-28
7-29
7-38
7-39
7-41
8-1
8-1
8-1
8-2
8-3
9-1
9-1
9-2
10-1
10-1
10-2
10-3
10-3
10.12.2015
PRELIMINARY SPECIFICATION
proprietary to OmniVision Technologies
7
OV7251
b&w CMOS VGA (640 x 480) image sensor with OmniPixel3-GS™ technology
proprietary to OmniVision Technologies
PRELIMINARY SPECIFICATION
version 1.01
8
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