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AST2400 datasheet V13.pdf
I Functional Specification
1 General Information
1.1 Introduction
1.2 Chip Architecture
1.3 Summary of Feature Set
1.3.1 Package
1.3.2 Design for Testability
1.3.3 PCI-Express 1x Bus Controller (AST1250 excluded)
1.3.4 VGA Display Controller (AST1250 excluded)
1.3.5 64-bit 2D Graphics Accelerator
1.3.6 Graphics Display Controller
1.3.7 DDR3/DDR2 SDRAM Controller
1.3.8 Embedded ARM926EJ-S CPU
1.3.9 Embedded ColdFire V1 CPU
1.3.10 Video Compression Engine
1.3.11 Internal SRAM
1.3.12 System Control Unit (SCU)
1.3.13 Interrupt Controller (VIC)
1.3.14 Static Memory Controller (SMC)
1.3.15 SD/SDIO Host Controller
1.3.16 USB2.0 Virtual Hub Controller
1.3.17 USB1.1 HID Device Controller
1.3.18 USB2.0 Host Controller
1.3.19 USB1.1 Host Controller
1.3.20 10/100/1000 Mbps Fast Ethernet MAC
1.3.21 I2C/SMBus Serial Interface Controller
1.3.22 GPIO Controller
1.3.23 Master Serial GPIO Controller
1.3.24 Slave Serial GPIO Monitor
1.3.25 UART (16550)
1.3.26 Timer
1.3.27 Watchdog Timer (WDT)
1.3.28 Real Time Clock (RTC)
1.3.29 LPC Bus Interface
1.3.30 System SPI Flash Controller
1.3.31 Super I/O Controller
1.3.32 Hash & Crypto Engine
1.3.33 Memory Integrity Check (MIC) Engine
1.3.34 ADC Controller
1.3.35 PWM Controller
1.3.36 Fan Tachometer Controller
1.3.37 PECI Controller
1.3.38 JTAG Master Controller
1.3.39 MCTP Controller
1.3.40 MSI Controller
1.3.41 X-DMA Controller
1.3.42 Software Specifications
1.4 Feature Comparisons (AST2400/AST2300/AST2150)
1.5 Feature Comparisons (AST1250/AST1050/AST2150)
1.6 Feature Comparisons (AST2400/AST1400/AST1250)
1.7 Applications
1.7.1 Flash Interface Architecture
1.7.2 Remote BIOS Update
1.7.3 UART Interface Application
1.7.4 Display Output Interface
2 Pin & I/O Related Specification
2.1 Pin Description
2.2 Different Pin Name List compare to AST2300/AST1050
2.3 Ball Map
2.4 Hardware Strapping Definition
2.5 Digital Video Input/Output Interface
2.5.1 Video Mode
2.5.2 Single Edge Data Mode
2.5.3 Digital Video Dual Edge Display Output Data Mode : 12 Bits Interface
2.6 GPIO Summary
2.6.1 GPIO Table
2.6.2 GPIO Pass Through
2.7 Serial GPIO Master
2.7.1 Timing Waveform
2.8 Serial GPIO Slave Monitor
3 Electrical Specifications
3.1 Absolute Maximum Ratings
3.2 Recommended Operating Conditions
3.3 ESD Capability
3.4 Operating Powers
3.4.1 Maximum Operating Power
3.4.2 Standby Mode Power
3.4.3 Enable CPU Dynamic Slow-down
3.5 Power Up Sequence
3.6 I/O DC Electrical Specification
3.7 AC Timing Specification
3.7.1 Reference Clock Input
3.7.2 LPC Interface
3.7.3 RGMII/RMII/NCSI Interface
3.7.4 DDR2/DDR3 Interface
3.7.5 Video Interface Input/Output: Single Edge
3.7.6 Video Interface Output: Dual Edge
3.7.7 NOR Interface
3.7.8 NAND Interface
3.7.9 SPI Interface
3.7.10 JTAG Interface
3.8 Thermal Specification (Estimation)
3.8.1 Terminology
3.8.2 Testing Conditions
3.8.3 Thermal Data
3.8.4 Substrate Material Properties
4 Package Information
4.1 SMT Soldering Reflow Chart
5 Multi-function Pins Mapping and Control
II CPU Interface
6 Memory Space Allocation Table
6.1 ARM Address Space Mapping
6.2 In-compatible List to AST2300
6.3 In-compatible List to AST2200/AST2150/AST2100/AST2050/AST1100 series
6.4 Coprocessor Address Space Mapping
6.5 VGA Memory Space map to ARM Memory Space
7 Interrupt Source Table
8 Static Memory Controller
8.1 Overview
8.2 Features
8.2.1 NOR type flash supporting features
8.2.2 NAND type flash supporting features
8.2.3 SPI type flash supporting features
8.2.4 Alternate (2nd) Boot Function
8.3 Timing Definition
8.4 Legacy Registers : Base Address = 0x1600:0000
8.5 New Registers : Base Address = 0x1E62:0000
8.6 Programming Note
8.6.1 DMA Mode
8.6.2 DMA CheckSum Calculation Mode
8.6.3 SPI Timing Calibration Sequence
9 SPI Flash Controller
9.1 Overview
9.2 Timing Definition
9.3 Registers : Base Address = 0x1E63:0000
10 AHB Bus Controller
10.1 Overview
10.2 Features
10.3 Registers : Base Address = 0x1E60:0000
11 Memory Integrity Check Controller
11.1 Overview
11.2 Features
11.3 Registers : Base Address = 0x1E64:0000
11.4 Page Control Bits
11.5 Control Buffer Format
11.6 Checksum Buffer Format
11.7 Porgramming Sequence
11.7.1 Parameter Definition
11.7.2 MIC Engine Initiation (DRAM 256M Byte Address Mode)
11.7.3 MIC Engine Initiation (DRAM 512M Byte Address Mode)
11.7.4 Start Page CheckSum Process
11.7.5 Stop Page CheckSum Process (DRAM 256M Byte Address Mode)
11.7.6 Stop Page CheckSum Process (DRAM 512M Byte Address Mode)
11.8 Interrupt Behavior
12 10/100/1G Ethernet MAC Controller
12.1 Overview
12.2 Features
12.3 Registers :
12.4 Function Description
12.4.1 Transmit Descriptor
12.4.2 Receive Descriptor
12.4.3 Transmitting Packet
12.4.4 Receiving Packet
12.4.5 Ethernet Address Filtering
12.4.6 MII Management Interface
12.5 Initialization
12.5.1 Frame Transmitting Procedure
12.5.2 Frame Receiving Procedure
13 USB2.0 Virtual Hub Controller
13.1 Overview
13.2 Features
13.3 Comparison to AST2200/AST2150/AST2100/AST2050
13.4 Registers : Base Address = 0x1E6A:0000
13.4.1 Address Definition
13.4.2 Root/Global Register Definition
13.4.3 Device #1 | #5 Register Definition
13.4.4 Programmable Endpoint #0 | #14 Register Definition
13.4.5 Programmable Endpoint DMA Descriptor Definition
13.4.6 Register Reset Table
13.5 Software Programming Guide
13.5.1 Reset Control
13.5.2 Initialization Sequence
13.5.3 Set Device Address
13.5.4 Response STALL
13.5.5 Programmable Endpoint OUT Transfer Finish Check
13.5.6 Prevent a Transient Read Pointer Value
13.5.7 Procedure to enable Interrupt
13.5.8 OUT Direction Endpoint Maximum Packet Size Setting
14 USB2.0/1.1 Host Controller
14.1 Overview
14.2 UHCI Features
14.3 EHCI Features
14.4 UHCI Registers : Base Address = 0x1E6B:0000
14.5 EHCI Registers : Base Address = 0x1E6A:1000
15 Interrupt Controller
15.1 Overview
15.1.1 ARM CPU Interrupt Controller
15.1.2 System LPC Interrupt Controller (SVIC)
15.1.3 Coprocessor Interrupt Controller (CVIC)
15.2 Features
15.3 VIC Registers : Base Address = 0x1E6C:0000
15.4 SVIC Registers : Base Address = 0x1E6C:1000
15.5 CVIC Registers : Base Address = 0x1E6C:2000
16 SRAM Memory Buffer
16.1 Overview
17 SD/SDIO Host Controller
17.1 Overview
17.2 Features
17.3 Registers : Base Address = 0x1E74:0000
18 SDRAM Memory Controller
18.1 Overview
18.1.1 Features
18.1.2 ECC Features
18.1.3 Register Summary
18.2 Fixed Priority DRAM Request
18.3 Registers: Base Address = 0x1E6E:0000
18.4 Address Arrangement
18.4.1 Address Translation
18.4.2 Graphics Memory Base Address
18.5 Data Arrangement
18.5.1 16 Bits Mode
18.6 Self Refresh Command Sequence
18.6.1 Enter Self Refresh
18.6.2 Exit Self Refresh
19 USB1.1 Controller
19.1 Overview
19.2 Features
19.3 Registers : Base Address = 0x1E6E:1000
19.4 Software Programming Guide
20 System Control Unit (SCU)
20.1 Overview
20.2 Registers : Base Address = 0x1E6E:2000
21 Hash & Crypto Engine (HACE)
21.1 Overview
21.2 Features
21.3 Registers : Base Address = 0x1E6E:3000
21.4 RSA Buffer Format in Extended SRAM : Extended SRAM Base Address = 0x1E72:0000
21.5 Crypto Context Buffer Format
21.5.1 RC4 (272 Bytes)
21.5.2 AES-128 (192 Bytes)
21.5.3 AES-192 (224 Bytes)
21.5.4 AES-256 (256 Bytes)
21.5.5 DES (40 Bytes)
21.6 Hash Function Programming Sequence
21.6.1 Parameter Definition
21.6.2 MD5/SHA1/SHA224/SHA256
21.6.3 HMAC MD5/SHA1/SHA224/SHA256
21.6.4 Accumulative Mode
21.7 Command Queue Data Format
22 JTAG Master Controller
22.1 Overview
22.2 Features
22.3 Registers : Base Address = 0x1E6E_4000
22.4 Operation
22.4.1 Reset State Machine
22.4.2 Instruction Transmission
22.4.3 Data Transmission
22.5 Application Note
22.5.1 Introduction
22.5.2 Hardware Mode
22.5.3 Software Mode
23 Graphics Display Controller
23.1 CRT Controller Registers Table : Base Address = 0x1E6E:6000
23.2 CRT Controller Registers
23.3 OSD Palette Registers
24 X-DMA Controller
24.1 Overview
24.2 Features
24.3 Registers
24.4 Command Format
24.5 Clearing and Setting Procedure
24.5.1 Host Command Queue in Dirty Frame Clearing Procedure
24.5.2 Down-stream in Dirty Frame Clearing Procedure
24.5.3 Host Command Queue Read/Write Pointer Setting Procedure
24.5.4 BMC Command Queue Read/Write Pointer Setting Procedure
24.5.5 VGA Command Queue Read/Write Pointer Setting Procedure
25 MCTP Controller
25.1 Overview
25.2 Features
25.3 Registers : Base Address = 0x1E6E_8000
25.4 Command
25.4.1 TX command
25.4.2 RX command
25.5 Operation
25.5.1 Send Packet
25.5.2 Receive Packet
26 ADC Controller
26.1 Overview
26.2 Features
26.3 Registers : Base Address = 0x1E6E_9000
26.4 Operation
26.4.1 Compensating Sensing method
26.4.2 Voltage Sense Method
27 Video Engine
27.1 Overview
27.2 Features
27.3 Registers : Base Address = 0x1E70:0000
28 GPIO Controller
28.1 Overview
28.2 Features
28.2.1 Parallel GPIO
28.2.2 Serial GPIO
28.2.3 SGPIO Slave Monitor
28.3 Registers : Base Address = 0x1E78:0000
28.3.1 Parallel GPIO
28.3.2 Serial GPIO
28.3.3 SGPIO Slave
28.4 Operation
28.4.1 LPC port80h direct to GPIO
28.4.2 Parallel GPIO output driving mode
29 Real Time Clock (RTC)
29.1 Overview
29.2 Features
29.3 Registers : Base Address = 0x1E78:1000
29.4 Operation
29.4.1 Initialize Sequence
29.4.2 Alarm Mode
30 Timer Controller
30.1 Overview
30.2 Features
30.3 Registers : Base Address = 0x1E78:2000
30.4 Operation
30.5 Programming Note
30.5.1 Interrupt Generation
30.5.2 Programmable Duty Cycle Pulse Generation
30.5.3 Programmable Delay Sequence Pulse Generation
31 UART (16550)
31.1 Overview
31.2 Features
31.3 Registers
31.3.1 UART_DLL/UART_DLH
32 Watchdog Timer
32.1 Overview
32.2 Features
32.3 Registers : Base Address = 0x1E78:5000
32.4 Operation
32.4.1 Enable watchdog reset
32.4.2 Enable watchdog pulse output
32.4.3 Enable watchdog interrupt output
32.5 Programming Note
32.5.1 PCLK frequency requirement
33 PWM & Fan Tacho Controller
33.1 Overview
33.2 Features
33.3 Registers : Base Address = 0x1E78:6000
34 Virtual UART
34.1 Overview
34.2 Features
34.3 VUART Registers : Base Address = 0x1E78:7000
34.4 PUART Registers : Base Address = 0x1E78:8000
35 LPC Controller
35.1 Overview
35.2 Features
35.3 Registers : Base Address = 0x1E78:9000
36 LPC+ Controller
36.1 Overview
36.2 Feature
36.3 Registers : Base Address = 0x1E6E_C000
36.4 Operation
36.4.1 Calibration
37 SuperIO Controller
37.1 Overview
38 System Wake-Up Control
38.1 Overview
39 MailBox Controller
39.1 Overview
40 I2C/SMBus Controller
40.1 Overview
40.2 Features
40.2.1 I2C Master - all 14 buses
40.2.2 I2C Slave - all 14 buses
40.2.3 SMBus - all 14 buses
40.2.4 General
40.3 Compare to AST2300
40.4 Timing Definition
40.4.1 Clock Setting Table
40.5 Registers : Base Address = 0x1E78:A000
40.5.1 Address Definition
40.5.2 Global Register Definition
40.5.3 Device Register Definition
40.6 Software Programming Guide
40.6.1 Initialization
40.6.2 Byte Buffer and Buffer Pool Usage
40.6.3 Buffer Pool Allocation
40.6.4 Master Mode Command
40.6.5 Slave Mode Command
40.6.6 Master/Slave Dual Mode Command
40.6.7 Interrupt Handler
40.6.8 Resetting Device
40.6.9 Command and Interrupt Processing Sequence
40.6.10 SDA Bus Lock Recover
40.7 Software Programming Example
40.7.1 Clock Rate Calculation
40.7.2 Master Transmit 1 Byte
40.7.3 Master Transmit using Buffer Mode
40.7.4 Master Receive 1 Byte
40.7.5 Master Receive using Buffer Mode
40.7.6 Master Transmit 1 Byte and then Receive 1 Byte
40.7.7 Slave Receive Address Match
40.7.8 Slave Write Mode
40.7.9 Slave Read Mode
40.7.10 Master Alert Handler
40.7.11 Slave Alert Handler
40.7.12 High Speed Mode Programming Example
41 PECI Controller
41.1 Overview
41.2 Features
41.3 Registers : Base Address = 0x1E78:B000
III PCI Express Interface
42 PCI Express Controller
42.1 PCI Express Configuration Registers
42.2 Type 1 Configuration Registers
42.3 PLDA Core Status Register
42.4 Power Management Capability Structure
42.5 PCI Express Capability Structure
42.6 SSID/SSVID Capability Structure
42.7 Virtual Channel Capability Structure
43 PCI Bus Controller
43.1 Overview
43.2 Features
44 VGA Display Controller
44.1 Overview
44.2 Features
44.3 Registers
44.4 Sequential Controller Registers
44.5 CRT Controller Registers
44.6 Graphics Controller Registers
44.7 Attribute Controller Registers
44.8 RAMDAC Registers
44.9 Extended CRT Registers
45 2D Graphics Engine
45.1 Overview
45.2 Features
45.3 2D Engine Registers
46 P-Bus to AHB Bridge
46.1 Overview
46.2 Registers : Base Address = MMIOBASE
47 Message Signaled Interrupts (MSI)
47.1 Overview
47.2 Features
47.3 Operation
47.3.1 Interrupt Table
47.3.2 Message Signaled Interrupts
47.3.3 Virtual INTx
48 Graphics Hardware Cursor
48.1 Features
48.2 Register Definition
48.3 Cursor Shape Structure Definition
48.3.1 Monochrome Cursor Format (AND-XOR-RGB444 pixel format)
48.3.2 Color Cursor Format (ARGB4444 pixel format)
AST2400/AST1250
Integrated Remote Management Processor
A1 Datasheet
Version 1.3
Oct 13, 2014
ASPEED Technology Inc. retains the right to make changes to its products or specifications. While
the information furnished herein is held to be accurate and reliable, no responsibility will be assumed
by ASPEED Technology for its use. Furthermore, the information contained herein does not convey to
the purchaser of microelectronic devices any license under the patent right of any manufactures.
ASPEED products are not intended for use in life support products where failure of an ASPEED product
could reasonably be expected to result in death or personal injury. Anyone using an ASPEED product
in such an application without express written consent of an officer of ASPEED does so at their own
risk, and agrees to fully indemnify ASPEED for any damages that may result from such use or sale.
All other trademarks or register trademarks mentioned herein are the property of their respective
holders.
Headquarters
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Hsinchu City 30077, Taiwan, R. O. C.
TEL: 886-3-5789568
FAX: 886-3-5789586
http://www.ASPEEDtech.com
Copyright c2014, ASPEED Technology Inc. All right reserved.
ASPEED AST2400/AST1250 A1 Datasheet – V1.3
Part Number Information
Part number
Solder ball type
Substrate type
Package size
Ball pitch
:AST2400A1- GP
:Lead-free
:RoHS Green package
:19mm x 19mm
: 0.8mm
Part number
Solder ball type
Substrate type
Package size
Ball pitch
:AST1250A1- GP
:Lead-free
:RoHS Green package
:19mm x 19mm
: 0.8mm
Topside mark
ASPEED
AST2400
XXXXXX.XX-X
YYWWTAN A1 GP
Topside mark
ASPEED
AST1250
XXXXXX.XX-X
YYWWTAN A1 GP
ASPEED Confidential
All rights reserved.
2
Oct 13, 2014
ASPEED AST2400/AST1250 A1 Datasheet – V1.3
Revision History
Date
Revision Description
Aug. 30, 2011
Dec. 23, 2011
Jun. 01, 2012
Oct. 31, 2012
Jan. 17, 2013
Apr. 25, 2013
Jul. 05, 2013
0.3
0.31
0.7
0.8
1.0
1.01
1.1
Sep. 24, 2013
1.11
Apr. 24, 2014
Oct. 13, 2014
1.2
1.3
Text color definition
Initial draft.
Add ACPI and suspend power state.
Pre-final release.
Release for A1.
Revise electrical spec.
Revise the package type description from TFBGA to LFBGA, but package
drawing is not changed.
1. Revise the hardware strap bit32 description.
2. Revise the SPI interface tIH timing at section 3.7.
3. Revise the DDR2/DDR3 interface tDQSCK and tDQSQ timing at section
3.7.
4. Revise the thermal specification at section 3.8.
1. Revise the minimum voltage of PECIVDD from 0.9V to 0.85V.
2. Remove the power up sequence of TK timing.
3. Remove the RMII MIN timing requirement for rise/fall time.
1. Revise the system UART port number from 2 ports to 4 ports.
2. Remove MSI, MCTP, and System memory DMA features from AST1250.
3. Revise the power up sequence.
1. Revise the GPIO type of GPIOZ, GPIOAA and GPIOAB, from bidirec-
tional type to output type. And modify the pin name from GPIO* to GPO*.
1. All new added features compare to AST2300/AST1050/AST1300 are highlighted by this color.
2. All different contents compare to previous release are highlighted by this color.
3. All important descriptions are highlighted by this color.
4. Removed features are highlighted by this style.
ASPEED Confidential
All rights reserved.
3
Oct 13, 2014
ASPEED AST2400/AST1250 A1 Datasheet – V1.3
Revision History of Software Programming Guide
Date
Revision Description
Aug. 30, 2011
Jun. 01, 2012
Jan. 17, 2013
Jul. 05, 2013
0.3
0.7
1.0
1.1
Apr. 24, 2014
1.2
Initial draft.
Pre-final release.
Final release.
1. Add watchdog programming guide at section 32.
2. Add GPIO driving mode (push-pull vs. open-drain) programming guide
at section 28.
3. Revise the JTAG master register JTAG10 description about TDO at sec-
tion22.
1. Revise the companion chips supported from 4 to 2 at section 36.
ASPEED Confidential
All rights reserved.
4
Oct 13, 2014
ASPEED AST2400/AST1250 A1 Datasheet – V1.3
AST2400 Migration List from A0 to A1
Functional Bugs in A0 that will be fixed in A1 list
1. Fixed SPICS2# pin function.
2. Fixed PCIe hang with ASPM enabled issue.
3. Fixed Video RC4/AES error.
4. Fixed UEFI BIOS checking extended config register (longer than 256 bytes) issue.
5. Fixed ADC fast timer mode issue.
6. Fixed MCTP DMA issue.
AST2400 A1 New Feature List
1. Support DDR clock duty calibration.
ASPEED Confidential
All rights reserved.
5
Oct 13, 2014
ASPEED AST2400/AST1250 A1 Datasheet – V1.3
Contents
I Functional Specification
17
1 General Information
17
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Chip Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 Summary of Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.1 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.2 Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.3 PCI-Express 1x Bus Controller (AST1250 excluded)
. . . . . . . . . . . . . . . . . . . . . 19
1.3.4 VGA Display Controller (AST1250 excluded)
. . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.5 64-bit 2D Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.6 Graphics Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.7 DDR3/DDR2 SDRAM Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.8 Embedded ARM926EJ-S CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.9 Embedded ColdFire V1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3.10 Video Compression Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3.11 Internal SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3.12 System Control Unit (SCU)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3.13 Interrupt Controller (VIC)
1.3.14 Static Memory Controller (SMC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.3.15 SD/SDIO Host Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.3.16 USB2.0 Virtual Hub Controller
1.3.17 USB1.1 HID Device Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3.18 USB2.0 Host Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3.19 USB1.1 Host Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3.20 10/100/1000 Mbps Fast Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.3.21 I2C/SMBus Serial Interface Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3.22 GPIO Controller
1.3.23 Master Serial GPIO Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3.24 Slave Serial GPIO Monitor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3.25 UART (16550)
1.3.26 Timer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3.27 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3.28 Real Time Clock (RTC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.3.29 LPC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.3.30 System SPI Flash Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.3.31 Super I/O Controller
1.3.32 Hash & Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3.33 Memory Integrity Check (MIC) Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3.34 ADC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3.35 PWM Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.3.36 Fan Tachometer Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.3.37 PECI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.3.38 JTAG Master Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.3.39 MCTP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.3.40 MSI Controller
1.3.41 X-DMA Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.3.42 Software Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
. . . . . . . . . . . . . . . . . . . . . . . . 36
1.4 Feature Comparisons (AST2400/AST2300/AST2150)
. . . . . . . . . . . . . . . . . . . . . . . . 38
1.5 Feature Comparisons (AST1250/AST1050/AST2150)
1.6 Feature Comparisons (AST2400/AST1400/AST1250)
. . . . . . . . . . . . . . . . . . . . . . . . 40
1.7 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.7.1 Flash Interface Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.7.2 Remote BIOS Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
ASPEED Confidential
All rights reserved.
6
Oct 13, 2014
ASPEED AST2400/AST1250 A1 Datasheet – V1.3
1.7.3 UART Interface Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.7.4 Display Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2 Pin & I/O Related Specification
47
2.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.2 Different Pin Name List compare to AST2300/AST1050 . . . . . . . . . . . . . . . . . . . . . . . 68
2.3 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.4 Hardware Strapping Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.5 Digital Video Input/Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.5.1 Video Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.5.2 Single Edge Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.5.3 Digital Video Dual Edge Display Output Data Mode : 12 Bits Interface . . . . . . . . . . . 79
2.6 GPIO Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.6.1 GPIO Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.6.2 GPIO Pass Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.7.1 Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.8 Serial GPIO Slave Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.7 Serial GPIO Master
3 Electrical Specifications
89
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.2 Recommended Operating Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.3 ESD Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.4 Operating Powers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.4.1 Maximum Operating Power
3.4.2 Standby Mode Power
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.4.3 Enable CPU Dynamic Slow-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.5 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.6 I/O DC Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.7 AC Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.7.1 Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.7.2 LPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.7.3 RGMII/RMII/NCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.7.4 DDR2/DDR3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.7.5 Video Interface Input/Output: Single Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.7.6 Video Interface Output: Dual Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.7.7 NOR Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.7.8 NAND Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.7.9 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.7.10 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.8 Thermal Specification (Estimation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.8.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.8.2 Testing Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.8.3 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.8.4 Substrate Material Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4 Package Information
4.1 SMT Soldering Reflow Chart
106
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5 Multi-function Pins Mapping and Control
II CPU Interface
108
116
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All rights reserved.
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Oct 13, 2014
ASPEED AST2400/AST1250 A1 Datasheet – V1.3
6 Memory Space Allocation Table
116
6.1 ARM Address Space Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.2 In-compatible List to AST2300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3 In-compatible List to AST2200/AST2150/AST2100/AST2050/AST1100 series . . . . . . . . . . . 117
6.4 Coprocessor Address Space Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.5 VGA Memory Space map to ARM Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7 Interrupt Source Table
119
8 Static Memory Controller
122
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8.2.1 NOR type flash supporting features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8.2.2 NAND type flash supporting features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.2.3 SPI type flash supporting features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.2.4 Alternate (2nd) Boot Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.3 Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.4 Legacy Registers : Base Address = 0x1600:0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.5 New Registers : Base Address = 0x1E62:0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.6 Programming Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8.6.1 DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8.6.2 DMA CheckSum Calculation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8.6.3 SPI Timing Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9 SPI Flash Controller
145
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.2 Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.3 Registers : Base Address = 0x1E63:0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10 AHB Bus Controller
149
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.3 Registers : Base Address = 0x1E60:0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11 Memory Integrity Check Controller
151
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.3 Registers : Base Address = 0x1E64:0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.4 Page Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.5 Control Buffer Format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.6 Checksum Buffer Format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.7 Porgramming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.7.1 Parameter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.7.2 MIC Engine Initiation (DRAM 256M Byte Address Mode) . . . . . . . . . . . . . . . . . . . 158
11.7.3 MIC Engine Initiation (DRAM 512M Byte Address Mode) . . . . . . . . . . . . . . . . . . . 159
11.7.4 Start Page CheckSum Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.7.5 Stop Page CheckSum Process (DRAM 256M Byte Address Mode) . . . . . . . . . . . . . 159
11.7.6 Stop Page CheckSum Process (DRAM 512M Byte Address Mode) . . . . . . . . . . . . . 159
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.8 Interrupt Behavior
12 10/100/1G Ethernet MAC Controller
161
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.3 Registers :
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.4 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.4.1 Transmit Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.4.2 Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
12.4.3 Transmitting Packet
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
ASPEED Confidential
All rights reserved.
8
Oct 13, 2014
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