ISA System Architecture.pdf

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Title Page

Table of Contents

Chapter 1: Intro to Microprocessor Communication

Instruction Fetch and Execution

General

In-Line Code Fetching

Reading and Writing

Chapter 2: Introduction to the Bus Cycle

Introduction

Automatic Dishwasher – Classic State Machine Example

The System Clock – a Metronome

Microprocessor's Bus Cycle State Machine

Address Time

Data Time

Chapter 3: Addressing I/O and Memory

Evolution of Memory and I/O Address Space

Intel 8080 Microprocessor Address Space

8086 and 8088 Microprocessor Address Space

Chapter 4: The Address Decode Logic

The Address Decoder Concept

Data Bus Contention (Address Conflicts)

How Address Decoders Work

Example 1– PC and PC/XT ROM Address Decoder

Background

Chapter 5: The 286 Microprocessor

The 80286 Functional Units

The Instruction Unit

The Execution Unit

General Registers

Chapter 6: The Reset Logic

The Power Supply Reset

Reset Button

Shutdown Detect

Hot Reset

Alternate (Fast) Hot Reset

Ctrl-Alt-Del Soft Reset

Chapter 7: The Power-Up Sequence

The Power Supply – Primary Reset Source

How RESET Affects the Microprocessor

Processor Reaction When Output Voltages Stabilize

The First Bus Cycle

Chapter 8: The 80286 System Kernel: The Engine

The Bus Control Logic

The Address Latch

Address Pipelining

Chapter 9: Detailed View of the 80286 Bus Cycle

Address and Data Time Revisited

The Read Bus Cycle

Chapter 10: The 80386DX and SX Microprocessors

Introduction

The 80386 Functional Units

General

Code Prefetch Unit

Instruction Decode Unit

Execution Unit

General

The Registers

General Registers

Status, MSW and Instruction Registers

Appendix B: Glossary

Glossary

Index

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ISA System Architecture Third Edition MINDSHARE, INC. TOM SHANLEY AND DON ANDERSON EDITED AND REVISED BY JOHN SWINDLE L MM Addison-Wesley Publishing Company Reading, Massachusetts • Menlo Park, California New York Don Mills, Ontario Wokingham, England Amsterdam Bonn Sydney Singapore Tokyo Madrid San Juan Paris • Seoul Milan Mexico City Taipei

Many of the designations used by manufacturers and sellers to distinguish their prod- ucts are claimed as trademarks. Where those designations appear in this book, and Ad- dison-Wesley was aware of a trademark claim, the designations have been printed in initial capital letters or all capital letters. The authors and publishers have taken care in preparation of this book, but make no expressed or implied warranty of any kind and assume no responsibility for errors or omissions. No liability is assumed for incidental or consequential damages in connec- tion with or arising out of the use of the information or programs contained herein. Library of Congress Cataloging-in-Publication Data ISBN: 0-201-40996-8 Copyright © 1995 by MindShare, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photo- copying, recording, or otherwise, without the prior written permission of the publisher. Printed in the United States of America. Published simultaneously in Canada. Sponsoring Editor: Keith Wollman Project Manager: Eleanor McCarthy Production Coordinator: Deborah McKenna Cover design: Barbara T. Atkinson Set in 10 point Palatino by MindShare, Inc. 1 2 3 4 5 6 7 8 9 -MA- 9998979695 First printing, February 1995 Addison-Wesley books are available for bulk purchases by corporations, institutions, and other organizations. For more information please contact the Corporate, Govern- ment, and Special Sales Department at (800) 238-9682.

Contents Contents Foreword...............................................................................................................................xxiii Acknowledgments................................................................................................................xxv About This Book The MindShare Architecture Series......................................................................................1 Organization of This Book...................................................................................................... 2 Who This Book Is For...............................................................................................................2 Prerequisite Knowledge..........................................................................................................2 Documentation Conventions..................................................................................................3 Hex Notation.......................................................................................................................3 Binary Notation...................................................................................................................3 Decimal Notation................................................................................................................3 Signal Name Representation.............................................................................................3 Identification of Bit Fields (logical groups of bits or signals) .......................................4 We Want Your Feedback .........................................................................................................4 Overview System Kernel ...........................................................................................................................6 Memory Subsystems................................................................................................................6 ISA Subsystem ..........................................................................................................................7 Origins of ISA ...........................................................................................................................7 The IBM PC .........................................................................................................................7 The IBM PC/AT..................................................................................................................8 The ISA Concept.......................................................................................................................8 Part 1: The System Kernel Chapter 1: Intro to Microprocessor Communications Instruction Fetch and Execution ..........................................................................................11 General...............................................................................................................................11 In-Line Code Fetching......................................................................................................13 Reading and Writing..............................................................................................................15 Type of Information Read from Memory......................................................................16 Type of Information Written to Memory.......................................................................16 The Buses .................................................................................................................................16 The Address Bus...............................................................................................................17 Control Bus – Transaction Type and Synchronization ................................................19 The Data Bus — Data Transfer Path ..............................................................................19 v

ISA System Architecture Chapter 2: Introduction to the Bus Cycle Introduction .............................................................................................................................21 Automatic Dishwasher – Classic State Machine Example..............................................21 The System Clock – a Metronome.......................................................................................22 Microprocessor's Bus Cycle State Machine .......................................................................23 Address Time ....................................................................................................................24 Data Time...........................................................................................................................25 The Wait State ...................................................................................................................26 Chapter 3: Addressing I/O and Memory Evolution of Memory and I/O Address Space...................................................................29 Intel 8080 Microprocessor Address Space.....................................................................29 8086 and 8088 Microprocessor Address Space .............................................................33 286 and 386SX Address Space ........................................................................................34 386DX, 486 and Pentium Processor Address Space.....................................................35 Memory Mapped I/O .............................................................................................................36 The I/O Device ........................................................................................................................36 Chapter 4: The Address Decode Logic The Address Decoder Concept.............................................................................................39 Data Bus Contention (Address Conflicts)..........................................................................41 How Address Decoders Work ..............................................................................................41 Example 1– PC and PC/XT ROM Address Decoder .........................................................42 Background .......................................................................................................................42 The PC/XT ROM Address Decode Logic .....................................................................44 Example 2 – System Board I/O Address Decoder .............................................................47 Chapter 5: The 80286 Microprocessor The 80286 Functional Units...................................................................................................53 The Instruction Unit .........................................................................................................55 The Execution Unit...........................................................................................................55 General Registers.......................................................................................................56 The Status and Control Registers ............................................................................59 The Address Unit..............................................................................................................63 The Segment Registers..............................................................................................63 Segment Register Usage in Real Mode ...................................................................63 Code Segment (CS) & Instruction Pointer (IP) Registers .....................................67 The Data Segment (DS) Register .............................................................................69 The Extra Segment (ES) Register .............................................................................70 Stack Segment (SS) & Stack Pointer (SP) Registers ...............................................71 Little-Endian Byte-Ordering Rule ...........................................................................74 Definition of Extended Memory..............................................................................75 Accessing Extended Memory in Real Mode ..........................................................76 vi

Contents The Bus Unit......................................................................................................................81 Address Latches and Drivers...................................................................................81 Instruction Prefetcher and 6-byte Prefetch Queue................................................81 Processor Extension Interface ..................................................................................82 Bus Control Logic ......................................................................................................83 Data Transceivers ......................................................................................................83 80286 Hardware Interface to External Devices..................................................................83 The Address Bus...............................................................................................................83 How 80286 Addresses External Locations ....................................................................85 The Data Bus .....................................................................................................................87 The Cardinal Rules ...........................................................................................................88 Cardinal Rule Number One .....................................................................................88 Cardinal Rule Number Two.....................................................................................89 Cardinal Rule Number Three ..................................................................................89 The Control Bus ................................................................................................................ 89 Bus Cycle Definition Lines .......................................................................................90 Bus Mastering Lines..................................................................................................90 Protecting Access To Shared Resource ...................................................................92 Ready Line..................................................................................................................94 Interrupt Lines ...........................................................................................................95 Processor Extension Interface Lines........................................................................96 The Clock Line ...........................................................................................................97 The Reset Line............................................................................................................97 Protected Mode .......................................................................................................................98 Intro to Protected Mode and Multitasking Operating Systems..................................99 Segment Register Usage in Protected Mode ...............................................................101 Chapter 6: The Reset Logic The Power Supply Reset .....................................................................................................107 Reset Button...........................................................................................................................108 Shutdown Detect ..................................................................................................................108 Hot Reset ................................................................................................................................109 Alternate (Fast) Hot Reset ...................................................................................................111 Ctrl-Alt-Del Soft Reset ........................................................................................................111 Chapter 7: The Power-Up Sequence The Power Supply – Primary Reset Source .....................................................................113 How RESET Affects the Microprocessor..........................................................................115 Processor Reaction When Output Voltages Stabilize....................................................115 The First Bus Cycle...............................................................................................................116 Chapter 8: The 80286 System Kernel: the Engine The Bus Control Logic .........................................................................................................119 vii

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