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ONFI 4.2 接口规范，NAND Flash的最新标准.pdf
Open NAND Flash Interface Specification
Revision 4.2
02 12 2020
Intel Corporation
Micron Technology, Inc.
Phison Electronics Corp.
Western Digital Corporation
SK Hynix, Inc.
Sony Corporation
This 4.2 revision of the Open NAND Flash Interface specification ("Final Specification") is
available for download at www.onfi.org.
SPECIFICATION DISCLAIMER
“AS
IS PROVIDED TO YOU
IS” WITH NO WARRANTIES
THIS SPECIFICATION
INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-
WHATSOEVER,
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS
SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF
ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMENTATION OF INFORMATION
IN THIS SPECIFICATION. THE AUTHORS DO NOT WARRANT OR REPRESENT THAT SUCH
USE WILL NOT INFRINGE SUCH RIGHTS. THE PROVISION OF THIS SPECIFICATION TO
YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
Copyright 2005-2020, Intel Corporation, Micron Technology, Inc., Phison Electronics Corp.,
Western Digitial Corporation, SK Hynix, Inc., Sony Corporation. All rights reserved.
For more information about ONFI, refer to the ONFI Workgroup website at www.onfi.org.
All product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
ONFI Workgroup Technical Editor:
mailto: Anthony Constantine
2111 NE 25th Ave
Hillsboro, OR 97124 USA
Tel: 971-215-1128
Email: anthony.m.constantine@intel.com
ii
Table of Contents
1.
2.18.1.
2.18.2.
2.20.1.
2.10.1.
2.11.
2.12.
2.12.1.
2.12.2.
Introduction ............................................................................................................................... 1
1.1. Goals and Objectives ........................................................................................................ 1
1.2. EZ NAND Overview .......................................................................................................... 1
1.3. References ........................................................................................................................ 1
1.4. Definitions, abbreviations, and conventions ...................................................................... 1
1.4.1. Definitions and Abbreviations .................................................................................... 1
1.4.2. Conventions ............................................................................................................... 5
2. Physical Interface ..................................................................................................................... 8
2.1. TSOP-48 and WSOP-48 Pin Assignments ....................................................................... 8
2.2. LGA-52 Pad Assignments ............................................................................................... 11
2.3. BGA-63 Ball Assignments ............................................................................................... 13
2.4. BGA-100 Ball Assignments ............................................................................................. 17
2.5. BGA-152 and BGA-132 Ball Assignments ...................................................................... 20
2.6. BGA-272, BGA-252, and BGA-316 Ball Assignments .................................................... 23
2.7. Signal Descriptions ......................................................................................................... 30
2.8. CE_n Signal Requirements ............................................................................................. 46
2.8.1. Requirements for CLK (NV-DDR) ............................................................................ 46
2.9. Absolute Maximum DC Ratings ...................................................................................... 46
Recommended DC Operating Conditions ................................................................... 48
2.10.
I/O Power (VccQ) and I/O Ground (VssQ) ........................................................... 48
AC Overshoot/Undershoot Requirements ................................................................... 49
DC and Operating Characteristics ............................................................................... 51
Single-Ended Requirements for Differential Signals ............................................ 59
VREFQ Tolerance ................................................................................................ 59
Calculating Pin Capacitance ....................................................................................... 61
Staggered Power-up .................................................................................................... 61
Power Cycle Requirements ......................................................................................... 61
Independent Data Buses ............................................................................................. 61
Bus Width Requirements ............................................................................................. 62
Ready/Busy (R/B_n) Requirements ............................................................................ 63
Power-On Requirements ...................................................................................... 63
R/B_n and SR[6] Relationship ............................................................................. 64
2.19. Write Protect ................................................................................................................ 64
2.20.
CE_n Pin Reduction Mechanism ................................................................................. 64
Volume Appointment when CE_n Reduction Not Supported .............................. 68
3. Memory Organization ............................................................................................................. 70
3.1. Addressing ...................................................................................................................... 71
3.1.1. Multi-plane Addressing ............................................................................................ 72
3.1.2.
Logical Unit Selection .............................................................................................. 73
3.1.3. Multiple LUN Operation Restrictions ........................................................................ 73
3.2. Volume Addressing ......................................................................................................... 74
3.2.1. Appointing Volume Address .................................................................................... 74
3.2.2. Selecting a Volume .................................................................................................. 74
3.2.3. Multiple Volume Operations Restrictions ................................................................. 74
3.2.4. Volume Reversion .................................................................................................... 75
3.3. Factory Defect Mapping .................................................................................................. 77
3.3.1. Device Requirements............................................................................................... 77
3.3.2. Host Requirements .................................................................................................. 77
3.4. Extended ECC Information Reporting ............................................................................. 78
3.4.1. Byte 0: Number of bits ECC correctability ............................................................... 78
3.4.2. Byte 1: Codeword size ............................................................................................. 79
3.4.3. Byte 2-3: Bad blocks maximum per LUN ................................................................. 79
3.4.4. Byte 4-5: Block endurance ....................................................................................... 79
3.5. Discovery and Initialization.............................................................................................. 79
2.13.
2.14.
2.15.
2.16.
2.17.
2.18.
iii
4.7.1.
3.5.1. Discovery without CE_n pin reduction ..................................................................... 79
3.5.2. Discovery with CE_n pin reduction .......................................................................... 80
3.5.3.
Target Initialization ................................................................................................... 83
4. Data Interface and Timing ...................................................................................................... 84
4.1. Data Interface Type Overview ........................................................................................ 84
4.2. Signal Function Assignment............................................................................................ 85
4.3. Bus State ......................................................................................................................... 85
4.3.1. SDR.......................................................................................................................... 86
4.3.2. NV-DDR ................................................................................................................... 86
4.3.3. NV-DDR2 and NV-DDR3 ......................................................................................... 87
4.3.4. Pausing Data Input/Output and Restarting an Exited Data Input/Output Sequence 87
4.4. NV-DDR / NV-DDR2 / NV-DDR3 and Repeat Bytes ...................................................... 90
4.5. Data Interface / Timing Mode Transitions ....................................................................... 91
4.5.1. SDR Transition from NV-DDR or NV-DDR2 ............................................................ 91
4.5.2. NV-DDR2 Recommendations .................................................................................. 92
4.5.3. NV-DDR3 Recommendations .................................................................................. 92
4.6. Test Conditions ............................................................................................................... 92
4.6.1. SDR Only ................................................................................................................. 92
4.6.2. Devices that Support Driver Strength Settings ........................................................ 93
4.7. ZQ Calibration ................................................................................................................. 93
ZQ External Resistor Value, Tolerance, and Capacitive loading ............................ 95
4.8.
I/O Drive Strength ........................................................................................................... 95
4.9. Output Slew Rate ............................................................................................................ 96
Capacitance ............................................................................................................... 101
4.10.
Legacy Capacitance Requirements ................................................................... 101
Capacitance Requirements (Informative)........................................................... 103
Package Electrical Specifications and Pad Capacitance for Raw NAND Devices
4.10.1.
4.10.2.
4.10.3.
Supporting I/O Speeds Greater than 533MT/s ..................................................................... 105
Impedance Values ..................................................................................................... 107
NV-DDR ............................................................................................................. 108
NV-DDR2 ........................................................................................................... 110
NV-DDR3 ........................................................................................................... 112
4.12. Output Driver Sensitivity ............................................................................................ 114
Input Slew Rate Derating .......................................................................................... 115
4.13.
NV-DDR ............................................................................................................. 115
NV-DDR2/NV-DDR3 .......................................................................................... 115
4.14.
Differential Signaling (NV-DDR2/NV-DDR3) ............................................................. 123
4.15. Warmup Cycles (NV-DDR2/NV-DDR3) ..................................................................... 124
4.16. On-die Termination (NV-DDR2/NV-DDR3) ............................................................... 125
ODT Sensitivity ................................................................................................... 128
Self-termination ODT.......................................................................................... 128
Matrix Termination .............................................................................................. 129
Timing Parameters .................................................................................................... 136
General Parameters ........................................................................................... 137
SDR .................................................................................................................... 139
NV-DDR ............................................................................................................. 140
NV-DDR2/NV-DDR3 .......................................................................................... 141
Timing Modes ............................................................................................................ 142
SDR .................................................................................................................... 142
NV-DDR ............................................................................................................. 144
NV-DDR2/NV-DDR3 .......................................................................................... 147
Timing Diagrams ....................................................................................................... 155
SDR .................................................................................................................... 155
NV-DDR ............................................................................................................. 163
NV-DDR2 and NV-DDR3 ................................................................................... 174
5. Command Definition ............................................................................................................. 182
4.18.1.
4.18.2.
4.18.3.
4.16.1.
4.16.2.
4.16.3.
4.17.1.
4.17.2.
4.17.3.
4.17.4.
4.19.
4.19.1.
4.19.2.
4.19.3.
4.11.
4.11.1.
4.11.2.
4.11.3.
4.13.1.
4.13.2.
4.17.
4.18.
iv
5.1. Command Set ............................................................................................................... 182
5.2. Command Descriptions ................................................................................................. 185
5.3. Reset Definition ............................................................................................................. 189
5.4. Synchronous Reset Definition ....................................................................................... 189
5.5. Reset LUN Definition ..................................................................................................... 190
5.6. Read ID Definition ......................................................................................................... 191
5.7. Read Parameter Page Definition .................................................................................. 195
5.7.1. Parameter Page Data Structure Definition ............................................................ 197
5.7.2. Extended Parameter Page Data Structure Definition ............................................ 217
5.8. Read Unique ID Definition............................................................................................. 220
5.9. Block Erase Definition ................................................................................................... 222
Read Status Definition ............................................................................................... 222
5.10.
Read Status Enhanced Definition ............................................................................. 227
5.11.
5.12.
Read Status and Read Status Enhanced required usage ........................................ 227
Status Field Definition................................................................................................ 228
5.13.
Read Definition .......................................................................................................... 229
5.14.
Read Cache Definition............................................................................................... 231
5.15.
Page Program Definition ........................................................................................... 235
5.16.
5.17.
Page Cache Program Definition ................................................................................ 237
Copyback Definition ................................................................................................... 241
5.18.
Small Data Move ....................................................................................................... 245
5.19.
Change Read Column Definition ............................................................................... 248
5.20.
5.21.
Change Read Column Enhanced Definition ............................................................. 248
Change Write Column Definition ............................................................................... 251
5.22.
Change Row Address Definition ............................................................................... 251
5.23.
5.24.
Volume Select Definition ........................................................................................... 253
5.25. ODT Configure Definition .......................................................................................... 254
ZQ Calibration Long .................................................................................................. 257
5.26.
ZQ Calibration Short .................................................................................................. 257
5.27.
5.28.
Set Features Definition .............................................................................................. 258
5.29. Get Features Definition.............................................................................................. 261
5.30.
Feature Parameter Definitions .................................................................................. 262
Timing Mode ....................................................................................................... 263
NV-DDR2 and NV-DDR3 Configuration ............................................................. 264
I/O Drive Strength ............................................................................................... 265
DCC, Read, Write Tx Training ........................................................................... 266
External Vpp Configuration ................................................................................ 273
Volume Configuration ......................................................................................... 273
EZ NAND control ................................................................................................ 274
6. Multi-plane Operations ......................................................................................................... 275
6.1. Requirements ................................................................................................................ 275
6.2. Status Register Behavior .............................................................................................. 276
6.3. Multi-plane Page Program ............................................................................................ 276
6.4. Multi-plane Copyback Read and Program .................................................................... 280
6.5. Multi-plane Block Erase ................................................................................................ 283
6.6. Multi-plane Read ........................................................................................................... 285
7. Behavioral Flows .................................................................................................................. 289
7.1. Target behavioral flows ................................................................................................. 289
7.1.1. Variables ................................................................................................................ 289
Idle states ............................................................................................................... 289
7.1.2.
7.1.3.
Idle Read states ..................................................................................................... 291
7.1.4. Reset command states .......................................................................................... 293
7.1.5. Read ID command states ...................................................................................... 295
7.1.6. Read Parameter Page command states................................................................ 296
7.1.7. Read Unique ID command states .......................................................................... 297
7.1.8. Page Program and Page Cache Program command states ................................. 298
5.30.1.
5.30.2.
5.30.3.
5.30.4.
5.30.5.
5.30.6.
5.30.7.
v
7.1.9. Block Erase command states ................................................................................ 301
Read command states ....................................................................................... 303
7.1.10.
Set Features command states ........................................................................... 305
7.1.11.
Get Features command states ........................................................................... 306
7.1.12.
Read Status command states ............................................................................ 306
7.1.13.
7.1.14.
Read Status Enhanced command states ........................................................... 307
Volume Select command states ......................................................................... 307
7.1.15.
7.1.16.
ODT Configure command states ........................................................................ 308
7.2. LUN behavioral flows .................................................................................................... 309
7.2.1. Variables ................................................................................................................ 309
Idle command states .............................................................................................. 309
7.2.2.
7.2.3.
Idle Read states ..................................................................................................... 311
7.2.4. Status states .......................................................................................................... 312
7.2.5. Reset states ........................................................................................................... 313
7.2.6. Block Erase command states ................................................................................ 314
7.2.7. Read command states ........................................................................................... 315
7.2.8. Page Program and Page Cache Program command states ................................. 318
Sample Code for CRC-16 (Informative) ........................................................................... 322
A.
Spare Size Recommendations (Informative) .................................................................... 324
B.
Device Self-Initialization with PSL (Informative) ............................................................... 325
C.
ICC Measurement Methodology ....................................................................................... 326
D.
E.
Measuring Timing Parameters to/From Tri-State ............................................................. 333
F. EZ NAND: End to End Data Path Protection (INFORMATIVE) ........................................... 334
vi
1. Introduction
1.1.
Goals and Objectives
This specification defines a standardized NAND Flash device interface that provides the means
for a system to be designed that supports a range of NAND Flash devices without direct design
pre-association. The solution also provides the means for a system to seamlessly make use of
new NAND devices that may not have existed at the time that the system was designed.
Some of the goals and requirements for the specification include:
• Support range of device capabilities and new unforeseen innovation
• Consistent with existing NAND Flash designs providing orderly transition to ONFI
• Capabilities and features are self-described in a parameter page such that hard-coded
chip ID tables in the host are not necessary
• Flash devices are interoperable and do not require host changes to support a new Flash
device
• Define a higher speed NAND interface that is compatible with existing NAND Flash
interface
• Allow for separate core (Vcc) and I/O (VccQ) power rails
• Support for offloading NAND lithography specific functionality to a controller stacked in
the NAND package (EZ NAND)
1.2.
EZ NAND Overview
EZ NAND includes the control logic packaged together with NAND to perform the NAND
management functionality that is lithography specific (e.g. ECC), while retaining the NAND
protocol infrastructure. EZ NAND delivers an ECC offloaded solution with minimal command
and/or protocol changes. The device parameter page will specify if EZ NAND is supported.
1.3.
References
The specification makes reference to the following specifications and standards:
•
JEDEC SSTL_18 standard. Standard is available at http://www.jedec.org.
1.4.
Definitions, abbreviations, and conventions
1.4.1. Definitions and Abbreviations
The terminology used in this specification is intended to be self-sufficient and does not rely on
overloaded meanings defined in other specifications. Terms with specific meaning not directly
clear from the context are clarified in the following sections.
1.4.1.1.
address
The address is comprised of a row address and a column address. The row address identifies
the page, block, and LUN to be accessed. The column address identifies the byte or word within
a page to access. The least significant bit of the column address shall always be zero in the NV-
DDR, NV-DDR2, or NV-DDR3 data interfaces.
1.4.1.2.
asynchronous
Asynchronous is when data is latched with the WE_n signal for writes and RE_n signal for reads.
1
1.4.1.3.
block
Consists of multiple pages and is the smallest addressable unit for erase operations.
1.4.1.4.
column
The byte (x8 devices) or word (x16 devices) location within the page register.
1.4.1.5.
data burst
A data burst is a continuous set of data input or data output cycles without a pause. Specifically,
there is not more than a data cycle time of pause within the data sequence.
1.4.1.5.1.
data burst end
The host issues a new command after exiting the data burst. This exits NAND read mode and
ends the data burst.
1.4.1.5.2.
data burst exit
The host brings CE_n, ALE or CLE high during the data burst. ODT is off (if enabled) when in
exit state and warmup cycles are re-issued (if enabled) if the data burst is continued after exit.
1.4.1.5.3.
data burst pause
The host stops DQS (input burst) or RE (output burst) during data burst. ODT (if enabled) stays
enabled the entire pause time and warmup cycles (if enabled) are not re-issued when continuing
the data burst from pause.
1.4.1.6.
DDR
Acronym for double data rate.
1.4.1.7.
defect area
The defect area is where factory defects are marked by the manufacturer. Refer to section 3.3.
1.4.1.8.
Deselected (ODT state)
When on-die termination is used, the LUN may be in a Deselected, Selected, or Sniff state with
associated actions for each. Refer to section 4.16.
1.4.1.9.
device
The packaged NAND unit. A device consists of one or more NAND Targets.
1.4.1.10.
differential signaling
Differential signaling is a method of transmitting information by means of two complementary
signals. The opposite technique is called single-ended signaling. The RE_n and DQS signals
may each have complementary signals enabled to improve noise immunity, refer to section
4.10.2.
1.4.1.11.
Dword
A Dword is thirty-two (32) bits of data. A Dword may be represented as 32 bits, as two adjacent
words, or as four adjacent bytes. When shown as bits the least significant bit is bit 0 and most
significant bit is bit 31. The most significant bit is shown on the left. When shown as words the
2
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