2019-04-20
Why Impedance Match?
High impedance (Open) or Low
impedance (Short) Load?
Hard to implement for high frequencies.
Position dependent.
No power transfer is possible!
Multiple reflections can result in group delay
variations that can produce undesired
intermodulation in broadband systems.
Unstable in active device measurement
The Concept of
Impedance Matching
中華大學 通訊系 田慶誠
tien@chu.edu.tw
03 5186030
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Why Impedance Match?
RF Amplifier Block Diagram
Advantages of the matched load condition
Ability to measure and adjust to known conditions.
Uniquely removes the requirement for a specific
reference plane.
Power-handling capacity of a transmission line is
maximum.
Easily interconnect a number of different
components into a system
50
Input
Matching
Network
DC Bias
Circuit
Transistor
Output
Matching
Network
50
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Thevenin’s Equivalent
RF Source
Maximum Power Transfer
from Source
2019-04-20
Z0=50
+
VS
-
P+
Pr
PIN
ZIN
VS: Thevenin’s equivalent source voltage
Z0(50): Thevenin’s equivalent source impedance
只需考慮Source能提供多少入射功率P+,至於50消
耗多少功率及VS電壓位於電路內部的那一個位置並無
物理意義。
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Incident Power of RF Source
50
+
VS
-
P+
Pr
PIN
50
Reflected power Pr=0 as ZIN=50.
Incident power P+=PAVS=PIN=
(將不隨負載ZIN而變)
2
1
2
2/V
S
50
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PL
PAVS
0
50
Maximum available power from source (PAVS)
is transferred to load when ZIN=Z0=50.
ZIN()
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Incident Voltage (V+) and
Current (I+) Waves
50
50
+
VS
-
+
VS
-
V+
V-
I+
I-
VIN
50
No Reflection
V-=0, I-=0
V+=VIN=VS/2
IIN
50
V
I
50
當沒有反射發生時,此時的電壓和電流即為入射
電壓及入射電流。
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2
Superposition of Voltages
and Currents
Z0=50
+
VS
-
I+
I-
V+
V-
+
VIN
-
IIN
ZIN
電壓及電流疊加原理:V++V-= VIN
I+ - I- = IIN
V
I
50
Z
0
IN
Z
V
IN
I
IN
輸入阻抗
V
I
V
I
特性阻抗
2019-04-20
Impedance Mismatch
電路、傳輸線特性如同日常生活中的水管
管徑(特性阻抗)不同將造成反射
A2
A1
V
I
Z
0
截面積 A= 流量 Q / 流速 v
特性阻抗 Z0= 入射電壓 V+ / 入射電流 I+
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Input Impedance, ZIN v.s.
Voltage Reflection Coefficient,
Impedance, Z v.s.
Voltage Reflection Coefficient,
V
V
Z
Z
IN
IN
Z
Z
0
0
Z
IN
V
IN
I
IN
Z
0
1
1
V- = V+
V
IN
1(
I
IN
1(
)
V)
V
Z
j
i
r
XjRZ
z
r
xj
Z
Z
0
1
1
Z0=Reference impedance
z= Normalized impedance
r= Normalized resistance
x= Normalized reactance
0
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3
Impedance Plane and
Smith (Z) Chart
Admittance, Y v.s.
Voltage Reflection Coefficient,
+jx
r=0
r=1
x=1
r=0
z=0
x=0
z=0
r
x=-1
x=1
r=1
x=0
x=-1
-jx
Devised by P. H. Smith, January 1939.
j
i
r
Y
y
g
bj
Y
Y
0
1
1
1
Z
BjG
Y0=Reference admittance
y= Normalized admittance
g= Normalized conductance
b= Normalized susceptance
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+jb
g=0
g=1
g=0
b=0
Admittance Plane and
Smith (Y) Chart
g=0
b=1
g
b=-1
b=-1
g=1
b=0
b=1
y=0
-jb
Devised by P. H. Smith, January 1939.
e
g
a
t
l
o
V
1.5
1
0.5
Z0=50
0
-0.5
-1
2V
-1.5
0
Physical Phenomenon of
Standing Wave
V(x,t)
ZIN=
50+j50
0.5
1
1.5
2
2.5
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Distance x
(Wavelength)
16
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4
Standing Wave Pattern
Standing Wave Pattern
e
g
a
t
l
o
V
1.5
1
0.5
Z0=50
0
-0.5
-1
2V
-1.5
0
V(x,t)
0.5
1
1.5
2
VMIN
VMAX
ZIN=
50+j50
2.5
3
Distance
(Wavelength)
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Voltage Standing Wave Ratio,
VSWR
VSWR
V
MAX
V
MIN
1
1
VSWR
VSWR
1
1
工業界一般RF電路要求標準: VSWR<2.0
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Power Reflection and
Transmission
Z0=50
+
VS
-
P+
Pr
PIN
ZIN
P
2
V
50
1
2
P
r
1
2
2
V
50
2
P
Power conservation rule: P+= Pr + PIN
P
IN
1(P
2
)
Return Loss
20
log
)dB(RL
)dB(RL
Return loss, RL(dB)
P
r
P
dBm(P)
)
log
10
20
RL
dBm(Pr
One-port network
log
Two-port network
log
log
20
20
RL
RL
1
2
20
log
S
11
)dB(S
11
1
2
20
20
log
S
11
log
S
22
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5
Mismatch Factor and
Mismatch Loss
Mismatch Factor, M
M
P
L
P
1
2
M1
Mismatch Loss, ML(dB)
ML
10
)Mlog(
10
1
log(
2
)
P
L
dBm(PMP
dBm(P)
)
L
)dB(ML
2019-04-20
Questions
已知放大器輸入端的VSWR=2.0,若在輸
入端將P+=0dBm入射功率送入, 請計算
|1|=|S11|= ?
S11(dB)= ? dB
RL1= ? dB
Pr= ? dBm
ML1= ? dB
PIN(進入放大器的功率)= ? dBm
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Answers
|1|=|S11|= (2.0-1)/(2.0+1)= 1/3
S11(dB)= 20log(1/3)= -9.54dB
RL1= 9.54dB
Pr= 0dBm – 9.54dB= -9.54dBm
ML1= -10log(1-(1/3)2)= 0.51dB
PL= 0dBm- 0.51dB= -0.51dBm
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Insertion Loss
For a two-port network
50
P+
Pr
PIN
S
11
S
21
S
S
12
22
PL
50
Insertion
Loss
)dB(
IL
10
log
P
L
P
20
log
S
21
2
S
21
P
L
P
P
IN
P
Mismatch
)
(
中華大學 通訊系
P
L
P
IN
Internal
(
loss
)
24
6
Power Dissipation
Insertion Gain
2019-04-20
For a passive network
50
PIN
P+
Pr
Pd
PL
50
Power conservation rule:
P+= Pr +PL +Pd
Dissipated power Pd
P
L
P
d
P
r
P
S1(P
11
2
S
21
2
)
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Impedances and Reflection
Coefficients in an Amplifier Circuit
50
Input
Matching
Network
Output
Matching
Network
50
Transistor
a
Za
S
ZS
IN
ZIN
OUT
ZOUT
L
ZL
b
Zb
For an amplifier circuit
50
PIN
P+
Pr
GInternal
Insertion
)dB(Gain
10
log
PL
50
P
L
P
20
log
S
21
2
S
21
P
L
P
P
IN
P
Mismatch
)
(
中華大學 通訊系
P
L
P
IN
Internal
(
)
gain
26
Input and Output VSWR
of Amplifier
50
50
a
Za (包含50負載)
b
Zb (包含50 Source)
Output reflection coefficient b
Input reflection coefficient a
a
S
11
VSWR
1
50
50
a
Z
Z
a
1
a
1
a
b
S
22
VSWR
2
50
50
b
Z
Z
b
1
b
1
b
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Source Impedance ZS and
Reflection Coefficient S
50
50
ZS
Input
Matching
Network
Input source
is closed
S
ZS
S
Z
Z
S
S
50
50
S
ZS
Thevenin’s
equivalent circuit
2019-04-20
Input Impedance ZIN and
Reflection Coefficient IN
50
Transistor
IN
ZIN
IN
Z
Z
IN
IN
50
50
Output
Matching
Network
50
L
ZL
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常見錯誤觀念(一)
50
Input
Matching
Network
Transistor
S
ZS
IN
ZIN
S
Z
Z
S
S
Z
Z
IN
IN
IN
Z
Z
IN
IN
Z
Z
S
S
Load Impedance ZL and
Reflection Coefficient L
50
L
ZL
Output
Matching
Network
50
ZL
L
ZL
Thevenin’s
equivalent circuit
L
Z
Z
L
L
50
50
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