module modulation(reset,clk,data,busy,d_out,d0); input reset, clk; input [7:0]data; output [7:0]d_out; //input of dac output busy,d0; reg[7:0] d_out; reg[7:0] data_buf; reg[3:0] stat0,stat1; reg[11:0]cnt; reg busy; reg d0; always@(posedge clk) d0<=data_buf[0]; always@(posedge clk) if (reset==1) cnt<=0; else case(cnt) 95:begin data_buf<=data_buf>>1;cnt<=cnt+1'b1;busy<=0;end 191:begin data_buf<=data_buf>>1;cnt<=cnt+1'b1;end 287:begin data_buf<=data_buf>>1;cnt<=cnt+1'b1;end 

383:begin data_buf<=data_buf>>1;cnt<=cnt+1'b1;end 479:begin data_buf<=data_buf>>1;cnt<=cnt+1'b1;end 575:begin data_buf<=data_buf>>1;cnt<=cnt+1'b1;end 672:begin data_buf<=data_buf>>1;cnt<=cnt+1'b1;busy<=1;end 768:begin data_buf<=data; cnt<=0;end default: cnt<=cnt+1'b1; endcase always@(posedge clk) if (data_buf[0]==0) case(stat0) 0:begin d_out<=128;stat0<=stat0+1'b1;end 1:begin d_out<=128+71;stat0<=stat0+1'b1;end 2:begin d_out<=128+100;stat0<=stat0+1'b1;end 3:begin d_out<=128+71;stat0<=stat0+1'b1;end 4:begin d_out<=128;stat0<=stat0+1'b1;end 5:begin d_out<=128-71;stat0<=stat0+1'b1;end 6:begin d_out<=128-100;stat0<=stat0+1'b1;end 7:begin d_out<=128-71;stat0<=0;stat1<=0;end default : begin d_out<=128;stat0<=1'b0;end endcase else 

case(stat1) 0:begin d_out<=128;stat1<=stat1+1'b1;end 1:begin d_out<=128+82;stat1<=stat1+1'b1;end 2:begin d_out<=128+82;stat1<=stat1+1'b1;end 3:begin d_out<=128;stat1<=stat1+1'b1;end 4:begin d_out<=128-82;stat1<=stat1+1'b1;end 5:begin d_out<=128-82;stat1<=0;stat0<=0;end default: begin d_out<=128;stat1<=1'b0;end endcase endmodule