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MIPI的 DSI协议.pdf
1 Overview
1.1 Scope
1.2 Purpose
2 Terminology (informative)
2.1 Definitions
2.2 Abbreviations
2.3 Acronyms
3 References (informative)
3.1 Display Bus Interface Standards for Parallel Signaling (DBI and DBI-2)
3.2 Display Pixel Interface Standards for Parallel Signaling (DPI and DPI-2)
3.3 MIPI Alliance Standard for Display Command Set (DCS)
3.4 MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2)
3.5 MIPI Alliance Specification for D-PHY (D-PHY)
4 DSI Introduction
4.1 DSI Layer Definitions
4.2 Command and Video Modes
4.2.1 Command Mode
4.2.2 Video Mode Operation
4.2.3 Virtual Channel Capability
5 DSI Physical Layer
5.1 Data Flow Control
5.2 Bidirectionality and Low Power Signaling Policy
5.3 Command Mode Interfaces
5.4 Video Mode Interfaces
5.5 Bidirectional Control Mechanism
5.6 Clock Management
5.6.1 Clock Requirements
5.6.2 Clock Power and Timing
5.7 System Power-Up and Initialization
6 Multi-Lane Distribution and Merging
6.1 Multi-Lane Interoperability and Lane-number Mismatch
6.1.1 Clock Considerations with Multi-Lane
6.1.2 Bi-directionality and Multi-Lane Capability
6.1.3 SoT and EoT in Multi-Lane Configurations
7 Low-Level Protocol Errors and Contention
7.1 Low-Level Protocol Errors
7.1.1 SoT Error
7.1.2 SoT Sync Error
7.1.3 EoT Sync Error
7.1.4 Escape Mode Entry Command Error
7.1.5 LP Transmission Sync Error
7.1.6 False Control Error
7.2 Contention Detection and Recovery
7.2.1 Contention Detection in LP Mode
7.2.2 Contention Recovery Using Timers
7.3 Additional Timers
7.3.1 Turnaround Acknowledge Timeout (TA_TO)
7.3.2 Peripheral Reset Timeout (PR_TO)
7.4 Acknowledge and Error Reporting Mechanism
8 DSI Protocol
8.1 Multiple Packets per Transmission
8.2 Packet Composition
8.3 Endian Policy
8.4 General Packet Structure
8.4.1 Long Packet Format
8.4.2 Short Packet Format
8.5 Common Packet Elements
8.5.1 Data Identifier Byte
8.5.2 Error Correction Code
8.6 Interleaved Data Streams
8.6.1 Interleaved Data Streams and Bi-directionality
8.7 Processor to Peripheral Direction (Processor-Sourced) Packet Data Types
8.8 Processor-to-Peripheral Transactions – Detailed Format Description
8.8.1 Sync Event (H Start, H End, V Start, V End), Data Type = xx 0001 (x1h)
8.8.2 EoTp, Data Type = 00 1000 (08h)
8.8.3 Color Mode Off Command, Data Type = 00 0010 (02h)
8.8.4 Color Mode On Command, Data Type = 01 0010 (12h)
8.8.5 Shutdown Peripheral Command, Data Type = 10 0010 (22h)
8.8.6 Turn On Peripheral Command, Data Type = 11 0010 (32h)
8.8.7 Generic Short WRITE Packet with 0, 1, or 2 parameters, Data Types = 00 0011 (03h), 01 0011 (13h), 10 0011 (23h), Respectively
8.8.8 Generic READ Request with 0, 1, or 2 Parameters, Data Types = 00 0100 (04h), 01 0100 (14h), 10 0100(24h), Respectively
8.8.9 DCS Commands
8.8.10 Set Maximum Return Packet Size, Data Type = 11 0111 (37h)
8.8.11 Null Packet (Long), Data Type = 00 1001 (09h)
8.8.12 Blanking Packet (Long), Data Type = 01 1001 (19h)
8.8.13 Generic Long Write, Data Type = 10 1001 (29h)
8.8.14 Packed Pixel Stream, 16-bit Format, Long packet, Data Type 00 1110 (0Eh)
8.8.15 Packed Pixel Stream, 18-bit Format, Long packet, Data type = 01 1110 (1Eh)
8.8.16 Pixel Stream, 18-bit Format in Three Bytes, Long packet, Data Type = 10 1110 (2Eh)
8.8.17 Packed Pixel Stream, 24-bit Format, Long packet, Data Type = 11 1110 (3Eh)
8.8.18 DO NOT USE and Reserved Data Types
8.9 Peripheral-to-Processor (Reverse Direction) LP Transmissions
8.9.1 Packet Structure for Peripheral-to-Processor LP Transmissions
8.9.2 System Requirements for ECC and Checksum and Packet Format
8.9.3 Appropriate Responses to Commands and ACK Requests
8.9.4 Format of Acknowledge and Error Report and Read Response Data Types
8.9.5 Error Reporting Format
8.10 Peripheral-to-Processor Transactions – Detailed Format Description
8.10.1 Acknowledge and Error Report, Data Type 00 0010 (02h)
8.10.2 Generic Short Read Response, 1 or 2 Bytes, Data Types = 01 0001 or 01 0010, Respectively
8.10.3 Generic Long Read Response with Optional Checksum, Data Type = 01 1010 (1Ah)
8.10.4 DCS Long Read Response with Optional Checksum, Data Type 01 1100 (1Ch)
8.10.5 DCS Short Read Response, 1 or 2 Bytes, Data Types = 10 0001 or 10 0010, Respectively
8.10.6 Multiple Transmissions and Error Reporting
8.10.7 Clearing Error Bits
8.11 Video Mode Interface Timing
8.11.1 Transmission Packet Sequences
8.11.2 Non-Burst Mode with Sync Pulses
8.11.3 Non-Burst Mode with Sync Events
8.11.4 Burst Mode
8.11.5 Parameters
8.12 TE Signaling in DSI
9 Error-Correcting Code (ECC) and Checksum
9.1 Packet Header Error Detection/Correction
9.2 Hamming Code Theory
9.3 Hamming-modified Code Applied to DSI Packet Headers
9.4 ECC Generation on the Transmitter
9.5 Applying ECC on the Receiver
9.6 Checksum Generation for Long Packet Payloads
10 Compliance, Interoperability, and Optional Capabilities
10.1 Display Resolutions
10.2 Pixel Formats
10.2.1 Video Mode
10.2.2 Command Mode
10.3 Number of Lanes
10.4 Maximum Lane Frequency
10.5 Bidirectional Communication
10.6 ECC and Checksum Capabilities
10.7 Display Architecture
10.8 Multiple Peripheral Support
10.9 EoTp Support and Interoperability
Annex A Contention Detection and Recovery Mechanisms (informative)
A.1 PHY Detected Contention
A.1.1 Protocol Response to PHY Detected Faults
Annex B Checksum Generation Example (informative)
Version 1.01.00 r11 21-Feb-2008
DRAFT MIPI Alliance Specification for DSI
DRAFT MIPI Alliance Specification for Display
Serial Interface
Draft Version 1.01.00 Release 11 – 21 February 2008
Further technical changes to this document are expected as work continues in the Display Working Group
Copyright © 2005-2008 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
Version 1.01.00 r11 21-Feb-2008
DRAFT MIPI Alliance Specification for DSI
NOTICE OF DISCLAIMER
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled
by any of the authors or developers of this material or MIPI. The material contained herein is provided on
an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS
AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all
other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if
any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of
accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of
negligence.
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD
TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY
AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR
MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE
GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER
CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR
ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,
WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is
further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the
contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;
and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance
with the contents of this Document. The use or implementation of the contents of this Document may
involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,
patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI
does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any
IPR or claims of IPR as respects the contents of this Document or otherwise.
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:
MIPI Alliance, Inc.
c/o IEEE-ISTO
445 Hoes Lane
Piscataway, NJ 08854
Attn: Board Secretary
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Contents
Draft Version 1.01.00 Release 11 – 21 February 2008 .................................................................................... i
1 Overview ............................................................................................................................................... 11
1.1
1.2
Scope ............................................................................................................................................. 11
Purpose .......................................................................................................................................... 11
2
Terminology (informative) .................................................................................................................... 12
2.1
2.2
2.3
Definitions ..................................................................................................................................... 12
Abbreviations ................................................................................................................................ 13
Acronyms ...................................................................................................................................... 13
3 References (informative) ....................................................................................................................... 16
3.1
3.2
Display Bus Interface Standards for Parallel Signaling (DBI and DBI-2) .................................... 16
Display Pixel Interface Standards for Parallel Signaling (DPI and DPI-2) ................................... 16
3.3 MIPI Alliance Standard for Display Command Set (DCS) ........................................................... 17
3.4 MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) ..................................................... 17
3.5 MIPI Alliance Specification for D-PHY (D-PHY) ........................................................................ 17
4 DSI Introduction .................................................................................................................................... 18
4.1
4.2
DSI Layer Definitions ................................................................................................................... 19
Command and Video Modes ......................................................................................................... 20
4.2.1
4.2.2
4.2.3
Command Mode .................................................................................................................... 20
Video Mode Operation .......................................................................................................... 20
Virtual Channel Capability .................................................................................................... 21
5 DSI Physical Layer ................................................................................................................................ 22
Data Flow Control ......................................................................................................................... 22
Bidirectionality and Low Power Signaling Policy ......................................................................... 22
Command Mode Interfaces ........................................................................................................... 23
Video Mode Interfaces .................................................................................................................. 23
Bidirectional Control Mechanism .................................................................................................. 23
Copyright © 2005-2008 MIPI Alliance, Inc. All rights reserved.
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5.1
5.2
5.3
5.4
5.5
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5.6
Clock Management ........................................................................................................................ 24
5.6.1
5.6.2
Clock Requirements .............................................................................................................. 24
Clock Power and Timing ....................................................................................................... 25
5.7
System Power-Up and Initialization .............................................................................................. 25
6 Multi-Lane Distribution and Merging ................................................................................................... 27
6.1 Multi-Lane Interoperability and Lane-number Mismatch ............................................................. 28
6.1.1
6.1.2
6.1.3
Clock Considerations with Multi-Lane .................................................................................. 29
Bi-directionality and Multi-Lane Capability ......................................................................... 29
SoT and EoT in Multi-Lane Configurations .......................................................................... 29
7
Low-Level Protocol Errors and Contention ........................................................................................... 32
7.1
Low-Level Protocol Errors ............................................................................................................ 32
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
SoT Error ............................................................................................................................... 32
SoT Sync Error ...................................................................................................................... 33
EoT Sync Error ...................................................................................................................... 33
Escape Mode Entry Command Error ..................................................................................... 34
LP Transmission Sync Error .................................................................................................. 34
False Control Error ................................................................................................................ 34
7.2
Contention Detection and Recovery .............................................................................................. 35
7.2.1
7.2.2
Contention Detection in LP Mode ......................................................................................... 35
Contention Recovery Using Timers ...................................................................................... 35
7.3
Additional Timers .......................................................................................................................... 38
7.3.1
7.3.2
Turnaround Acknowledge Timeout (TA_TO) ....................................................................... 38
Peripheral Reset Timeout (PR_TO) ....................................................................................... 38
7.4
Acknowledge and Error Reporting Mechanism ............................................................................ 39
8 DSI Protocol .......................................................................................................................................... 40
8.1 Multiple Packets per Transmission ................................................................................................ 40
Packet Composition ....................................................................................................................... 41
Endian Policy ................................................................................................................................. 42
Copyright © 2005-2008 MIPI Alliance, Inc. All rights reserved.
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8.2
8.3
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8.4
General Packet Structure ............................................................................................................... 42
8.4.1
8.4.2
Long Packet Format ............................................................................................................... 42
Short Packet Format .............................................................................................................. 44
8.5
Common Packet Elements ............................................................................................................. 44
8.5.1
8.5.2
Data Identifier Byte ............................................................................................................... 44
Error Correction Code ........................................................................................................... 45
8.6
Interleaved Data Streams ............................................................................................................... 45
8.6.1
Interleaved Data Streams and Bi-directionality ..................................................................... 46
8.7
8.8
Processor to Peripheral Direction (Processor-Sourced) Packet Data Types .................................. 46
Processor-to-Peripheral Transactions – Detailed Format Description ........................................... 47
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
Sync Event (H Start, H End, V Start, V End), Data Type = xx 0001 (x1h) ........................... 47
EoTp, Data Type = 00 1000 (08h) ......................................................................................... 48
Color Mode Off Command, Data Type = 00 0010 (02h) ...................................................... 49
Color Mode On Command, Data Type = 01 0010 (12h) ....................................................... 49
Shutdown Peripheral Command, Data Type = 10 0010 (22h) ............................................... 49
Turn On Peripheral Command, Data Type = 11 0010 (32h) ................................................. 49
8.8.7
Generic Short WRITE Packet with 0, 1, or 2 parameters, Data Types = 00 0011 (03h), 01
0011 (13h), 10 0011 (23h), Respectively .............................................................................................. 49
8.8.8
Generic READ Request with 0, 1, or 2 Parameters, Data Types = 00 0100 (04h), 01 0100
(14h), 10 0100(24h), Respectively ........................................................................................................ 49
8.8.9
DCS Commands .................................................................................................................... 50
8.8.10
Set Maximum Return Packet Size, Data Type = 11 0111 (37h) ............................................ 51
8.8.11 Null Packet (Long), Data Type = 00 1001 (09h) ................................................................... 51
8.8.12 Blanking Packet (Long), Data Type = 01 1001 (19h)............................................................ 51
8.8.13 Generic Long Write, Data Type = 10 1001 (29h) .................................................................. 51
8.8.14
Packed Pixel Stream, 16-bit Format, Long packet, Data Type 00 1110 (0Eh) ...................... 52
8.8.15
Packed Pixel Stream, 18-bit Format, Long packet, Data type = 01 1110 (1Eh) .................... 53
8.8.16
Pixel Stream, 18-bit Format in Three Bytes, Long packet, Data Type = 10 1110 (2Eh) ....... 54
8.8.17
Packed Pixel Stream, 24-bit Format, Long packet, Data Type = 11 1110 (3Eh) ................... 55
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8.8.18 DO NOT USE and Reserved Data Types .............................................................................. 55
8.9
Peripheral-to-Processor (Reverse Direction) LP Transmissions ................................................... 56
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
Packet Structure for Peripheral-to-Processor LP Transmissions ........................................... 56
System Requirements for ECC and Checksum and Packet Format ....................................... 57
Appropriate Responses to Commands and ACK Requests.................................................... 57
Format of Acknowledge and Error Report and Read Response Data Types ......................... 58
Error Reporting Format ......................................................................................................... 59
8.10 Peripheral-to-Processor Transactions – Detailed Format Description ........................................... 60
8.10.1 Acknowledge and Error Report, Data Type 00 0010 (02h) ................................................... 61
8.10.2 Generic Short Read Response, 1 or 2 Bytes, Data Types = 01 0001 or 01 0010, Respectively61
8.10.3 Generic Long Read Response with Optional Checksum, Data Type = 01 1010 (1Ah) ......... 62
8.10.4 DCS Long Read Response with Optional Checksum, Data Type 01 1100 (1Ch) ................. 62
8.10.5 DCS Short Read Response, 1 or 2 Bytes, Data Types = 10 0001 or 10 0010, Respectively . 62
8.10.6 Multiple Transmissions and Error Reporting ........................................................................ 62
8.10.7 Clearing Error Bits ................................................................................................................. 63
8.11 Video Mode Interface Timing ....................................................................................................... 63
8.11.1
Transmission Packet Sequences ............................................................................................ 63
8.11.2 Non-Burst Mode with Sync Pulses ........................................................................................ 64
8.11.3 Non-Burst Mode with Sync Events ....................................................................................... 65
8.11.4 Burst Mode ............................................................................................................................ 66
8.11.5
Parameters ............................................................................................................................. 67
8.12 TE Signaling in DSI ...................................................................................................................... 68
9
Error-Correcting Code (ECC) and Checksum ....................................................................................... 70
Packet Header Error Detection/Correction .................................................................................... 70
Hamming Code Theory ................................................................................................................. 70
Hamming-modified Code Applied to DSI Packet Headers ........................................................... 70
ECC Generation on the Transmitter .............................................................................................. 74
Applying ECC on the Receiver ..................................................................................................... 75
Copyright © 2005-2008 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
vi
9.1
9.2
9.3
9.4
9.5
Version 1.01.00 r11 21-Feb-2008
DRAFT MIPI Alliance Specification for DSI
9.6
Checksum Generation for Long Packet Payloads .......................................................................... 75
10
Compliance, Interoperability, and Optional Capabilities................................................................... 77
10.1 Display Resolutions ....................................................................................................................... 77
10.2 Pixel Formats ................................................................................................................................. 78
10.2.1 Video Mode ........................................................................................................................... 78
10.2.2 Command Mode .................................................................................................................... 78
10.3 Number of Lanes ........................................................................................................................... 78
10.4 Maximum Lane Frequency ............................................................................................................ 78
10.5 Bidirectional Communication ........................................................................................................ 79
10.6 ECC and Checksum Capabilities ................................................................................................... 79
10.7 Display Architecture ...................................................................................................................... 79
10.8 Multiple Peripheral Support .......................................................................................................... 79
10.9 EoTp Support and Interoperability ................................................................................................ 79
Annex A Contention Detection and Recovery Mechanisms (informative) ................................................... 80
A.1
PHY Detected Contention ............................................................................................................. 80
A.1.1
Protocol Response to PHY Detected Faults ........................................................................... 80
Annex B Checksum Generation Example (informative) ............................................................................... 86
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Version 1.01.00 r11 21-Feb-2008
Figures
Figure 1 DSI Transmitter and Receiver Interface ......................................................................................... 18
DRAFT MIPI Alliance Specification for DSI
Figure 2 DSI Layers ..................................................................................................................................... 19
Figure 3 Basic HS Transmission Structure ................................................................................................... 22
Figure 4 Power-Up Sequencing Example ..................................................................................................... 26
Figure 5 Lane Distributor Conceptual Overview ......................................................................................... 27
Figure 6 Lane Merger Conceptual Overview ............................................................................................... 28
Figure 7 Four-Lane Transmitter with Two-Lane Receiver Example ........................................................... 29
Figure 8 Two Lane HS Transmission Example ............................................................................................ 30
Figure 9 Three Lane HS Transmission Example .......................................................................................... 31
Figure 10 HS Transmission Examples with EoTp disabled ......................................................................... 41
Figure 11 HS Transmission Examples with EoTp enabled .......................................................................... 41
Figure 12 Endian Example (Long Packet) .................................................................................................... 42
Figure 13 Long Packet Structure .................................................................................................................. 43
Figure 14 Short Packet Structure .................................................................................................................. 44
Figure 15 Data Identifier Byte ...................................................................................................................... 44
Figure 16 Interleaved Data Stream Example with EoTp disabled ................................................................ 45
Figure 17 Logical Channel Block Diagram (Receiver Case) ....................................................................... 46
Figure 18 16-bit per Pixel – RGB Color Format, Long packet .................................................................... 52
Figure 19 18-bit per Pixel (Packed) – RGB Color Format, Long packet ..................................................... 53
Figure 20 18-bit per Pixel (Loosely Packed) – RGB Color Format, Long packet ........................................ 54
Figure 21 24-bit per Pixel – RGB Color Format, Long packet .................................................................... 55
Figure 22 Video Mode Interface Timing Legend ......................................................................................... 64
Figure 23 Video Mode Interface Timing: Non-Burst Transmission with Sync Start and End ..................... 65
Figure 24 Video Mode Interface Timing: Non-burst Transmission ............................................................. 66
Figure 25 Video Mode Interface Timing: Burst Transmission ..................................................................... 67
Figure 26 24-bit ECC generation on TX side ............................................................................................... 74
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