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TMS320C6455 DSP DDR2 Memory Controller.pdf
TMS320C6455/C6454 DSP DDR2 Memory Controller
Table of Contents
Preface
1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
1.3 Functional Block Diagram
1.4 Industry Standard(s) Compliance Statement
2 Peripheral Architecture
2.1 Clock Control
2.2 Memory Map
2.3 Signal Descriptions
2.4 Protocol Description(s)
2.4.1 Mode Register Set (MRS and EMRS)
2.4.2 Refresh Mode
2.4.3 Activation (ACTV)
2.4.4 Deactivation (DCAB and DEAC)
2.4.5 READ Command
2.4.6 Write (WRT) Command
2.5 Memory Width, Byte Alignment, and Endianness
2.6 Address Mapping
2.7 DDR2 Memory Controller Interface
2.7.1 Command Ordering and Scheduling, Advanced Concept
2.7.2 Command Starvation
2.7.3 Possible Race Condition
2.8 Refresh Scheduling
2.9 Self-Refresh Mode
2.10 Reset Considerations
2.11 DDR2 SDRAM Memory Initialization
2.11.1 DDR2 SDRAM Device Mode Register Configuration Values
2.11.2 DDR2 SDRAM Initialization After Reset
2.11.3 DDR2 SDRAM Initialization After Register Configuration
2.12 Interrupt Support
2.13 EDMA Event Support
2.14 Emulation Considerations
3 Using the DDR2 Memory Controller
3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM
3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
3.2.1 Programming the SDRAM Configuration Register (SDCFG)
3.2.2 Programming the SDRAM Refresh Control Register (SDRFC)
3.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)
3.2.4 Configuring the DDR2 Memory Controller Control Register (DMCCTL)
4 DDR2 Memory Controller Registers
4.1 Module ID and Revision Register (MIDR)
4.2 DDR2 Memory Controller Status Register (DMCSTAT)
4.3 SDRAM Configuration Register (SDCFG)
4.4 SDRAM Refresh Control Register (SDRFC)
4.5 SDRAM Timing 1 Register (SDTIM1)
4.6 SDRAM Timing 2 Register (SDTIM2)
4.7 Burst Priority Register (BPRIO)
4.8 DDR2 Memory Controller Control Register (DMCCTL)
Revision History
TMS320C6455/C6454 DSP
DDR2 Memory Controller
User's Guide
Literature Number: SPRU970G
December 2005– Revised June 2011
2
Copyright © 2005–2011, Texas Instruments Incorporated
SPRU970G– December 2005–Revised June 2011
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Contents
2
3
4
1.1
1.2
1.3
1.4
Preface ....................................................................................................................................... 7
Introduction ........................................................................................................................ 9
1
Purpose of the Peripheral .............................................................................................. 9
Features .................................................................................................................. 9
Functional Block Diagram .............................................................................................. 9
Industry Standard(s) Compliance Statement ....................................................................... 10
Peripheral Architecture ...................................................................................................... 11
Clock Control ........................................................................................................... 11
2.1
Memory Map ............................................................................................................ 11
2.2
Signal Descriptions .................................................................................................... 11
2.3
Protocol Description(s) ................................................................................................ 13
2.4
Memory Width, Byte Alignment, and Endianness ................................................................. 20
2.5
Address Mapping ...................................................................................................... 21
2.6
DDR2 Memory Controller Interface .................................................................................. 24
2.7
Refresh Scheduling .................................................................................................... 27
2.8
Self-Refresh Mode ..................................................................................................... 28
2.9
2.10 Reset Considerations .................................................................................................. 28
2.11 DDR2 SDRAM Memory Initialization ................................................................................ 28
Interrupt Support ....................................................................................................... 30
2.12
EDMA Event Support .................................................................................................. 30
2.13
Emulation Considerations ............................................................................................. 30
2.14
Using the DDR2 Memory Controller ..................................................................................... 31
Connecting the DDR2 Memory Controller to DDR2 SDRAM .................................................... 31
Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications .................... 35
DDR2 Memory Controller Registers ..................................................................................... 38
Module ID and Revision Register (MIDR) .......................................................................... 39
DDR2 Memory Controller Status Register (DMCSTAT) .......................................................... 40
SDRAM Configuration Register (SDCFG) .......................................................................... 41
SDRAM Refresh Control Register (SDRFC) ....................................................................... 43
SDRAM Timing 1 Register (SDTIM1) ............................................................................... 44
SDRAM Timing 2 Register (SDTIM2) ............................................................................... 46
Burst Priority Register (BPRIO) ...................................................................................... 47
DDR2 Memory Controller Control Register (DMCCTL) ........................................................... 48
Revision History ......................................................................................................................... 49
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
3.1
3.2
SPRU970G– December 2005–Revised June 2011
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Copyright © 2005–2011, Texas Instruments Incorporated
Table of Contents
3
List of Figures
www.ti.com
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26
Device Block Diagram .................................................................................................... 10
DDR2 Memory Controller Signals....................................................................................... 12
DDR2 MRS and EMRS Command...................................................................................... 14
Refresh Command ........................................................................................................ 15
ACTV Command........................................................................................................... 16
DCAB Command .......................................................................................................... 17
DEAC Command .......................................................................................................... 18
DDR2 READ Command .................................................................................................. 19
DDR2 WRT Command ................................................................................................... 20
Byte Alignment............................................................................................................. 21
Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM............................................... 22
Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM ............................................... 22
Logical Address-to-DDR2 SDRAM Address Map ..................................................................... 23
DDR2 SDRAM Column, Row, and Bank Access ..................................................................... 24
DDR2 Memory Controller FIFO Block Diagram ....................................................................... 25
Connecting to Two 16-Bit DDR2 SDRAM Devices ................................................................... 32
Connecting to a Single 16-Bit DDR2 SDRAM Device ................................................................ 33
Connecting to Two 8-Bit DDR2 SDRAM Devices..................................................................... 34
Module ID and Revision Register (MIDR).............................................................................. 39
DDR2 Memory Controller Status Register (DMCSTAT).............................................................. 40
SDRAM Configuration Register (SDCFG) ............................................................................. 41
SDRAM Refresh Control Register (SDRFC)........................................................................... 43
SDRAM Timing 1 Register (SDTIM1)................................................................................... 44
SDRAM Timing 2 Register (SDTIM2)................................................................................... 46
Burst Priority Register (BPRIO).......................................................................................... 47
DDR2 Memory Controller Control Register (DMCCTL) .............................................................. 48
4
List of Figures
Copyright © 2005–2011, Texas Instruments Incorporated
SPRU970G– December 2005–Revised June 2011
Submit Documentation Feedback
www.ti.com
List of Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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DDR2 Memory Controller Signal Descriptions......................................................................... 12
DDR2 SDRAM Commands .............................................................................................. 13
Truth Table for DDR2 SDRAM Commands............................................................................ 13
Addressable Memory Ranges ........................................................................................... 20
Bank Configuration Register Fields for Address Mapping ........................................................... 21
DDR2 Memory Controller FIFO Description ........................................................................... 24
Refresh Urgency Levels .................................................................................................. 27
Device and DDR2 Memory Controller Reset Relationship........................................................... 28
DDR2 SDRAM Mode Register Configuration.......................................................................... 29
DDR2 SDRAM Extended Mode Register 1 Configuration ........................................................... 29
SDCFG Configuration..................................................................................................... 35
DDR2 Memory Refresh Specification .................................................................................. 36
SDRFC Configuration..................................................................................................... 36
SDTIM1 Configuration .................................................................................................... 36
SDTIM2 Configuration .................................................................................................... 37
DMCCTL Configuration................................................................................................... 37
DDR2 Memory Controller Registers .................................................................................... 38
Module ID and Revision Register (MIDR) Field Descriptions ....................................................... 39
DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions ....................................... 40
SDRAM Configuration Register (SDCFG) Field Descriptions ....................................................... 41
SDRAM Refresh Control Register (SDRFC) Field Descriptions .................................................... 43
SDRAM Timing 1 Register (SDTIM1) Field Descriptions ............................................................ 44
SDRAM Timing 2 Register (SDTIM2) Field Descriptions ............................................................ 46
Burst Priority Register (BPRIO) Field Descriptions ................................................................... 47
DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions ........................................ 48
SPRU970G– December 2005–Revised June 2011
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Copyright © 2005–2011, Texas Instruments Incorporated
List of Tables
5
6
List of Tables
Copyright © 2005–2011, Texas Instruments Incorporated
SPRU970G– December 2005–Revised June 2011
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Preface
SPRU970G–December 2005–Revised June 2011
Read This First
About This Manual
This document describes the DDR2 memory controller in the TMS320C6455/C6454 digital signal
processors (DSPs).
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet. Tip: Enter the literature number in the search box provided at
www.ti.com.
SPRU189 — TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors
(DSPs).
SPRU198 — TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code for
the TMS320C6000™ DSPs and includes application program examples.
SPRU301 — TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™
integrated development environment and software tools.
SPRU321 — Code Composer Studio Application Programming Interface Reference Guide.
Describes the Code Composer Studio™ application programming interface (API), which allows you
to program custom plug-ins for Code Composer.
SPRU871 — TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signal
processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
C6000, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
SPRU970G– December 2005–Revised June 2011
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Copyright © 2005–2011, Texas Instruments Incorporated
Preface
7
8
Read This First
Copyright © 2005–2011, Texas Instruments Incorporated
SPRU970G– December 2005–Revised June 2011
Submit Documentation Feedback
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