Advanced ASIC Chip Synthesis_Using Synopsys® Design Compiler™_second edition.pdf

发布时间：2022-06-14 发布人：admin 分类：说明书资料大小：16.76M 资料格式：pdf 举报版权申诉

25a7c3a6-714b-41d9-b727-460f3a310524.pdf-第1页.png

第1页 / 共355页

25a7c3a6-714b-41d9-b727-460f3a310524.pdf-第2页.png

第2页 / 共355页

25a7c3a6-714b-41d9-b727-460f3a310524.pdf-第3页.png

第3页 / 共355页

25a7c3a6-714b-41d9-b727-460f3a310524.pdf-第4页.png

第4页 / 共355页

25a7c3a6-714b-41d9-b727-460f3a310524.pdf-第5页.png

第5页 / 共355页

25a7c3a6-714b-41d9-b727-460f3a310524.pdf-第6页.png

第6页 / 共355页

25a7c3a6-714b-41d9-b727-460f3a310524.pdf-第7页.png

第7页 / 共355页

25a7c3a6-714b-41d9-b727-460f3a310524.pdf-第8页.png

第8页 / 共355页

文本预览

http://bbs.eetop.cn

ADVANCED ASIC CHIP SYNTHESIS Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime® SECOND EDITION

Trademark Information UNIX is a registered trademark of UNIX Systems Laboratories, Inc. Verilog is a registered trademark of Cadence Design Systems, Inc. RSPF and DSPF is a trademark of Cadence Design Systems, Inc. SDF and SPEF is a trademark of Open Verilog International. Synopsys, PrimeTime, Formality, DesignPower, DesignWare and SOLV-IT! are registered trademarks of Synopsys, Inc. Design Analyzer, Design Vision, Physical Compiler, Design Compiler, DFT Compiler, VHDL Compiler, HDL Compiler, ECO Compiler, Library Compiler, Synthetic Libraries, DesignTime, Floorplan Manager, characterize, dont_touch, dont_touch_network and uniquify, are trademarks of Synopsys, Inc. SolvNET is a service mark of Synopsys, Inc. All other brand or product names mentioned in this document, are trademarks or registered trademarks of their respective companies or organizations. All ideas and concepts provided in this book are authors own, and are not endorsed by Synopsys, Inc. Synopsys, Inc. is not responsible for information provided in this book. http://bbs.eetop.cn

ADVANCED ASIC CHIP SYNTHESIS Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime® SECOND EDITION Himanshu Bhatnagar Conexant Systems, Inc. KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW http://bbs.eetop.cn

eBook ISBN: Print ISBN: 0-306-47507-3 0-7923-7644-7 ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2002 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at: http://kluweronline.com http://ebooks.kluweronline.com http://bbs.eetop.cn

To my wife Nivedita and my daughter Nayan http://bbs.eetop.cn

This Page Intentionally Left Blank http://bbs.eetop.cn

Contents Foreword Preface Acknowledgements About The Author Traditional Design Flow CHAPTER 1: ASIC DESIGN METHODOLOGY 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.2 1.2.1 1.3 Specification and RTL Coding Dynamic Simulation Constraints, Synthesis and Scan Insertion Formal Verification Static Timing Analysis using PrimeTime Placement, Routing and Verification Engineering Change Order Physical Compiler Flow Physical Synthesis Chapter Summary xv xvii xxiii xxv 1 2 4 5 6 8 10 11 12 13 16 17 http://bbs.eetop.cn

分享到：

赞收藏

资料库

Advanced ASIC Chip Synthesis_Using Synopsys® Design Compiler™_second edition.pdf

相关推荐

开发技术

热门标签

最新资料