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8位乘法器的设计.doc
8 位乘法器的设计
1.实验目的
1) 学习 MAX+plus II 软件的基本使用方法。
2) 了解 VHDL 程序的基本逻辑电路的综合设计。
2.实验内容
设计并调试好一个 8 位乘法器，并用 MAX+plus II 实验开发
系统进行系统仿真。这里的设计思路是由 8 位加法器构成的以时
序逻辑方式设计的 8 位乘法器。乘法通过逐位相加原理来实现，
从被乘数的最低为开始，若为 1，则被乘数左移后与上一次和相
加；若为 0，左移后与全零相加，直至被乘数的最高位。
8 为 乘 法 器 有 乘 法 运 算 控 制 电 路 ARICTL 、8 位 右 移 寄 存 器
SREG8B、16 为锁存器 REG16B、选通与门 ANDARITH、和 8
位加法器的 ADDER8B 逻辑构成。
3.实验条件
1) 开发软件：MAX+plus II。
2) 实验设备：装有 VISTA 系统电脑一台。
4.实验设计
1) 系统的原理框图
2) VHDL 源程序
--选通与门模块的源程序 ANDARITH.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ANDARITH IS
PORT(ABIN: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT: OUT STD_LOGIC_vector(7 DOWNTO 0));
END ENTITY ANDARITH;
ARCHITECTURE ART OF ANDARITH IS
BEGIN
PROCESS(ABIN,DIN)IS
BEGIN
FOR I IN 0 TO 7 LOOP
DOUT(I)<=DIN(I)AND ABIN;
END LOOP;
END PROCESS;
END ARCHITECTURE ART;
--4 位二进制并行加法器的源程序 ADDER4B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER4B IS
PORT(C4: IN STD_LOGIC;
A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO4: OUT STD_LOGIC);
END ENTITY ADDER4B;
ARCHITECTURE ART OF ADDER4B IS
SIGNAL S5: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL A5,B5: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
A5<='0'&A4;
B5<='0'&B4;
S5<=A5+B5+C4;
S4<=S5(3 DOWNTO 0);
CO4<=S5(4);
END ARCHITECTURE ART;
--8 位二进制加法器的源程序 ADDER8B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER8B IS
PORT(CIN: IN STD_LOGIC;
A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COUT: OUT STD_LOGIC);
END ENTITY ADDER8B;
ARCHITECTURE ART OF ADDER8B IS
COMPONENT ADDER4B IS
PORT(C4: IN STD_LOGIC;
A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO4: OUT STD_LOGIC);
END COMPONENT ADDER4B;
SIGNAL SC: STD_LOGIC;
BEGIN
U1: ADDER4B
PORT MAP(C4=>CIN,A4=>A(3 DOWNTO 0),B4=>B(3 DOWNTO 0),
S4=>S(3 DOWNTO 0),CO4=>SC);
U2: ADDER4B
PORT MAP(C4=>SC,A4=>A(7 DOWNTO 4),B4=>B(7 DOWNTO 4),
S4=>S(7 DOWNTO 4),CO4=>COUT);
END ARCHITECTURE ART;
--6 位锁存器的源程序 REG16B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG16B IS
PORT (CLK: IN STD_LOGIC;
CLR: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(8 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END ENTITY REG16B;
ARCHITECTURE ART OF REG16B IS
SIGNAL R16S: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(CLK,CLR)IS
BEGIN
IF CLR='1' THEN R16S<="0000000000000000";
ELSIF CLK'EVENT AND CLK= '1' THEN
R16S(6 DOWNTO 0)<=R16S(7 DOWNTO 1);
R16S(15 DOWNTO 7)<=D;
END IF;
END PROCESS;
Q<=R16S;
END ARCHITECTURE ART;
--8 位右移寄存器的源程序 SREG8B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SREG8B IS
PORT(CLK: IN STD_LOGIC;
LOAD: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
QB: OUT STD_LOGIC);
END ENTITY SREG8B;
ARCHITECTURE ART OF SREG8B IS
SIGNAL REG8B: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK,LOAD)IS
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF LOAD='1' THEN REG8B<=DIN;
ELSE REG8B(6 downto 0)<=REG8B(7 DOWNTO 1);
END IF;
END IF;
END PROCESS;
QB<=REG8B(0);
END ARCHITECTURE ART;
--乘法运算控制器的源程序 ARICTL.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PORT(CLK:IN STD_LOGIC;
START:IN STD_LOGIC;
ENTITY ARICTL IS
ARIEND:OUT STD_LOGIC;
CLKOUT: OUT STD_LOGIC;
RSTALL: OUT STD_LOGIC);
END ENTITY ARICTL;
ARCHITECTURE ART OF ARICTL IS
SIGNAL CNT4B: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
RSTALL<=START;
PROCESS(CLK,START)IS
BEGIN
IF START='1'THEN CNT4B<="0000";
ELSIF CLK'EVENT AND CLK='1'THEN
IF CNT4B<8 THEN
CNT4B <=CNT4B+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,CNT4B,START)IS
BEGIN
IF START='0' THEN
IF CNT4B<8 THEN
CLKOUT <=CLK;ARIEND<='0';
ELSE CLKOUT<='0';ARIEND<='1';
END IF;
ELSE CLKOUT<=CLK;ARIEND<='0';
END IF;
END PROCESS;
END ARCHITECTURE ART;
--8 位乘法器的源程序 MULTI8X8.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MULTI8X8 IS
PORT(CLK:IN STD_LOGIC;
START:IN STD_LOGIC;
A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ARIEND:OUT STD_LOGIC;
DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END ENTITY MULTI8X8;
ARCHITECTURE ART OF MULTI8X8 IS
COMPONENT ARICTL IS
PORT(CLK:IN STD_LOGIC;START:IN STD_LOGIC;
CLKOUT:OUT STD_LOGIC; RSTALL:OUT STD_LOGIC;
ARIEND: OUT STD_LOGIC);
END COMPONENT ARICTL;
COMPONENT ANDARITH IS
PORT(ABIN:IN STD_LOGIC;
DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT ANDARITH;
COMPONENT ADDER8B IS
PORT(CIN: IN STD_LOGIC;
A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COUT: OUT STD_LOGIC);
END COMPONENT ADDER8B ;
COMPONENT SREG8B IS
PORT(CLK: IN STD_LOGIC;
LOAD: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
QB: OUT STD_LOGIC);
END COMPONENT SREG8B ;
COMPONENT REG16B IS
PORT (CLK: IN STD_LOGIC;
CLR: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(8 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END COMPONENT REG16B ;
SIGNAL S1: STD_LOGIC;
SIGNAL S2: STD_LOGIC;
SIGNAL S3: STD_LOGIC;
SIGNAL S4: STD_LOGIC;
SIGNAL S5: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL S6: STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL S7: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
DOUT<=S7; S1<='0';
U1:ARICTL PORT MAP(CLK=>CLK,START=>START,
DOWNTO 0));
END ARCHITECTURE ART;
CLKOUT=>S2,RSTALL=>S3,ARIEND=>ARIEND);
U2:SREG8B PORT MAP(CLK=>S2,LOAD=>S3,
DIN=>A,QB=>S4);
U3:ANDARITH PORT MAP(ABIN=>S4,DIN=>B,DOUT=>S5);
U4:ADDER8B PORT MAP(CIN=>S1,A=>S7(15 DOWNTO 8),
B=>S5,S=>S6(7 DOWNTO 0),COUT=>S6(8));
U5:REG16B PORT MAP(CLK=>S2,CLR=>S3,D=>S6(8 DOWNTO 0),Q=>S7(7
5.实验结果及总结
1) 系统仿真情况
输入值 A=0AH、B=0CH,结果 DOUT=0078H;
输入值 A=0CH、B=0AH,结果 DOUT=0078H;
输入值 A=02H、B=03H,结果 DOUT=0006H;
仿真图如下：
2) 仿真分析
当 START 输入信号为“1”，REG16B 清零和被乘数 A[7..0]
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