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Decawave UWB 用户手册 超宽带.pdf
List of Figures
List of Tables
1 Introduction
1.1 About the DW1000
1.2 About this document
2 Overview of the DW1000
2.1 Introduction
2.2 Interfacing to the DW1000
2.2.1 The SPI Interface
2.2.1.1 SPI operating modes
2.2.1.2 Transaction formats of the SPI interface
2.2.1.2.1 SPI transaction with a 2-octet header
2.2.1.2.2 SPI transaction with a 3-octet header
2.2.2 Interrupts
2.2.3 General Purpose I/O
2.2.4 The SYNC pin
2.3 DW1000 Operational States
2.3.1 State diagram
2.3.2 Overview of main operational states
2.4 Power On Reset (POR)
2.4.1 SLEEP and DEEPSLEEP
2.4.1.1 Waking from sleep
2.4.1.2 Configuration register preservation
2.4.1.3 Automatically loading LDO calibration data from the OTP
2.4.2 Specific state sequences supported by the DW1000
2.5 Default Configuration on Power Up
2.5.1 Default System Configuration
2.5.2 Default Channel Configuration
2.5.3 Default Transmitter Configuration
2.5.4 Default Receiver Configuration
2.5.5 Default Configurations that should be modified
2.5.5.1 AGC_TUNE1
2.5.5.2 AGC_TUNE2
2.5.5.3 DRX_TUNE2
2.5.5.4 NTM
2.5.5.5 LDE_CFG2
2.5.5.6 TX_POWER
2.5.5.7 RF_TXCTRL
2.5.5.8 TC_PGDELAY
2.5.5.9 FS_PLLTUNE
2.5.5.10 LDELOAD
2.5.5.11 LDOTUNE
3 Message Transmission
3.1 Basic Transmission
3.2 Transmission timestamp
3.3 Delayed Transmission
3.4 Extended Length Data Frames
3.5 High Speed Transmission
3.5.1 TX buffer offset index
3.5.2 TX buffer write while sending or receiving
4 Message Reception
4.1 Basic Reception
4.1.1 Preamble Detection
4.1.2 Preamble Accumulation
4.1.3 SFD Detection
4.1.4 PHR Demodulation
4.1.5 Data Demodulation
4.1.6 RX Message timestamp
4.2 Delayed Receive
4.3 Double Receive Buffer
4.3.1 Enabling double-buffered operation
4.3.2 Controlling which buffer is being accessed
4.3.3 Operation of double buffering
4.3.4 TRXOFF when using Double Buffering
4.3.5 Overrun
4.4 Low-Power Listening
Figure 16: Low power listening with two sleep times
Figure 17: Power profile for low power listening mode where no frame is received
4.4.1 Configuring low-power listening
4.5 Low-Power SNIFF mode
4.5.1 SNIFF mode
Figure 19: Power profile for SNIFF where a frame is not received
Figure 20: Power profile for SNIFF where a frame is received
4.5.2 Low duty-cycle SNIFF mode
4.6 Diagnostics
4.7 Assessing the quality of reception and the RX timestamp
4.7.1 Estimating the signal power in the first path
4.7.2 Estimating the receive signal power
5 Media Access Control (MAC) hardware features
5.1 Cyclic redundancy check
5.2 Frame filtering
5.2.1 Frame Filtering Rules
5.2.2 Frame Filtering Notes
5.3 Automatic Acknowledgement
5.3.1 Preamble length & SFD in Automatic Acknowledge Frame
5.3.1.1 Preamble length
5.3.1.2 SFD Initialisation
5.3.2 Automatic Receiver Re-Enable
5.3.3 Automatic ACK Turnaround Time
5.3.4 Frame Pending bit
5.3.5 Host Notification
5.4 Transmit and automatically wait for response
6 Other features of the DW1000
6.1 External Synchronisation
6.1.1 One Shot Timebase Reset (OSTR) Mode
6.1.2 One Shot Transmit Synchronisation (OSTS) Mode
6.1.3 One Shot Receive Synchronisation (OSRS) Mode
6.2 External Power Amplification
6.3 Using the on-chip OTP memory
6.3.1 OTP memory map
6.3.2 Programming a value into OTP memory
6.3.3 Reading a value from OTP memory
6.4 Measuring IC temperature and voltage
7 The DW1000 register set
7.1 Register map overview
7.2 Detailed register description
7.2.1 Terminology
7.2.2 Register file: 0x00 – Device Identifier
7.2.3 Register file: 0x01 – Extended Unique Identifier
7.2.4 Register file: 0x02 – Reserved
7.2.5 Register file: 0x03 – PAN Identifier and Short Address
7.2.6 Register file: 0x04 – System Configuration
7.2.7 Register file: 0x05 – Reserved
7.2.8 Register file: 0x06 – System Time Counter
7.2.9 Register file: 0x07 – Reserved
7.2.10 Register file: 0x08 – Transmit Frame Control
7.2.11 Register file: 0x09 – Transmit Data Buffer
7.2.12 Register file: 0x0A – Delayed Send or Receive Time
7.2.13 Register file: 0x0B – Reserved
7.2.14 Register file: 0x0C – Receive Frame Wait Timeout Period
7.2.15 Register file: 0x0D – System Control Register
7.2.16 Register file: 0x0E – System Event Mask Register
7.2.17 Register file: 0x0F – System Event Status Register
7.2.18 Register file: 0x10 – RX Frame Information Register
7.2.19 Register file: 0x11 – RX Frame Buffer
7.2.20 Register file: 0x12 – Rx Frame Quality Information
7.2.21 Register file: 0x13 – Receiver Time Tracking Interval
7.2.22 Register file: 0x14 – Receiver Time Tracking Offset
7.2.23 Register file: 0x15 – Receive Time Stamp
7.2.24 Register file: 0x16 – Reserved
7.2.25 Register file: 0x17 – Transmit Time Stamp
7.2.26 Register file: 0x18 – Transmitter Antenna Delay
7.2.27 Register file: 0x19 – Reserved
7.2.28 Register file: 0x1A – Acknowledgement time and response time
7.2.29 Register files: 0x1B and 0x1C – Reserved
7.2.30 Register file: 0x1D – SNIFF Mode
7.2.31 Register file: 0x1E – Transmit Power Control
7.2.31.1 Units of TX Power Control
7.2.31.2 Smart Transmit Power Control
7.2.31.3 Manual Transmit Power Control
7.2.31.4 Transmit Power Control Reference Values
7.2.32 Register file: 0x1F – Channel Control
7.2.33 Register file: 0x20 – Reserved
7.2.34 Register file: 0x21 – User defined SFD sequence
7.2.35 Register file: 0x22 – Reserved
7.2.36 Register file: 0x23 –AGC configuration and control
7.2.36.1 Sub-Register 0x23:00 – AGC_RES1
7.2.36.2 Sub-Register 0x23:02 – AGC_CTRL1
7.2.36.3 Sub-Register 0x23:04 – AGC_TUNE1
7.2.36.4 Sub-Register 0x23:06 – AGC_RES2
7.2.36.5 Sub-Register 0x23:0C – AGC_TUNE2
7.2.36.6 Sub-Register 0x23:14 – AGC_RES3
7.2.36.7 Sub-Register 0x23:12 – AGC_TUNE3
7.2.36.8 Sub-Register 0x23:14 – AGC_RES4
7.2.36.9 Sub-Register 0x23:1E – AGC_STAT1
7.2.37 Register file: 0x24 – External Synchronisation Control
7.2.37.1 Sub-Register 0x24:00 EC_CTRL
7.2.37.2 Sub-Register 0x24:04 EC_RXTC
7.2.37.3 Sub-Register 0x24:08 EC_GOLP
7.2.38 Register file: 0x25 – Accumulator CIR memory
7.2.39 Register file: 0x26 – GPIO control and status
7.2.39.1 Sub-Register 0x26:00 – GPIO_MODE
7.2.39.2 Sub-Register 0x26:04 – Reserved
7.2.39.3 Sub-Register 0x26:08 – GPIO_DIR
7.2.39.4 Sub-Register 0x26:0C – GPIO_DOUT
7.2.39.5 Sub-Register 0x26:10 – GPIO_IRQE
7.2.39.6 Sub-Register 0x26:14 – GPIO_ISEN
7.2.39.7 Sub-Register 0x26:18 – GPIO_IMODE
7.2.39.8 Sub-Register 0x26:1C – GPIO_IBES
7.2.39.9 Sub-Register 0x26:20 – GPIO_ICLR
7.2.39.10 Sub-Register 0x26:24 – GPIO_IDBE
7.2.39.11 Sub-Register 0x26:28 – GPIO_RAW
7.2.40 Register file: 0x27 – Digital receiver configuration
7.2.40.1 Sub-Register 0x27:00 – DRX_RES1
7.2.40.2 Sub-Register 0x27:02 – DRX_TUNE0b
7.2.40.3 Sub-Register 0x27:04 – DRX_TUNE1a
7.2.40.4 Sub-Register 0x27:06 – DRX_TUNE1b
7.2.40.5 Sub-Register 0x27:08 – DRX_TUNE2
7.2.40.6 Sub-Register 0x27:0C – DRX_RES2
7.2.40.7 Sub-Register 0x27:20 – DRX_SFDTOC
7.2.40.8 Sub-Register 0x27:22 – DRX_RES3
7.2.40.9 Sub-Register 0x27:24 – DRX_PRETOC
7.2.40.10 Sub-Register 0x27:26 – DRX_TUNE4H
7.2.40.11 Sub-Register 0x27:2C – RXPACC_NOSAT
7.2.41 Register file: 0x28 – Analog RF configuration block
7.2.41.1 Sub-Register 0x28:00 – RF_CONF
7.2.41.2 Sub-Register 0x28:04 – RF_RES1
7.2.41.3 Sub-Register 0x28:0B– RF_RXCTRLH
7.2.41.4 Sub-Register 0x28:0C– RF_TXCTRL
7.2.41.5 Sub-Register 0x28:10 – RF_RES2
7.2.41.6 Sub-Register 0x28:2C – RF_STATUS
7.2.41.7 Sub-Register 0x28:30 – LDOTUNE
7.2.42 Register file: 0x29 – Reserved
7.2.43 Register file: 0x2A – Transmitter Calibration block
7.2.43.1 Sub-Register 0x2A:00 – TC_SARC
7.2.43.2 Sub-Register 0x2A:03 – TC_SARL
7.2.43.3 Sub-Register 0x2A:06 – TC_SARW
7.2.43.4 Sub-Register 0x2A:0B – TC_PGDELAY
7.2.43.5 Sub-Register 0x2A:0C – TC_PGTEST
7.2.44 Register file: 0x2B – Frequency synthesiser control block
7.2.44.1 Sub-Register 0x2B:00 – FS_RES1
7.2.44.2 Sub-Register 0x2B:07 – FS_PLLCFG
7.2.44.3 Sub-Register 0x2B:0B – FS_PLLTUNE
7.2.44.4 Sub-Register 0x2B:0C – FS_RES2
7.2.44.5 Sub-Register 0x2B:0E – FS_XTALT
7.2.44.6 Sub-Register 0x2B:0F – FS_RES3
7.2.45 Register file: 0x2C – Always-on system control interface
7.2.45.1 Sub-Register 0x2C:00 – AON_WCFG
7.2.45.2 Sub-Register 0x2C:02 – AON_CTRL
7.2.45.3 Sub-Register 0x2C:03 – AON_RDAT
7.2.45.4 Reading from a specified address within AON memory
7.2.45.5 Sub-Register 0x2C:04 – AON_ADDR
7.2.45.6 Sub-Register 0x2C:05 – AON_RES1
7.2.45.7 Sub-Register 0x2C:06 – AON_CFG0
7.2.45.8 Sub-Register 0x2C:0A – AON_CFG1
7.2.46 Register file: 0x2D – OTP Memory Interface
7.2.46.1 Sub-Register 0x2D:00 – OTP_WDAT
7.2.46.2 Sub-Register 0x2D:04 – OTP_ADDR
7.2.46.3 Sub-Register 0x2D:06 – OTP_CTRL
7.2.46.4 Sub-Register 0x2D:08 – OTP_STAT
7.2.46.5 Sub-Register 0x2D:0A – OTP_RDAT
7.2.46.6 Sub-Register 0x2D:0E – OTP_SRDAT
7.2.46.7 Sub-Register 0x2D:12 – OTP_SF
7.2.46.8 Receiver operating parameter sets
7.2.47 Register file: 0x2E – Leading Edge Detection Interface
7.2.47.1 Sub-Register 0x2E:0000 – LDE_THRESH
7.2.47.2 Sub-Register 0x2E:0806 – LDE_CFG1
7.2.47.3 Sub-Register 0x2E:1000 – LDE_PPINDX
7.2.47.4 Sub-Register 0x2E:1002 – LDE_PPAMPL
7.2.47.5 Sub-Register 0x2E:1804 – LDE_RXANTD
7.2.47.6 Sub-Register 0x2E:1806– LDE_CFG2
7.2.47.7 Sub-Register 0x2E:2804 – LDE_REPC
7.2.48 Register file: 0x2F – Digital Diagnostics Interface
7.2.48.1 Sub-Register 0x2F:00 – Event Counter Control
7.2.48.2 Sub-Register 0x2F:04 – PHR Error Counter
7.2.48.3 Sub-Register 0x2F:06 – RSD Error Counter
7.2.48.4 Sub-Register 0x2F:08 – FCS Good Counter
7.2.48.5 Sub-Register 0x2F:0A – FCS Error Counter
7.2.48.6 Sub-Register 0x2F:0C – Frame Filter Rejection Counter
7.2.48.7 Sub-Register 0x2F:0E – RX Overrun Error Counter
7.2.48.8 Sub-Register 0x2F:10 – SFD Timeout Error Counter
7.2.48.9 Sub-Register 0x2F:12 – Preamble Detection Timeout Event Counter
7.2.48.10 Sub-Register 0x2F:14 – RX Frame Wait Timeout Event Counter
7.2.48.11 Sub-Register 0x2F:16 – TX Frame Sent Counter
7.2.48.12 Sub-Register 0x2F:18 – Half Period Warning Counter
7.2.48.13 Sub-Register 0x2F:1A – Transmitter Power-Up Warning Counter
7.2.48.14 Sub-Register 0x2F:1C – EVC_RES1
7.2.48.15 Sub-Register 0x2F:24 – Digital Diagnostics Test Mode Control
7.2.49 Register files: 0x30 to 0x35 – Reserved
7.2.50 Register file: 0x36 – Power Management and System Control
7.2.50.1 Sub-Register 0x36:00 – PMSC_CTRL0
7.2.50.2 Sub-Register 0x36:04 – PMSC_CTRL1
7.2.50.3 Sub-Register 0x36:08 – PMSC_RES1
7.2.50.4 Sub-Register 0x36:0C – PMSC_SNOZT
7.2.50.5 Sub-Register 0x36:10 – PMSC_RES2
7.2.50.6 Sub-Register 0x36:26 – PMSC_TXFSEQ
7.2.50.7 Sub-Register 0x36:28 – PMSC_LEDC
7.2.51 Register files: 0x37 to 0x3F – Reserved
8 DW1000 Calibration
8.1 IC Calibration – Crystal Oscillator Trim
8.1.1 Calibration Method
8.2 IC Calibration – Transmit power and spectrum
8.2.1 Calibration Method
8.2.1.1 Calibration – Manual TX Power Control
8.2.1.2 Calibration – Smart TX Power Control
8.2.2 Other TX adjustments to consider
8.3 IC Calibration – Antenna Delay
8.3.1 Calibration Method
9 Operational design choices when employing the DW1000
9.1 Operating range
9.2 Channel and Bandwidth selection
9.3 Choice of data rate, preamble length and PRF
9.4 Power consumption
9.5 Node density and air utilisation
9.6 Low–duty cycle – air time
9.7 Location schemes
9.8 General considerations
10 APPENDIX 1: The IEEE 802.15.4 UWB physical layer
10.1 Frame structure overview
10.2 Data modulation scheme
10.3 Synchronisation header modulation scheme
10.4 PHY header
10.5 UWB channels and preamble codes
10.6 Additional details on the standard
11 APPENDIX 2: The IEEE 802.15.4 MAC layer
11.1 General MAC message format
11.2 The frame control field in the MAC header
11.2.1 Frame type field
11.2.2 Security enabled Field
11.2.3 Frame pending field
11.2.4 Acknowledgement request field
11.2.5 PAN ID compression field
11.2.6 Destination addressing mode field
11.2.7 Frame version field
11.2.8 Source addressing mode field
11.3 The Sequence Number field
11.4 MAC level processing in the DW1000
12 APPENDIX 3: Two-Way Ranging
12.1 Introduction
12.2 Single-sided Two-way Ranging
12.3 Double-sided Two-way Ranging
12.3.1 Using 4 messages
12.3.2 Using three messages
12.3.3 Using symmetric reply times
12.3.4 Comparison between DS and SDS two-way ranging
12.3.4.1 Introduction
12.3.4.2 Infrastructure based asset tracking
12.3.4.3 Infrastructure based asset tracking
12.3.4.4 Infrastructure-less Peer-to-peer networks
13 APPENDIX 4: Abbreviations and acronyms
14 APPENDIX 5: References
[1] IEEE 802.15.4-2011 or “IEEE Std 802.15.4™‐2011” (Revision of IEEE Std 802.15.4-2006). IEEE Standard for Local and metropolitan area networks – Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs). IEEE Computer Society Sponsored by the...
15 Document History
16 Change Log
17 About Decawave
DW1000 USER MANUAL
DW1000 USER MANUAL
HOW TO USE, CONFIGURE AND
PROGRAM THE DW1000 UWB
TRANSCEIVER
This document is subject to change without notice
© Decawave Ltd 2016
Version 2.09
Page 1 of 228
DW1000 User Manual
Table of Contents
LIST OF FIGURES ........................................................ 3
LIST OF TABLES .......................................................... 4
1
INTRODUCTION ................................................. 7
1.1
1.2
ABOUT THE DW1000 ...................................... 7
ABOUT THIS DOCUMENT .................................... 7
OVERVIEW OF THE DW1000 ............................. 10
2
2.1
2.2
2.3
2.4
2.5
INTRODUCTION .............................................. 10
INTERFACING TO THE DW1000 ........................ 10
DW1000 OPERATIONAL STATES ...................... 14
POWER ON RESET (POR) ................................ 18
DEFAULT CONFIGURATION ON POWER UP .......... 20
3 MESSAGE TRANSMISSION ................................ 25
3.1
3.2
3.3
3.4
3.5
BASIC TRANSMISSION ...................................... 25
TRANSMISSION TIMESTAMP .............................. 26
DELAYED TRANSMISSION ................................. 26
EXTENDED LENGTH DATA FRAMES ..................... 27
HIGH SPEED TRANSMISSION ............................. 29
4 MESSAGE RECEPTION ....................................... 32
BASIC RECEPTION ........................................... 32
DELAYED RECEIVE ........................................... 35
DOUBLE RECEIVE BUFFER................................. 35
LOW-POWER LISTENING .................................. 39
LOW-POWER SNIFF MODE .............................. 41
DIAGNOSTICS ................................................ 44
ASSESSING THE QUALITY OF RECEPTION AND THE RX
4.1
4.2
4.3
4.4
4.5
4.6
4.7
TIMESTAMP ................................................................ 44
5 MEDIA ACCESS CONTROL (MAC) HARDWARE
FEATURES ................................................................. 48
5.1
5.2
5.3
5.4
CYCLIC REDUNDANCY CHECK ............................. 48
FRAME FILTERING ........................................... 48
AUTOMATIC ACKNOWLEDGEMENT .................... 50
TRANSMIT AND AUTOMATICALLY WAIT FOR RESPONSE
53
6
OTHER FEATURES OF THE DW1000 ................... 54
6.1
6.2
6.3
6.4
EXTERNAL SYNCHRONISATION ........................... 54
EXTERNAL POWER AMPLIFICATION .................... 57
USING THE ON-CHIP OTP MEMORY ................... 57
MEASURING IC TEMPERATURE AND VOLTAGE ...... 61
THE DW1000 REGISTER SET .............................. 62
7.1
7.2
REGISTER MAP OVERVIEW ................................ 62
DETAILED REGISTER DESCRIPTION ...................... 64
DW1000 CALIBRATION ................................... 189
7
8
8.1
8.2
8.3
IC CALIBRATION – CRYSTAL OSCILLATOR TRIM ... 189
IC CALIBRATION – TRANSMIT POWER AND SPECTRUM
191
IC CALIBRATION – ANTENNA DELAY ................. 194
OPERATIONAL DESIGN CHOICES WHEN
9
EMPLOYING THE DW1000....................................... 197
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
OPERATING RANGE ....................................... 197
CHANNEL AND BANDWIDTH SELECTION ............. 197
CHOICE OF DATA RATE, PREAMBLE LENGTH AND PRF
197
POWER CONSUMPTION .................................. 198
NODE DENSITY AND AIR UTILISATION ................ 198
LOW–DUTY CYCLE – AIR TIME .......................... 199
LOCATION SCHEMES ...................................... 200
GENERAL CONSIDERATIONS............................. 201
10 APPENDIX 1: THE IEEE 802.15.4 UWB PHYSICAL
LAYER ..................................................................... 203
FRAME STRUCTURE OVERVIEW ........................ 203
10.1
DATA MODULATION SCHEME .......................... 203
10.2
10.3
SYNCHRONISATION HEADER MODULATION SCHEME
204
PHY HEADER ............................................... 205
10.4
10.5 UWB CHANNELS AND PREAMBLE CODES ........... 206
10.6
ADDITIONAL DETAILS ON THE STANDARD ........... 207
11 APPENDIX 2: THE IEEE 802.15.4 MAC LAYER ... 208
GENERAL MAC MESSAGE FORMAT .................. 208
11.1
THE FRAME CONTROL FIELD IN THE MAC HEADER 209
11.2
11.3
THE SEQUENCE NUMBER FIELD ....................... 211
11.4 MAC LEVEL PROCESSING IN THE DW1000........ 212
12 APPENDIX 3: TWO-WAY RANGING ................. 213
12.1
12.2
12.3
INTRODUCTION ............................................ 213
SINGLE-SIDED TWO-WAY RANGING .................. 213
DOUBLE-SIDED TWO-WAY RANGING ................ 215
13 APPENDIX 4: ABBREVIATIONS AND ACRONYMS
220
14 APPENDIX 5: REFERENCES .............................. 224
15 DOCUMENT HISTORY ..................................... 224
16 CHANGE LOG .................................................. 224
17 ABOUT DECAWAVE ........................................ 228
© Decawave Ltd 2016
Version 2.09
Page 2 of 228
DW1000 User Manual
List of Figures
FIGURE 1: SPI READ AND WRITE TRANSACTIONS ................... 11
FIGURE 2: SINGLE OCTET HEADER OF THE NON-INDEXED SPI
TRANSACTION ......................................................... 12
FIGURE 3: EXAMPLE NON-INDEXED READ OF THE DEVICE ID
REGISTER (0X00) .................................................... 12
FIGURE 4: TWO OCTET HEADER OF THE SHORT INDEXED SPI
TRANSACTION ......................................................... 12
FIGURE 5: EXAMPLE SHORT-INDEXED READ OF 3RD AND 4TH OCTETS
OF REGISTER 0X00 .................................................. 13
FIGURE 6: THREE OCTET HEADER OF THE LONG INDEXED SPI
TRANSACTION ......................................................... 13
FIGURE 7: EXAMPLE LONG-INDEXED WRITE OF ONE OCTET TO
INDEX 310 OF THE TX BUFFER ................................... 13
FIGURE 8: DW1000 STATE DIAGRAM ................................ 15
FIGURE 9: TIMING DIAGRAM AND POWER PROFILE FOR COLD
START POR ............................................................ 18
FIGURE 10: TRANSMIT FRAME FORMAT ............................... 25
FIGURE 11: BASIC TRANSMIT SEQUENCE ............................. 25
FIGURE 12 : PHR ENCODING EXTENDED LENGTH DATA FRAMES
........................................................................... 28
FIGURE 13: BASIC RECEIVE SEQUENCE .................................. 32
FIGURE 14: FLOW CHART FOR USING DOUBLE RX BUFFERING ... 38
FIGURE 15 : TRXOFF IN DOUBLE-BUFFERED MODE ............. 39
FIGURE 16: LOW POWER LISTENING WITH TWO SLEEP TIMES ... 40
FIGURE 17: POWER PROFILE FOR LOW POWER LISTENING MODE
WHERE NO FRAME IS RECEIVED ................................... 41
FIGURE 18: STATE TRANSITIONS DURING SNIFF MODE ........... 42
FIGURE 19: POWER PROFILE FOR SNIFF WHERE A FRAME IS NOT
RECEIVED ............................................................... 43
FIGURE 20: POWER PROFILE FOR SNIFF WHERE A FRAME IS
RECEIVED ............................................................... 43
FIGURE 21: POWER PROFILE FOR LOW DUTY-CYCLE SNIFF WHERE
A FRAME IS NOT RECEIVED ......................................... 44
FIGURE 22: ESTIMATED RX LEVEL VERSUS ACTUAL RX LEVEL .... 47
FIGURE 23: DW1000 EXTERNAL SYNCHRONISATION INTERFACE
............................................................................ 54
FIGURE 24: SYNCHRONISED TRANSMISSION .......................... 56
FIGURE 25: OSRS MODE RECEIVE TIMEBASE SYNCHRONISATION
............................................................................ 56
FIGURE 26: TRANSMIT POWER CONTROL OCTET .................. 106
FIGURE 27: COMBINING EDG1 AND EDV2 TO GIVE AN ED NOISE
FIGURE ................................................................ 120
FIGURE 28: FLOW CHART FOR DIRECT READ OF AON ADDRESS 158
FIGURE 29: PPM VS CRYSTAL TRIM SETTING, VBATT= 3.3 V . 191
FIGURE 30: TRANSMIT AND RECEIVE ANTENNA DELAY ......... 195
FIGURE 31: UWB PHY FRAME STRUCTURE ....................... 203
FIGURE 32:- BPM/BPSK DATA AND PHR MODULATION ...... 203
FIGURE 33: PHR BIT ASSIGNMENT .................................... 206
FIGURE 34: GENERAL MAC MESSAGE FORMAT ................... 208
FIGURE 35: MAC MESSAGE FRAME CONTROL FIELD .............. 209
FIGURE 36: SINGLE-SIDED TWO-WAY RANGING ................... 213
FIGURE 37: DOUBLE-SIDED TWO-WAY RANGING WITH FOUR
MESSAGES ............................................................ 215
FIGURE 38: DOUBLE-SIDED TWO-WAY RANGING WITH THREE
MESSAGES ............................................................ 215
FIGURE 39: RANGING TO 3 ANCHORS WITH JUST 5 MESSAGES
WHERE EACH ANCHOR CALCULATES ITS OWN RANGE RESULT
.......................................................................... 218
© Decawave Ltd 2016
Version 2.09
Page 3 of 228
DW1000 User Manual
List of Tables
TABLE 1: MAIN DW1000 OPERATIONAL STATES / MODES ...... 16
TABLE 2: MODE 2 EXCERPT FROM DW1000 DATA SHEET
OPERATIONAL MODES TABLE .................................... 20
TABLE 3: GPIO DEFAULT FUNCTIONS .................................. 21
TABLE 4: REGISTER ACCESSES REQUIRED TO LOAD LDE MICROCODE
........................................................................... 24
TABLE 5: PREAMBLE DURATION FIELD VALUES IN EXTENDED
LENGTH DATA FRAME PHR ...................................... 28
TABLE 6: RECOMMENDED PAC SIZE .................................... 32
TABLE 7: REGISTERS IN THE RX DOUBLE-BUFFERED SWINGING-SET
........................................................................... 36
TABLE 8: AUTO-ACK PREAMBLE LENGTH DEPENDING ON RXPSR
TABLE 28: REGISTER FILE: 0X27 – DIGITAL RECEIVER
CONFIGURATION OVERVIEW ..................................... 136
TABLE 29: SUB-REGISTER 0X27:02 – DRX_TUNE0B VALUES137
TABLE 30: SUB-REGISTER 0X27:04 – DRX_TUNE1AVALUES 138
TABLE 31: SUB-REGISTER 0X27:06 – DRX_TUNE1B VALUES138
TABLE 32: SUB-REGISTER 0X27:08 – DRX_TUNE2VALUES . 139
TABLE 33: REGISTER 0X27:26 DRX_TUNE4H VALUES ........ 141
TABLE 34: REGISTER FILE: 0X28 – ANALOG RF CONFIGURATION
BLOCK OVERVIEW .................................................. 142
TABLE 35: SUB-REGISTER 0X28:0B– RF_RXCTRLH VALUES 144
TABLE 36: SUB-REGISTER 0X28:0C– RF_TXCTRL VALUES ... 144
TABLE 37: REGISTER FILE: 0X2A – TRANSMITTER CALIBRATION
AND RXPACC ........................................................ 51
BLOCK OVERVIEW .................................................. 147
TABLE 9: AUTO-ACK PREAMBLE LENGTH SELECTION IN EXTENDED
TABLE 38: SUB-REGISTER 0X2A:0B – TC_PGDELAY
LENGTH FRAMES MODE ............................................ 51
TABLE 10: OTP MEMORY MAP ........................................... 58
TABLE 11: OTP_SRDAT REGISTER .................................... 59
TABLE 12: REGISTER ACCESSES REQUIRED TO PROGRAM THE OTP
........................................................................... 59
TABLE 13: AN EXAMPLE OF REGISTER ACCESSES REQUIRED TO
READ FROM OTP .................................................... 60
TABLE 14: AN EXAMPLE OF REGISTER ACCESSES TO PERFORM A
READ OF THE TEMPERATURE AND VOLTAGE SENSORS ...... 61
TABLE 15: REGISTER MAP OVERVIEW ................................... 62
TABLE 16: PREAMBLE LENGTH SELECTION ............................. 75
TABLE 17: PREAMBLE LENGTH REPORTING ............................ 93
TABLE 18: RXPACC ADJUSTMENTS BY SFD CODE................. 96
TABLE 19: REFERENCE VALUES FOR REGISTER FILE: 0X1E –
TRANSMIT POWER CONTROL, FOR SMART TRANSMIT
POWER CONTROL ................................................. 110
TABLE 20: REFERENCE VALUES REGISTER FILE: 0X1E – TRANSMIT
POWER CONTROL FOR MANUAL TRANSMIT POWER
CONTROL (SMART TRANSMIT POWER CONTROL DISABLED)
......................................................................... 110
TABLE 21: RECOMMENDED SFD SEQUENCE CONFIGURATIONS FOR
BEST PERFORMANCE .............................................. 115
RECOMMENDED VALUES ......................................... 150
TABLE 39: .................................................................... 150
TABLE 40: REGISTER FILE: 0X2B – FREQUENCY SYNTHESISER
CONTROL BLOCK OVERVIEW ..................................... 151
TABLE 41: SUB-REGISTER 0X2B:07 – FS_PLLCFG VALUES ... 151
TABLE 42: SUB-REGISTER 0X2B:0B – FS_PLLTUNE VALUES 152
TABLE 43: REGISTER FILE: 0X2C – ALWAYS-ON SYSTEM CONTROL
OVERVIEW............................................................ 154
TABLE 44: CONFIGURATIONS MAINTAINED IN THE AON MEMORY
ARRAY................................................................. 157
TABLE 45: REGISTER FILE: 0X2D – OTP MEMORY INTERFACE
OVERVIEW............................................................ 162
TABLE 46: RECEIVER OPERATING PARAMETER SETS ............... 167
TABLE 47: REGISTER FILE: 0X2E – LEADING EDGE DETECTION
INTERFACE OVERVIEW ............................................ 168
TABLE 48: SUB-REGISTER 0X2E:1806– LDE_CFG2VALUES . 170
TABLE 49: SUB-REGISTER 0X2E:2804 – LDE_REPC
CONFIGURATIONS FOR (850 KBPS & 6.8 MBPS).......... 171
TABLE 50: REGISTER FILE: 0X2F – DIGITAL DIAGNOSTICS
INTERFACE OVERVIEW ............................................ 172
TABLE 51: REGISTER FILE: 0X36 – POWER MANAGEMENT AND
SYSTEM CONTROL OVERVIEW .................................. 181
TABLE 22: REGISTER FILE: 0X23 –AGC CONFIGURATION AND
TABLE 52: REGISTER ACCESSES REQUIRED FOR TRANSMITTER
CONTROL OVERVIEW .............................................. 116
TABLE 23: SUB-REGISTER 0X23:04 – AGC_TUNE1 VALUES 118
TABLE 24: SUB-REGISTER 0X23:0C – AGC_TUNE2 VALUES 118
TABLE 25: SUB-REGISTER 0X23:12 – AGC_TUNE3 VALUES 119
TABLE 26: SCALING FACTOR FOR CHANNEL NOISE ENERGY
ESTIMATION ......................................................... 120
TABLE 27: REGISTER FILE: 0X26 – GPIO CONTROL AND STATUS
OVERVIEW ........................................................... 124
CONFIGURATION PROCEDURE ................................... 192
TABLE 53: RECOMMENDED RX POWER LEVEL FOR ANTENNA
CALIBRATION ........................................................ 195
TABLE 54: RECOMMENDED TX-RX SEPARATION FOR ANTENNA
CALIBRATION ........................................................ 195
TABLE 55: RECOMMENDED PREAMBLE LENGTHS .................. 198
TABLE 56: TRANSMISSIONS PER SECOND USING ALOHA ....... 199
TABLE 57: TECHNIQUES TO SAVE POWER IN RECEIVING .......... 201
© Decawave Ltd 2016
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DW1000 User Manual
TABLE 58: PREAMBLE PARAMETERS .................................. 205
TABLE 59: DW1000 SUPPORTED UWB CHANNELS AND
RECOMMENDED PREAMBLE CODES ............................ 206
TABLE 60: FRAME TYPE FIELD VALUES ................................ 209
TABLE 61: DESTINATION ADDRESSING MODE FIELD VALUES .... 211
TABLE 62: SOURCE ADDRESSING MODE FIELD VALUES ........... 211
TABLE 63: TYPICAL CLOCK INDUCED ERRORS IN SS-TWR TIME OF
FLIGHT ESTIMATION ............................................... 214
TABLE 64: TYPICAL CLOCK INDUCED ERROR IN SS-TWR TIME-OF-
FLIGHT ESTIMATION USING ACTUAL IEEE80.15.4-2011
UWB FRAME LENGTHS........................................... 214
TABLE 65: DOCUMENT HISTORY ....................................... 224
© Decawave Ltd 2016
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DW1000 User Manual
DOCUMENT INFORMATION
Disclaimer
Decawave reserves the right to change product specifications without notice. As far as possible changes to functionality and
specifications will be issued in product specific errata sheets or in new versions of this document. Customers are advised to check
with Decawave for the most recent updates on this product.
Copyright © 2016 Decawave Ltd
LIFE SUPPORT POLICY
Decawave products are not authorized for use in safety-critical applications (such as life support) where a failure of the Decawave
product would reasonably be expected to cause severe personal injury or death. Decawave customers using or selling Decawave
products in such a manner do so entirely at their own risk and agree to fully indemnify Decawave and its representatives against
any damages arising out of the use of Decawave products in such safety-critical applications.
Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent
permanent damage.
REGULATORY APPROVALS
The DW1000, as supplied from Decawave, has not been certified for use in any particular geographic region by the appropriate
regulatory body governing radio emissions in that region although it is capable of such certification depending on the region
and the manner in which it is used.
All products developed by the user incorporating the DW1000 must be approved by the relevant authority governing radio
emissions in any given jurisdiction prior to the marketing or sale of such products in that jurisdiction and user bears all
responsibility for obtaining such approval as needed from the appropriate authorities.
© Decawave Ltd 2016
Version 2.09
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DW1000 User Manual
1
Introduction
1.1 About the DW1000
The DW1000 is a fully integrated low power, single chip CMOS radio transceiver IC compliant with the
IEEE 802.15.4-2011 ultra-wideband (UWB) standard.
•
•
•
•
•
•
It facilitates proximity detection to an accuracy of +/- 10 cm using two-way ranging time-of-flight (TOF)
measurements.
It facilitates real time location of assets in to an accuracy of +/- 10 cm using either two-way ranging (TOF)
measurements or one-way time difference of arrival (TDOA) Time Difference of Arrival schemes
It spans 6 RF bands from 3.5 GHz to 6.5 GHz
It supports data rates of 110 kbps, 850 kbps and 6.8 Mbps
Its high data rates allow it to keep on-air time short and thereby save power and extend battery lifetimes
Its ability to deal with severe multipath environments makes it ideal for highly reflective RF
environments
1.2 About this document
This user manual describes the operation and programming of the DW1000 and discusses some of the
design choices to be considered when implementing systems using it.
Information already contained in the DW1000 data sheet is not reproduced here and it is intended that the
reader should use this user manual in conjunction with the DW1000 data sheet.
The document is divided into a number of sections each of which deals with a particular aspect of the
DW1000 as follows: -
Section
No
Section Name
Information covered
2
3
4
5
6
7
Overview of the DW1000
Gives an overview of the DW1000, describes how to interface
to the device and details its various operating modes
Message Transmission
Describes the functionality and use of the DW1000
transmitter
Message Reception
Describes the functionality and use of the DW1000 receiver
Media Access Control (MAC)
hardware features
Describes the MAC level functionality provided in hardware
by the DW1000.
Other features of the DW1000
Describes other features supported by the DW1000
The DW1000 register set
Describes DW1000 user-accessible register set in detail, lists
all user accessible bit fields in each register and their
respective functions.
© Decawave Ltd 2016
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DW1000 User Manual
Section
No
Section Name
Information covered
8
DW1000 Calibration
Describes the parameters of the DW1000 that require
calibration; the methodology that should be used in
calibrating them and how often they require calibration.
9
10
11
Operational design choices
when employing the DW1000
Discusses some of the issues to be considered and trade-offs
to be made when building systems based on the DW1000
APPENDIX 1: The IEEE 802.15.4
UWB physical layer
Provides background information on the UWB PHY layer of
the IEEE802.15.4 standard
APPENDIX 2: The IEEE 802.15.4
MAC layer
Provides background information on the MAC layer of the
IEEE802.15.4 standard
12
APPENDIX 3: Two-Way Ranging
Gives an introduction to the use of the DW1000 in two-way
ranging proximity systems
APPENDIX 4: Abbreviations and
acronyms
Provides a list and explanation of abbreviations and
acronyms used in the rest of the document
APPENDIX 5: References
Lists the documents referred to in this user manual
Document History
Gives the revision history of this document
Major changes
Gives the major changes at each revision of this document
13
14
15
16
Note: Decawave also provides DW1000 device driver software as source code. This source code includes a
set of API functions to initialise, configure and control the DW1000. It provides API functions for
transmission and reception, and for driving the functionalities of the IC. The DW1000 driver source code is
targeted for the ARM cortex M3 but is readily portable to other microprocessor systems. The code comes
with a number of demo/test applications, (including a two-way ranging application), to exercise the API and
the features of the DW1000.
Clock Periods and Frequencies
The chipping rate given by the IEEE 802.15.4-2011 standard [1] is 499.2 MHz. DW1000 system clocks are
referenced to this frequency. Where the system clock frequency is given as 125 MHz, this is an
approximation to the actual system clock frequency of 124.8 MHz. Similarly, where the system clock period
is given as 8 ns, this is an approximation to the actual period of 1/ (124.8×106) seconds.
The 1 GHz PLL clock, where referenced, is an approximation to its actual frequency of 998.4 MHz.
A 63.8976 GHz sampling clock is associated with ranging for the IEEE 802.15.4-2011 standard, where a 15.65
picosecond time period is referred to, it is an approximation to the period of this clock.
PRF
PRF values of 16 MHz and 64 MHz are given in this document. These are approximations to the PRF values
dictated by [1]. PRF mean values are slightly higher for SHR as opposed to the other portions of a frame.
© Decawave Ltd 2016
Version 2.09
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