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Low Power HDMI Transmitter Data Sheet — EP952(B)_DS V0.5 EP952(B) Data Sheet V0.5 Original Release Date: Sep. 27, 2010 p. 27, 2 p. 27, 2 Revised: Apr. 02, 2012 01010 Expl Exp Explore Explore reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Explore does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Explore products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Explore product could create a situation where personal injury or death may occur. Should Buyer purchase or use Explore products for any such unintended or unauthorized application, Buyer shall indemnify and hold Explore and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Explore was negligent regarding the design or manufacture of the part. Explore Microelectronics Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 1

Data Sheet — EP952(B)_DS V0.5 Revision History Version Number Revision Date Sep/27/2010 Author Ether Lai 0.0 0.1 0.3 0.4 0.5 Dec/01/2010 Ether Lai 0.2 Apr/11/2011 Ether Lai Mar/03/2011 Sep/14/2011 Ether Lai Kyle Kuo Nov/24/2011 Apr/02/2012 Description of Changes Initial Version Add the Pin Diagram of BGA-64 package; Add the detailed package outline dimension; Update BGA-64 package outline dimension; Add the Ordering Information for different type of chip configuration; Revise Package Footprint Diagram; Fix typo in Register Description; Add the Thermal Resistance; Add the Power Consumption Revised EXT_SWING Resistor Value to 820 Ohm Remove Device Part of K Serial Separate the User Guide to Data Sheet & User Guide; Fix the Typos; er Ger G ata Shee 20 Oh ata Shee820 Oh Kyle Kuo Ether Lai & U 2 Explore Microelectronics Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED

Data Sheet — EP952(B)_DS V0.5 Section 1 Introduction 1.1 Overview EP952(B) is a Low Power HDMI (High Definition Multimedia Interface) transmitter. The chip is compliant with HDMI Rev 1.4 and HDCP Rev 1.4 specifications. The chip converts input video data in RGB or YUV format and audio data in IIS or SPDIF format into HDMI differential signals. The chip supports 8-bit video upto 1080p in HDMI mode. The chip also supports 3D video. The chip supports highly flexible digital video input in a muxed 12-bits mode or non-muxed 24-bit mode input. In both modes, the chip supports single or dual edge clocking. 1.2 Features • HDMI Specification 1.4 Compliant • HDCP RDCP R MHz inHz i v 1.4 s v 1.4 HDMHDM d) audio pressed resse d) audio Audio C ACR (A ACR (A Audio C Integrated HDCP encryption engine which is compliant with HDCP Rev 1.4 specification for transmitting protected content Integrated on-chip HDCP Keys (Optional) • • Wide TMDS Clock Frequency Range: 25MHz - 165MHz in HDMI mode • • • • • • Support 8-bit video upto 1080p in HDMI mode Support 3D video Support IIS and SPDIF (LPCM or compressed) audio types Support auto-send for DVI, ADO, ACR (Audio Clock Regeneration) and General Control packets. t buffer t buffe Support 1 Generic Data Packet buffer Flexible digital video input: muxed 12-bit and non-muxed 24-bit mode in RGB or YUV, embedded sync or separate sync Support 1 port of SPDIF audio input (without the need for system clock) and 2 channels of IIS audio inputs Supports audio down sampling at 1/2, 1/3 or 1/4 sampling rate for both SPDIF and IIS Supports CCIR YUV422 format input d 12-bit t: mumuxexe d 12-bit udio in dio inpp • • • On-chip YUV422 to YUV444 conversion and YUV444 to YUV422 conversion • On-chip YUV to RGB and RGB to YUB conversion in ITU-R BT.601 and 709 color space • Register Programmable Single/Dual Edge Clocking Mode • • Programmable DE generation • • Supports x2, x4 and x8 Pixel Repetition Supports input De-Skewing IIC Slave Programming Interface DIF au DIF au io do wn samp dio dow wn samp R YUV42 CCIR CCIR R YUV4 V422 V422 • 3 Explore Microelectronics Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED

Data Sheet — EP952(B)_DS V0.5 • Supports Receiver Hot Plug Detection • Downward compatible with DVI 1.0 • • Supports Power Down Mode 3.3V and 1.8V power required 1.3 Ordering Information Two parts with different Package Type and HDCP Key Configuration are provided: Table 1-1 EP952 Ordering Information Device Part # EP952 EP952B HDCP Keys Write from External MCU Write from External MCU Package Type Pins 64 64 ernal M ernal M M LQFP-64 (7mm x 7mm) BGA-64 (5mm x 5mm) ExtErnarn 4 Explore Microelectronics Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED

Section 2 Overview 2.1 Block Diagram Data Sheet — EP952(B)_DS V0.5 Figure 2-1 Block Diagram PLL EXT_SWING i r e t t i m s n n a a a r r r T T T e n g n E P C D H H M I M M D D D H H H I I TX0+/TX0- TX1+/TX1- TX2+/TX2- TXC+/TXC- HDCP Keys SDA_PULL SCL_PULL IDCK DE HSYNC VSYNC D[23:0] Video Processing SPDIF IIS* Audio Processing Registers & Logics IIC Slave IIC Slav IC Slav EXT_RSTb MCU_SDA MCU_SCL Explore Microelectronics Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 5

Data Sheet — EP952(B)_DS V0.5 2.2 Pin Diagram 2.2.1 LQFP-64 I VDD D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DE HSYNC VSYNC VDD 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Figure 2-2 Pin Diagram (LQFP-64) D C K D 1 1 D 1 2 D 1 3 D 1 4 D 1 5 D 1 6 D 1 7 V S S V D D E D 1 8 D 1 9 D 2 0 D 2 1 D 2 2 D 2 3 4 8 4 7 4 4 3 5 4 1 4 0 3 9 3 8 4 6 4 5 3 7 3 6 4 3 4 2 3 4 3 3 31 30 3232 32 18 19 20 21 22 24 23 26 25 28 27 29 17 COMR AVSS TX2P TX2M AVDD TX1P TX1M AVSS TX0P TX0M AVDD TXCP TXCM AVSS/PVSS PVDD EXT_SWING 64 1 1 2 3 4 5 6 7 8 9 0 1 1 1 2 1 3 1 4 1 5 1 6 1 I F D P S D S _ S I I S W _ S I I K C S _ S I I d e v r e s e r L L U P _ A D S L L U P _ L C S H D V S R S S V E D D V A D S _ U C M L C S _ U C M T N I b T S R _ T X E C N G L P T H 6 Explore Microelectronics Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED

2.2.2 BGA-64 1 Figure 2-3 Pin Diagram (BGA64) 2 6 4 5 3 Data Sheet — EP952(B)_DS V0.5 7 8 D10 VDD IDCK VDDE D19 D23 COMR TX2P A B C D E F G H VS VDD SPDIF 7 77 6 66 8 88 D8 D6 D4 D2 D0 D9 D7 D5 D3 D1 HS DE D12 D13 IIS_SCK IIS_WS IIS_SD D11 VSS D18 D22 AVSS TX2M TX0P TX1P TX1M D20 D21 VSS NT INT D15 D17 D14 D16 RSTb AVSS AVDD AVDD DE VDDE RSVDH SCL_PULL TX AVSS TX1 AVD Tb A LLLL M ssc TOPTO TOP View 5 SDA_PULL nnnn scan_en SWING HTPLG MSDA PVDD MSCL AVSS 4 3 2 1 NC TX0M TXCP TXCM A B C D E F G H Bottom View Explore Microelectronics Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 7

Data Sheet — EP952(B)_DS V0.5 2.3 Pin Description Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open. Table 2-1 Input Control/Data/CLK Pins DESCRIPTION e it pi Top half of 24-bit pixel bus When BSEL = HIGH, this bus inputs the top half of the 24-bit pixel bus When BSEL = LOW, these bits are not used to input pixel data. In this mode, the state of D[23:16] is input to the IIC register CFG. This allow 8-bits of user configuration data to be read by the graphics controller through the IIC interface. D[15:12] are not used and should be tied to GND. Bottom half of 24-bit pixel bus / 12-bit pixel bus input When BSEL = HIGH, this bus inputs the bottom half of the 24-bit pixel bus When BSEL = LOW, this bus inputs 1/2 a pixel (12-bits) at every latch edge (both falling and/or rising) of the clock. Input Data Clock Data Enable Input. This signal is high when input pixel data is valid to the transmitter and low otherwise. It is critical that this signal have the same setup/hold timing as the data bus. Horizontal Sync Input. Vertical Sync Input. 24-b24 at every every data is v data is v nal hav nal hav t p Inpn Table 2-2 Audio Input Pins put pixe put pixe that this at thi DESCRIPTION DESDE tch edg tch ed ut Put P o Io port inp port inp Audud SPDIF audio port input putut nput for ut fo IIS SCK input for IIS audio port IIS WS input for IIS audio port WS input input IIS SD input for IIS audio port S SD inp SD inp for IIS aud or IIS aud ut for IIS a ut for IIS IS audio p IS audio Table 2-3 IIC Pins DESCRIPTION SCL signal for slave IIC port SDA signal for slave IIC port Pull-up this pin to 3V3 through 4.7K: resistor. Pull-up this pin to 3V3 through 4.7K: resistor. Connect this pin to 3.3V for normal operation. Table 2-4 Misc. Pins DESCRIPTION External Reset (Active LOW). A HIGH level indicates normal operation and a LOW level causes all the logic on the chip to be reset. NAME IN / OUT D23 - D12 IN D11 - D0 IDCK DE HSYNC VSYNC NAME SPDIF IIS_SCK IIS_WS IIS_SD IN IN IN IN IN IN / OUT IN IN IN IN NAME U_SCL OUTUT IN IN // IN / O OUT U_SDU_SD ININ IN I IO ULLLL OUT IO IN MCU_SCL U_SCL DAA MCU_SDA SCL_PULL SDA_PULL RSVDH NAME IN / OUT EXT_RSTb IN 8 Explore Microelectronics Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED

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