ddr3设计注意要点.pdf

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DDR3 Design Considerations for PCB Applications

Introduction

Overview of Presentation

DDR3 – Same players

Cross-over Point

DDR SDRAM Highlights and Comparison

DDR SDRAM Highlights and Comparison (cont.)

Typical Freescale DDR2/3 Controller Highlights

Typical Freescale DDR2/3 Controller Highlights (cont’d)

Memory Controller Block Diagram

Key DDR3 Memory Improvements and Additions

DDR3 Signaling – Example SSTL-1.5

Lower Power

Improved Pinout

Fly By Routing Topology

Fly By Routing Improved SI

Fly By Skew Across All receivers

The need for write-leveling….

Write-Leveling… How it works

Read Adjustment

Dynamic ODT – System Motivation

New DDR3 Pins

New DDR3 Pins… cont’d

NEW DDR3 pins – ZQ Calibration Pin

Freescale Controller Driver Calibration

DIMM Mirroring…

NEW DDR3 pins – TDQS/TDQS#

Layout Example – CTS8536

DDR3-800Mhz In the Lab

Pitfall 1 – Noisy VREF

Pitfall 1 – Measuring VREF

Pitfall 1 – Protecting VREF

Pitfall 2 – Wimpy VREF source

Pitfall 3 – Reference Plane discontinuities

Pitfall 4 – Data Tuning

Pitfall 5 – Forgetting Termination

Pitfall 6 – POR config selection

Pitfall 7 – Expandability

Pitfall 8 – Not using proven JEDEC topologies

Pitfall 9 – Separate VDDQ/VDDIO

Pitfall 10– Slew Rate De-rating (setup & hold)

Pitfall 11 – No debug or testability on BGA devices

DDR3 Initialization Flow

DDR2 Initialization Flow

Burst Length

Power-up : Power Rails

Power-up : Power Rails cont’d

Reset

Stable clocks

DRAMs Initialized

Mode Register Set 0

Mode Register Set 1

Mode Register Set 2

Driver Calibration

July 2009 DDR3 Design Considerations for PCB Applications AN111 Jon Burnett Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM

Introduction ►Customers are beginning to inquire and / or expect DDR3 support on their new product offerings, especially as the price cross-over point nears. ►The first device with DDR3 support was 8572. ►The first development system with DDR3 will be P2020. ►As such, more and more FSL products are supporting DDR3 moving forward. ►In this session we will look at key distinctions between DDR3 vs. DDR1 & DDR2, with key emphasis placed on elements that are important to hardware / board design engineers. Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 2 TM

Overview of Presentation ► DDR3 SDRAM Attributes. ► DDR Controller Highlights. ► DDR3 Signaling. ► DDR3 Routing Methodology. ► Memory Pins, New Features. ► PCB Design Pitfalls. Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 3 TM

DDR3 – Same players ► Supported by all major memory vendors Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 4 TM

Cross-over Point Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 5 TM

DDR SDRAM Highlights and Comparison Feature/Category Package Densities Voltage I/O Signaling DDR1 TSOP 128Mb -1Gb 2.5V Core 2.5V I/O SSTL_2 Internal Memory Banks 4 DDR2 DDR3 BGA only 256Mb - 4Gb 1.8V Core 1.8V I/O SSTL_18 4 to 8 BGA only 512Mb -8Gb 1.5V Core 1.5V I/O SSTL_15 8 Data Rate Termination 200-400 Mbps 400–800 Mbps 800–1600 Mbps Motherboard termination to VTT for all signals On-die termination for data group. VTT termination for address, command, and control On-die termination for data group. VTT termination for address, command, and control Data Strobes Single Ended Differential or single Differential Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 6 TM

DDR SDRAM Highlights and Comparison (cont.) Feature/Category DDR1 DDR2 DDR3 Burst Length CL/tRCD/tRP Master Reset ODT (On-die termination) Driver Calibration Write Leveling BL= 2, 4, 8 (2-bit prefetch) 15 ns each BL= 4, 8 (4-bit prefetch) 15 ns each BL= 8 (Burst chop 4) (8-bit prefetch) 12 ns each No No No No No Yes Yes Yes Off-Chip (OCD) On-Chip with ZQ pin (ZQ cal) No Yes Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 7 TM

Typical Freescale DDR2/3 Controller Highlights ►Interface speed • DDR2 - up to 800 MHz • DDR3 - up to 800 MHz today (MPC8572, MPC8526) Evaluating higher speeds 1066 MHz and up to 1600 MHz ►Support Interface width • 64/72-bit data bus – high end product • 32/40-bit data bus – low end products • 16/24-bit data bus – low end products ►Discrete, unbuffered, and registered DIMM support • Memory device densities from 64Mb – through 8Gb • Up to four chip selects supported • Support for x8/x16 DDR devices – x4 devices are not supported ►Full ECC (Error Correction Code) support • Single error correction/detection, double error detection • Error injection for software development ►Self refresh support Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 8 TM

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