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802.3bs_D3.5.pdf
Introduction
Contents
1. Introduction
1.1 Overview
1.1.3 Architectural perspectives
1.1.3.2 Compatibility interfaces
1.3 Normative references
1.4 Definitions
1.5 Abbreviations
4. Media Access Control
4.4 Specific implementations
4.4.2 MAC parameters
30. Management
30.2 Managed objects
30.2.5 Capabilities
30.3 Layer management for DTEs
30.3.2 PHY device managed object class
30.3.2.1 PHY device attributes
30.3.2.1.2 aPhyType
30.3.2.1.3 aPhyTypeList
30.3.2.1.5 aSymbolErrorDuringCarrier
30.5 Layer management for medium attachment units (MAUs)
30.5.1 MAU managed object class
30.5.1.1 MAU attributes
30.5.1.1.2 aMAUType
30.5.1.1.4 aMediaAvailable
30.5.1.1.12 aLaneMapping
30.5.1.1.15 aFECAbility
30.5.1.1.17 aFECCorrectedBlocks
30.5.1.1.18 aFECUncorrectableBlocks
30.5.1.1.32 aPCSFECIndicationAbility
30.5.1.1.33 aPCSFECIndicationEnable
45. Management Data Input/Output (MDIO) Interface
45.2 MDIO Interface Registers
45.2.1 PMA/PMD registers
45.2.1.1 PMA/PMD control 1 register (Register 1.0)
45.2.1.1.3 Speed selection (1.0.13, 1.0.6, 1.0.5:2)
45.2.1.1.4 PMA remote loopback (1.0.1)
45.2.1.1.5 PMA local loopback (1.0.0)
45.2.1.2 PMA/PMD status 1 register (Register 1.1)
45.2.1.2.3 Fault (1.1.7)
45.2.1.4 PMA/PMD speed ability (Register 1.4)
45.2.1.4.aaa 400G capable (1.4.15)
45.2.1.4.ac 200G capable (1.4.12)
45.2.1.6 PMA/PMD control 2 register (Register 1.7)
45.2.1.6.3 PMA/PMD type selection (1.7.65:0)
45.2.1.7 PMA/PMD status 2 register (Register 1.8)
45.2.1.7.4 Transmit fault (1.8.11)
45.2.1.7.5 Receive fault (1.8.10)
45.2.1.8 PMD transmit disable register (Register 1.9)
45.2.1.8.1 PMD transmit disable 914 (1.9.1015)
45.2.1.8.2 PMD transmit disable 4, 5, 6, 7, 8 through 13 (1.9.5, 1.9.6, 1.9.7, 1.9.8, 1.9.9 through 1.9.14)
45.2.1.9 PMD receive signal detect register (Register 1.10)
45.2.1.9.1 PMD receive signal detect 914 (1.10.1015)
45.2.1.9.2 PMD receive signal detect 4, 5, 6, 7, 8 through 13 (1.10.5, 1.10.6, 1.10.7, 1.10.8, 1.10.9 through 1.10.14)
45.2.1.10 PMA/PMD extended ability register (Register 1.11)
45.2.1.10.aab 200G/400G extended abilities (1.11.13)
45.2.1.14e 200G PMA/PMD extended ability register (Register 1.23)
45.2.1.14e.1 200G PMA remote loopback ability (1.23.15)
45.2.1.14e.2 200GBASE-LR4 ability (1.23.5)
45.2.1.14e.3 200GBASE-FR4 ability (1.23.4)
45.2.1.14e.4 200GBASE-DR4 ability (1.23.3)
45.2.1.14f 400G PMA/PMD extended ability register (Register 1.24)
45.2.1.14f.1 400G PMA remote loopback ability (1.24.15)
45.2.1.14f.2 400GBASE-LR8 ability (1.24.5)
45.2.1.14f.3 400GBASE-FR8 ability (1.24.4)
45.2.1.14f.4 400GBASE-DR4 ability (1.24.3)
45.2.1.14f.5 400GBASE-SR16 ability (1.24.2)
45.2.1.14g PMD transmit disable extension register (Register 1.27)
45.2.1.14g.1 PMD transmit disable 15 (1.27.0)
45.2.1.14h PMD receive signal detect extension register (Register 1.28)
45.2.1.14h.1 PMD receive signal detect 15 (1.28.0)
45.2.1.116a 200GAUI-8 and 400GAUI-16 chip-to-module recommended CTLE, lane 0 register (Register 1.400)
45.2.1.116a.1 Recommended CTLE peaking (1.400.4:1)
45.2.1.116b 200GAUI-8 and 400GAUI-16 chip-to-module recommended CTLE, lane 1 through lane 7 registers (Registers 1.401 through 1.407)
45.2.1.116c 400GAUI-16 chip-to-module recommended CTLE, lane 8 through lane 15 registers (Registers 1.408 through 1.415)
45.2.1.116d 200GAUI-n and 400GAUI-n chip-to-chip transmitter equalization, receive direction, lane 0 register (Register 1.500)
45.2.1.116d.1 Request flag (1.500.15)
45.2.1.116d.2 Post-cursor request (1.500.14:12)
45.2.1.116d.3 Pre-cursor request (1.500.11:10)
45.2.1.116d.4 Post-cursor remote setting (1.500.9:7)
45.2.1.116d.5 Pre-cursor remote setting (1.500.6:5)
45.2.1.116d.6 Post-cursor local setting (1.500.4:2)
45.2.1.116d.7 Pre-cursor local setting (1.500.1:0)
45.2.1.116e 200GAUI-n and 400GAUI-n chip-to-chip transmitter equalization, receive direction, lane 1 through lane 15 registers (Registers 1.501 through 1.515)
45.2.1.116f 200GAUI-n and 400GAUI-n chip-to-chip transmitter equalization, transmit direction, lane 0 register (Register 1.516)
45.2.1.116f.1 Request flag (1.516.15)
45.2.1.116f.2 Post-cursor request (1.516.14:12)
45.2.1.116f.3 Pre-cursor request (1.516.11:10)
45.2.1.116f.4 Post-cursor remote setting (1.516.9:7)
45.2.1.116f.5 Pre-cursor remote setting (1.516.6:5)
45.2.1.116f.6 Post-cursor local setting (1.516.4:2)
45.2.1.116f.7 Pre-cursor local setting (1.516.1:0)
45.2.1.116g 200GAUI-n and 400GAUI-n chip-to-chip transmitter equalization, transmit direction, lane 1 through lane 15 registers (Registers 1.517 through 1.531)
45.2.1.123 Test-pattern ability (Register 1.1500)
45.2.1.124 PRBS pattern testing control (Register 1.1501)
45.2.1.125 Square wave testing control (Register 1.1510)
45.2.1.125a PRBS13Q testing control (Register 1.1512)
45.2.1.126 PRBS Tx pattern testing error counter (Register 1.1600 through 1,1615, 1.1601, 1.1602, 1.1603, 1.1604, 1.1605, 1.1606, 1.1607, 1.1608, 1.1609)
45.2.1.127 PRBS Rx pattern testing error counter (Register 1.1700 through 1.1715, 1.1701, 1.1702, 1.1703, 1.1704, 1.1705, 1.1706, 1.1707, 1.1708, 1.1709)
45.2.3 PCS registers
45.2.3.1 PCS control 1 register (Register 3.0)
45.2.3.2 PCS status 1 register (Register 3.1)
45.2.3.2.7 PCS receive link status (3.1.2)
45.2.3.4 PCS speed ability (Register 3.4)
45.2.3.4.8 200G capable (3.4.8)
45.2.3.4.9 400G capable (3.4.9)
45.2.3.6 PCS control 2 register (Register 3.7)
45.2.3.6.1 PCS type selection (3.7.3:0)
45.2.3.7a PCS status 3 register (Register 3.9)
45.2.3.7a.1 400GBASE-R capable (3.9.1)
45.2.3.7a.2 200GBASE-R capable (3.9.0)
45.2.3.9a EEE control and capability 2 (Register 3.21)
45.2.3.9a.a 400GBASE-R EEE fast wake supported (3.21.5)
45.2.3.9a.b 200GBASE-R EEE fast wake supported (3.21.3)
45.2.3.13 BASE-R and MultiGBASE-T PCS status 1 register (Register 3.32)
45.2.3.13.1 BASE-R and MultiGBASE-T receive link status (3.32.12)
45.2.3.17 BASE-R PCS test-pattern control register (Register 3.42)
45.2.3.46 Lane 0 mapping register (Register 3.400)
45.2.3.47h PCS FEC symbol error counter lane 0 (Register 3.600, 3.601)
45.2.3.47i PCS FEC symbol error counter lane 1 through 15 (Registers 3.602 through 3.631)
45.2.3.47j PCS FEC control register (Register 3.800)
45.2.3.47j.1 PCS FEC degraded SER enable (3.800.2)
45.2.3.47j.2 PCS FEC bypass indication enable (3.800.1)
45.2.3.47k PCS FEC status register (Register 3.801)
45.2.3.47k.1 Local degraded SER received (3.801.6)
45.2.3.47k.2 Remote degraded SER received (3.801.5)
45.2.3.47k.3 PCS FEC degraded SER (3.801.4)
45.2.3.47k.4 PCS FEC degraded SER ability (3.801.3)
45.2.3.47k.5 PCS FEC high SER (3.801.2)
45.2.3.47k.6 PCS FEC bypass indication ability (3.801.1)
45.2.3.47l PCS FEC corrected codewords counter (Register 3.802, 3.803)
45.2.3.47m PCS FEC uncorrected codewords counter (Register 3.804, 3.805)
45.2.3.47n PCS FEC degraded SER activate threshold register (Register 3.806, 3.807)
45.2.3.47o PCS FEC degraded SER deactivate threshold register (Register 3.808, 3.809)
45.2.3.47p PCS FEC degraded SER interval register (Register 3.810, 3.811)
45.2.4 PHY XS registers
45.2.4.1 PHY XS control 1 register (Register 4.0)
45.2.4.4 PHY XS speed ability (Register 4.4)
45.2.4.4.a 400G capable (4.4.9)
45.2.4.4.b 200G capable (4.4.8)
45.2.4.11a BASE-R PHY XS status 1 register (Register 4.32)
45.2.4.11a.1 BASE-R PHY XS receive link status (4.32.12)
45.2.4.11b BASE-R PHY XS test-pattern control register (Register 4.42)
45.2.4.11b.1 Transmit test-pattern enable (4.42.3)
45.2.4.11c Multi-lane BASE-R PHY XS alignment status 1 register (Register 4.50)
45.2.4.11c.1 PHY XS lane alignment status (4.50.12)
45.2.4.11d Multi-lane BASE-R PHY XS alignment status 3 register (Register 4.52)
45.2.4.11d.1 Lane 7 aligned (4.52.7)
45.2.4.11d.2 Lane 6 aligned (4.52.6)
45.2.4.11d.3 Lane 5 aligned (4.52.5)
45.2.4.11d.4 Lane 4 aligned (4.52.4)
45.2.4.11d.5 Lane 3 aligned (4.52.3)
45.2.4.11d.6 Lane 2 aligned (4.52.2)
45.2.4.11d.7 Lane 1 aligned (4.52.1)
45.2.4.11d.8 Lane 0 aligned (4.52.0)
45.2.4.11e Multi-lane BASE-R PHY XS alignment status 4 register (Register 4.53)
45.2.4.11e.1 Lane 15 aligned (4.53.7)
45.2.4.11e.2 Lane 14 aligned (4.53.6)
45.2.4.11e.3 Lane 13 aligned (4.53.5)
45.2.4.11e.4 Lane 12 aligned (4.53.4)
45.2.4.11e.5 Lane 11 aligned (4.53.3)
45.2.4.11e.6 Lane 10 aligned (4.53.2)
45.2.4.11e.7 Lane 9 aligned (4.53.1)
45.2.4.11e.8 Lane 8 aligned (4.53.0)
45.2.4.11f PHY XS lane mapping, lane 0 register (Register 4.400)
45.2.4.11g PHY XS lane mapping, lane 1 through lane 15 registers (Registers 4.401 through 4.415)
45.2.4.11h PHY XS FEC symbol error counter lane 0 (Register 4.600, 4.601)
45.2.4.11i PHY XS FEC symbol error counter lane 1 through 15 (Registers 4.602 through 4.631)
45.2.4.11j PHY XS FEC control register (Register 4.800)
45.2.4.11j.1 PHY XS FEC degraded SER enable (4.800.2)
45.2.4.11j.2 PHY XS FEC bypass indication enable (4.800.1)
45.2.4.11k PHY XS FEC status register (Register 4.801)
45.2.4.11k.1 Remote degraded SER received (4.801.5)
45.2.4.11k.2 PHY XS FEC degraded SER (4.801.4)
45.2.4.11k.3 PHY XS FEC degraded SER ability (4.801.3)
45.2.4.11k.4 PHY XS FEC high SER (4.801.2)
45.2.4.11k.5 PHY XS FEC bypass indication ability (4.801.1)
45.2.4.11l PHY XS FEC corrected codewords counter (Register 4.802, 4.803)
45.2.4.11m PHY XS FEC uncorrected codewords counter (Register 4.804, 4.805)
45.2.4.11n PHY XS FEC degraded SER activate threshold register (Register 4.806, 4.807)
45.2.4.11o PHY XS FEC degraded SER deactivate threshold register (Register 4.808, 4.809)
45.2.4.11p PHY XS FEC degraded SER interval register (Register 4.810, 4.811)
45.2.5 DTE XS registers
45.2.5.1 DTE XS control 1 register (Register 5.0)
45.2.5.4 DTE XS speed ability (Register 5.4)
45.2.5.4.a 400G capable (5.4.9)
45.2.5.4.b 200G capable (5.4.8)
45.2.5.11a BASE-R DTE XS status 1 register (Register 5.32)
45.2.5.11a.1 BASE-R DTE XS receive link status (5.32.12)
45.2.5.11b BASE-R DTE XS test-pattern control register (Register 5.42)
45.2.5.11b.1 Transmit test-pattern enable (5.42.3)
45.2.5.11c Multi-lane BASE-R DTE XS alignment status 1 register (Register 5.50)
45.2.5.11c.1 DTE XS lane alignment status (5.50.12)
45.2.5.11d Multi-lane BASE-R DTE XS alignment status 3 register (Register 5.52)
45.2.5.11d.1 Lane 7 aligned (5.52.7)
45.2.5.11d.2 Lane 6 aligned (5.52.6)
45.2.5.11d.3 Lane 5 aligned (5.52.5)
45.2.5.11d.4 Lane 4 aligned (5.52.4)
45.2.5.11d.5 Lane 3 aligned (5.52.3)
45.2.5.11d.6 Lane 2 aligned (5.52.2)
45.2.5.11d.7 Lane 1 aligned (5.52.1)
45.2.5.11d.8 Lane 0 aligned (5.52.0)
45.2.5.11e Multi-lane BASE-R DTE XS alignment status 4 register (Register 5.53)
45.2.5.11e.1 Lane 15 aligned (5.53.7)
45.2.5.11e.2 Lane 14 aligned (5.53.6)
45.2.5.11e.3 Lane 13 aligned (5.53.5)
45.2.5.11e.4 Lane 12 aligned (5.53.4)
45.2.5.11e.5 Lane 11 aligned (5.53.3)
45.2.5.11e.6 Lane 10 aligned (5.53.2)
45.2.5.11e.7 Lane 9 aligned (5.53.1)
45.2.5.11e.8 Lane 8 aligned (5.53.0)
45.2.5.11f DTE XS lane mapping, lane 0 register (Register 5.400)
45.2.5.11g DTE XS lane mapping, lane 1 through lane 15 registers (Registers 5.401 through 5.415)
45.2.5.11h DTE XS FEC symbol error counter lane 0 (Register 5.600, 5.601)
45.2.5.11i DTE XS FEC symbol error counter lane 1 through 15 (Registers 5.602 through 5.631)
45.2.5.11j DTE XS FEC control register (Register 5.800)
45.2.5.11j.1 DTE XS FEC degraded SER enable (5.800.2)
45.2.5.11j.2 DTE XS FEC bypass indication enable (5.800.1)
45.2.5.11k DTE XS FEC status register (Register 5.801)
45.2.5.11k.1 Local degraded SER received (5.801.6)
45.2.5.11k.2 Remote degraded SER received (5.801.5)
45.2.5.11k.3 DTE XS FEC degraded SER (5.801.4)
45.2.5.11k.4 DTE XS FEC degraded SER ability (5.801.3)
45.2.5.11k.5 DTE XS FEC high SER (5.801.2)
45.2.5.11k.6 DTE XS FEC bypass indication ability (5.801.1)
45.2.5.11l DTE XS FEC corrected codewords counter (Register 5.802, 5.803)
45.2.5.11m DTE XS FEC uncorrected codewords counter (Register 5.804, 5.805)
45.2.5.11n DTE XS FEC degraded SER activate threshold register (Register 5.806, 5.807)
45.2.5.11o DTE XS FEC degraded SER deactivate threshold register (Register 5.808, 5.809)
45.2.5.11p DTE XS FEC degraded SER interval register (Register 5.810, 5.811)
78. Energy-Efficient Ethernet (EEE)
78.1 Overview
78.1.4 PHY types optionally supporting EEE
78.5 Communication link access latency
78.5.1 10 Gb/s PHY extension using extender sublayers XGXS
90. Ethernet support for time synchronization protocols
90.1 Introduction
116. Introduction to 200 Gb/s and 400 Gb/s networks
116.1 Overview
116.1.1 Scope
116.1.2 Relationship of 200 Gigabit and 400 Gigabit Ethernet to the ISO OSI reference model
116.1.3 Nomenclature
116.1.4 Physical Layer signaling systems
116.2 Summary of 200 Gigabit and 400 Gigabit Ethernet sublayers
116.2.1 Reconciliation Sublayer (RS) and Media Independent Interface
116.2.2 200GMII and 400GMII Extender Sublayers (200GXS and 400GXS)
116.2.3 Physical Coding Sublayer (PCS)
116.2.4 Physical Medium Attachment (PMA) sublayer
116.2.5 Physical Medium Dependent (PMD) sublayer
116.2.6 Management interface (MDIO/MDC)
116.2.7 Management
116.3 Service interface specification method and notation
116.3.1 Inter-sublayer service interface
116.3.2 Instances of the Inter-sublayer service interface
116.3.3 Semantics of inter-sublayer service interface primitives
116.3.3.1 IS_UNITDATA_i.request
116.3.3.1.1 Semantics of the service primitive
116.3.3.1.2 When generated
116.3.3.1.3 Effect of receipt
116.3.3.2 IS_UNITDATA_i.indication
116.3.3.2.1 Semantics of the service primitive
116.3.3.2.2 When generated
116.3.3.2.3 Effect of receipt
116.3.3.3 IS_SIGNAL.indication
116.3.3.3.1 Semantics of the service primitive
116.3.3.3.2 When generated
116.3.3.3.3 Effect of receipt
116.4 Delay constraints
116.5 Skew constraints
116.6 FEC Degrade
116.7 State diagrams
116.8 Protocol implementation conformance statement (PICS) proforma
117. Reconciliation Sublayer (RS) and Media Independent Interface for 200 Gb/s and 400 Gb/s operation (200GMII and 400GMII)
117.1 Overview
117.1.1 Summary of major concepts
117.1.2 Application
117.1.3 Rate of operation
117.1.4 Delay constraints
117.1.5 Allocation of functions
117.1.6 200GMII/400GMII structure
117.1.7 Mapping of 200GMII/400GMII signals to PLS service primitives
117.2 200GMII/400GMII data stream
117.3 200GMII/400GMII functional specifications
117.4 LPI Assertion and Detection
117.5 Protocol implementation conformance statement (PICS) proforma for Clause 117, Reconciliation Sublayer (RS) and Media Independent Interface for 200 Gb/s and 400 Gb/s operation (200GMII and 400GMII)
117.5.1 Introduction
117.5.2 Identification
117.5.2.1 Implementation identification
117.5.2.2 Protocol summary
117.5.3 Major capabilities/options
117.5.4 PICS proforma tables for Reconciliation Sublayer (RS) and Media Independent Interface for 200 Gb/s and 400 Gb/s operation (200GMII and 400GMII)
117.5.4.1 General
117.5.4.2 Mapping of PLS service primitives
117.5.4.3 Data stream structure
117.5.4.4 200GMII/400GMII signal functional specifications
117.5.4.5 Link fault signaling state diagram
117.5.4.6 LPI functions
118. 200GMII Extender, 400GMII Extender, 200GMII Extender Sublayer (200GXS), and 400GMII Extender Sublayer (400GXS)
118.1 Overview
118.1.1 Summary of major concepts
118.1.2 200GXS/400GXS Sublayer
118.1.3 200GAUI-n/400GAUI-n
118.2 FEC Degrade
118.2.1 DTE XS FEC Degrade signaling
118.2.2 PHY XS FEC Degrade signaling
118.3 200GXS and 400GXS partitioning example
118.4 200GXS and 400GXS MDIO function mapping
118.5 Protocol implementation conformance statement (PICS) proforma for Clause 118, 200GMII Extender, 400GMII Extender, 200GMII Extender Sublayer (200GXS), and 400GMII Extender Sublayer (400GXS)
118.5.1 Introduction
118.5.2 Identification
118.5.2.1 Implementation identification
118.5.2.2 Protocol summary
118.5.3 Major capabilities/options
118.5.4 PICS proforma tables for 200GMII Extender, 400GMII Extender, 200GMII Extender Sublayer (200GXS), and 400GMII Extender Sublayer (400GXS)
118.5.4.1 Transmit function
118.5.4.2 Receive function
118.5.4.3 64B/66B coding rules
118.5.4.4 Scrambler and descrambler
118.5.4.5 Alignment markers
118.5.5 Test-pattern modes
118.5.6 Bit order
118.5.7 Management
118.5.7.1 State diagrams
118.5.7.2 Loopback
118.5.7.3 Delay constraints
119. Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R
119.1 Overview
119.1.1 Scope
119.1.2 Relationship of 200GBASE-R and 400GBASE-R to other standards
119.1.3 Physical Coding Sublayer (PCS)
119.1.4 Inter-sublayer interfaces
119.1.4.1 PCS service interface (200GMII/400GMII)
119.1.4.2 Physical Medium Attachment (PMA) service interface
119.1.5 Functional block diagram
119.2 Physical Coding Sublayer (PCS)
119.2.1 Functions within the PCS
119.2.2 Use of blocks
119.2.3 64B/66B code
119.2.3.1 Notation conventions
119.2.3.2 64B/66B block structure
119.2.3.3 Control codes
119.2.3.4 Valid and invalid blocks
119.2.3.5 Idle (/I/)
119.2.3.6 Start (/S/)
119.2.3.7 Terminate (/T/)
119.2.3.8 Ordered set (/O/)
119.2.3.9 Error (/E/)
119.2.4 Transmit
119.2.4.1 Encode and rate matching
119.2.4.2 64B/66B to 256B/257B transcoder
119.2.4.3 Scrambler
119.2.4.4 Alignment marker mapping and insertion
119.2.4.4.1 AM creation for the 200GBASE-R PCS
119.2.4.4.2 AM creation for the 400GBASE-R PCS
119.2.4.5 Pre-FEC distribution
119.2.4.6 Reed-Solomon encoder
119.2.4.7 Symbol distribution
119.2.4.8 Transmit bit ordering and distribution
119.2.4.9 Test-pattern generators
119.2.5 Receive function
119.2.5.1 Alignment lock and deskew
119.2.5.2 Lane reorder and de-interleave
119.2.5.3 Reed-Solomon decoder
119.2.5.4 Post FEC interleave
119.2.5.5 Alignment marker removal
119.2.5.6 Descrambler
119.2.5.7 256B/257B to 64B/66B transcoder
119.2.5.8 Decode and rate matching
119.2.6 Detailed functions and state diagrams
119.2.6.1 State diagram conventions
119.2.6.2 State variables
119.2.6.2.1 Constants
119.2.6.2.2 Variables
119.2.6.2.3 Functions
119.2.6.2.4 Counters
119.2.6.3 State diagrams
119.3 PCS management
119.3.1 PCS MDIO function mapping
119.4 Loopback
119.5 Delay constraints
119.6 Protocol implementation conformance statement (PICS) proforma for Clause 119, Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R
119.6.1 Introduction
119.6.2 Identification
119.6.2.1 Implementation identification
119.6.2.2 Protocol summary
119.6.3 Major capabilities/options
119.6.4 PICS proforma tables for Physical Coding Sublayer (PCS) 64B/66B, type 200GBASE-R and 400GBASE-R
119.6.4.1 Transmit function
119.6.4.2 Receive function
119.6.4.3 64B/66B coding rules
119.6.4.4 Scrambler and descrambler
119.6.4.5 Alignment markers
119.6.4.6 Test-pattern modes
119.6.4.7 Bit order
119.6.4.8 Management
119.6.4.9 State diagrams
119.6.4.10 Loopback
119.6.4.11 Delay constraints
120. Physical Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R
120.1 Overview
120.1.1 Scope
120.1.2 Position of the PMA in the 200GBASE-R and 400GBASE-R sublayers
120.1.3 Summary of functions
120.1.4 PMA sublayer positioning
120.2 PMA interfaces
120.3 PMA service interface
120.4 Service interface below PMA
120.5 Functions within the PMA
120.5.1 Per input-lane clock and data recovery
120.5.2 Bit-level multiplexing
120.5.3 Skew and Skew Variation
120.5.3.1 Skew generation toward SP1
120.5.3.2 Skew tolerance at SP1
120.5.3.3 Skew generation toward SP2
120.5.3.4 Skew tolerance at SP5
120.5.3.5 Skew generation at SP6
120.5.3.6 Skew tolerance at SP6
120.5.4 Delay constraints
120.5.5 Clocking architecture
120.5.6 Signal drivers
120.5.7 Gray mapping for PAM4 encoded lanes
120.5.8 Link status
120.5.9 PMA local loopback mode (optional)
120.5.10 PMA remote loopback mode (optional)
120.5.11 PMA test patterns (optional)
120.5.11.1 Test patterns for NRZ encoded signals
120.5.11.1.1 PRBS31 test pattern
120.5.11.1.2 PRBS9 test pattern
120.5.11.1.3 Square wave test pattern
120.5.11.2 Test patterns for PAM4 encoded signals
120.5.11.2.1 PRBS13Q test pattern
120.5.11.2.2 PRBS31Q test pattern
120.5.11.2.3 SSPRQ test pattern
120.5.11.2.4 Square wave (quaternary) test pattern
120.6 PMA MDIO function mapping
120.7 Protocol implementation conformance statement (PICS) proforma for Clause 120, Physical Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R
120.7.1 Introduction
120.7.2 Identification
120.7.2.1 Implementation identification
120.7.2.2 Protocol summary
120.7.3 Major capabilities/options
120.7.4 Skew generation and tolerance
120.7.5 Test patterns
120.7.6 Loopback modes
121. Physical Medium Dependent (PMD) sublayer and medium, type 200GBASE-DR4
121.1 Overview
121.1.1 Bit error ratio
121.2 Physical Medium Dependent (PMD) service interface
121.3 Delay and Skew
121.3.1 Delay constraints
121.3.2 Skew constraints
121.4 PMD MDIO function mapping
121.5 PMD functional specifications
121.5.1 PMD block diagram
121.5.2 PMD transmit function
121.5.3 PMD receive function
121.5.4 PMD global signal detect function
121.5.5 PMD lane-by-lane signal detect function
121.5.6 PMD reset function
121.5.7 PMD global transmit disable function (optional)
121.5.8 PMD lane-by-lane transmit disable function (optional)
121.5.9 PMD fault function (optional)
121.5.10 PMD transmit fault function (optional)
121.5.11 PMD receive fault function (optional)
121.6 Lane assignments
121.7 PMD to MDI optical specifications for 200GBASE-DR4
121.7.1 200GBASE-DR4 transmitter optical specifications
121.7.2 200GBASE-DR4 receive optical specifications
121.7.3 200GBASE-DR4 illustrative link power budget
121.8 Definition of optical parameters and measurement methods
121.8.1 Test patterns for optical parameters
121.8.2 Wavelength
121.8.3 Average optical power
121.8.4 Outer Optical Modulation Amplitude (OMAouter)
121.8.5 Transmitter and dispersion eye closure for PAM4 (TDECQ)
121.8.5.1 TDECQ conformance test setup
121.8.5.2 Channel requirements
121.8.5.3 TDECQ measurement method
121.8.5.4 TDECQ reference equalizer
121.8.6 Extinction ratio
121.8.7 Relative intensity noise (RIN21.4OMA)
121.8.8 Receiver sensitivity
121.8.9 Stressed receiver sensitivity
121.8.9.1 Stressed receiver conformance test block diagram
121.8.9.2 Stressed receiver conformance test signal characteristics and calibration
121.8.9.3 Stressed receiver conformance test signal verification
121.8.9.4 Sinusoidal jitter for receiver conformance test
121.9 Safety, installation, environment, and labeling
121.9.1 General safety
121.9.2 Laser safety
121.9.3 Installation
121.9.4 Environment
121.9.5 Electromagnetic emission
121.9.6 Temperature, humidity, and handling
121.9.7 PMD labeling requirements
121.10 Fiber optic cabling model
121.11 Characteristics of the fiber optic cabling (channel)
121.11.1 Optical fiber cable
121.11.2 Optical fiber connection
121.11.2.1 Connection insertion loss
121.11.2.2 Maximum discrete reflectance
121.11.3 Medium Dependent Interface (MDI)
121.11.3.1 Optical lane assignments
121.11.3.2 Medium Dependent Interface (MDI) requirements
121.12 Protocol implementation conformance statement (PICS) proforma for Clause 121, Physical Medium Dependent (PMD) sublayer and medium, type 200GBASE-DR4
121.12.1 Introduction
121.12.2 Identification
121.12.2.1 Implementation identification
121.12.2.2 Protocol summary
121.12.3 Major capabilities/options
121.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 200GBASE-DR4
121.12.4.1 PMD functional specifications
121.12.4.2 Management functions
121.12.4.3 PMD to MDI optical specifications for 200GBASE-DR4
121.12.4.4 Optical measurement methods
121.12.4.5 Environmental specifications
121.12.4.6 Characteristics of the fiber optic cabling and MDI
122. Physical Medium Dependent (PMD) sublayer and medium, type 200GBASE-FR4, 200GBASE-LR4, 400GBASE-FR8, and 400GBASE-LR8
122.1 Overview
122.1.1 Bit error ratio
122.2 Physical Medium Dependent (PMD) service interface
122.3 Delay and Skew
122.3.1 Delay constraints
122.3.2 Skew constraints
122.4 PMD MDIO function mapping
122.5 PMD functional specifications
122.5.1 PMD block diagram
122.5.2 PMD transmit function
122.5.3 PMD receive function
122.5.4 PMD global signal detect function
122.5.5 PMD lane-by-lane signal detect function
122.5.6 PMD reset function
122.5.7 PMD global transmit disable function (optional)
122.5.8 PMD lane-by-lane transmit disable function
122.5.9 PMD fault function (optional)
122.5.10 PMD transmit fault function (optional)
122.5.11 PMD receive fault function (optional)
122.6 Wavelength-division-multiplexed lane assignments
122.7 PMD to MDI optical specifications for 200GBASE-FR4, 200GBASE-LR4, 400GBASE-FR8, and 400GBASE-LR8
122.7.1 200GBASE-FR4, 200GBASE-LR4, 400GBASE-FR8, and 400GBASE-LR8 transmitter optical specifications
122.7.2 200GBASE-FR4, 200GBASE-LR4, 400GBASE-FR8, and 400GBASE-LR8 receive optical specifications
122.7.3 200GBASE-FR4, 200GBASE-LR4, 400GBASE-FR8, and 400GBASE-LR8 illustrative link power budgets
122.8 Definition of optical parameters and measurement methods
122.8.1 Test patterns for optical parameters
122.8.2 Wavelength
122.8.3 Average optical power
122.8.4 Outer Optical Modulation Amplitude (OMAouter)
122.8.5 Transmitter and dispersion eye closure for PAM4 (TDECQ)
122.8.5.1 TDECQ conformance test setup
122.8.5.2 Channel requirements
122.8.5.3 TDECQ measurement method
122.8.5.4 TDECQ reference equalizer
122.8.6 Extinction ratio
122.8.7 Relative intensity noise (RIN16.5OMA and RIN15.1OMA)
122.8.8 Receiver sensitivity
122.8.9 Stressed receiver sensitivity
122.8.9.1 Stressed receiver conformance test block diagram
122.8.9.2 Stressed receiver conformance test signal characteristics and calibration
122.8.9.3 Stressed receiver conformance test signal verification
122.9 Safety, installation, environment, and labeling
122.9.1 General safety
122.9.2 Laser safety
122.9.3 Installation
122.9.4 Environment
122.9.5 Electromagnetic emission
122.9.6 Temperature, humidity, and handling
122.9.7 PMD labeling requirements
122.10 Fiber optic cabling model
122.11 Characteristics of the fiber optic cabling (channel)
122.11.1 Optical fiber cable
122.11.2 Optical fiber connection
122.11.2.1 Connection insertion loss
122.11.2.2 Maximum discrete reflectance
122.11.3 Medium Dependent Interface (MDI) requirements
122.12 Protocol implementation conformance statement (PICS) proforma for Clause 122, Physical Medium Dependent (PMD) sublayer and medium, type 200GBASE-FR4, 200GBASE-LR4, 400GBASE-FR8, and 400GBASE-LR8
122.12.1 Introduction
122.12.2 Identification
122.12.2.1 Implementation identification
122.12.2.2 Protocol summary
122.12.3 Major capabilities/options
122.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 200GBASE-FR4, 200GBASE-LR4, 400GBASE-FR8, and 400GBASE-LR8
122.12.4.1 PMD functional specifications
122.12.4.2 Management functions
122.12.4.3 PMD to MDI optical specifications for 200GBASE-FR4
122.12.4.4 PMD to MDI optical specifications for 200GBASE-LR4
122.12.4.5 PMD to MDI optical specifications for 400GBASE-FR8
122.12.4.6 PMD to MDI optical specifications for 400GBASE-LR8
122.12.4.7 Optical measurement methods
122.12.4.8 Environmental specifications
122.12.4.9 Characteristics of the fiber optic cabling and MDI
123. Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-SR16
123.1 Overview
123.1.1 Bit error ratio
123.2 Physical Medium Dependent (PMD) service interface
123.3 Delay and Skew
123.3.1 Delay constraints
123.3.2 Skew constraints
123.4 PMD MDIO function mapping
123.5 PMD functional specifications
123.5.1 PMD block diagram
123.5.2 PMD transmit function
123.5.3 PMD receive function
123.5.4 PMD global signal detect function
123.5.5 PMD lane-by-lane signal detect function
123.5.6 PMD reset function
123.5.7 PMD global transmit disable function (optional)
123.5.8 PMD lane-by-lane transmit disable function (optional)
123.5.9 PMD fault function (optional)
123.5.10 PMD transmit fault function (optional)
123.5.11 PMD receive fault function (optional)
123.6 Lane assignments
123.7 PMD to MDI optical specifications for 400GBASE-SR16
123.7.1 400GBASE-SR16 transmitter optical specifications
123.7.2 400GBASE-SR16 receive optical specifications
123.7.3 400GBASE-SR16 illustrative link power budget
123.8 Definition of optical parameters and measurement methods
123.8.1 Test patterns for optical parameters
123.8.2 Center wavelength and spectral width
123.8.3 Average optical power
123.8.4 Optical Modulation Amplitude (OMA)
123.8.5 Transmitter and dispersion eye closure (TDEC)
123.8.6 Extinction ratio
123.8.7 Transmitter optical waveform (transmit eye)
123.8.8 Stressed receiver sensitivity
123.9 Safety, installation, environment, and labeling
123.9.1 General safety
123.9.2 Laser safety
123.9.3 Installation
123.9.4 Environment
123.9.5 Electromagnetic emission
123.9.6 Temperature, humidity, and handling
123.9.7 PMD labeling requirements
123.10 Fiber optic cabling model
123.11 Characteristics of the fiber optic cabling (channel)
123.11.1 Optical fiber cable
123.11.2 Optical fiber connection
123.11.2.1 Connection insertion loss
123.11.2.2 Maximum discrete reflectance
123.11.3 Medium Dependent Interface (MDI)
123.11.3.1 Optical lane assignments
123.11.3.2 Medium Dependent Interface (MDI) requirements
123.12 Protocol implementation conformance statement (PICS) proforma for Clause 123, Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-SR16
123.12.1 Introduction
123.12.2 Identification
123.12.2.1 Implementation identification
123.12.2.2 Protocol summary
123.12.3 Major capabilities/options
123.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-SR16
123.12.4.1 PMD functional specifications
123.12.4.2 Management functions
123.12.4.3 PMD to MDI optical specifications for 400GBASE-SR16
123.12.4.4 Optical measurement methods
123.12.4.5 Environmental specifications
123.12.4.6 Characteristics of the fiber optic cabling and MDI
124. Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-DR4
124.1 Overview
124.1.1 Bit error ratio
124.2 Physical Medium Dependent (PMD) service interface
124.3 Delay and Skew
124.3.1 Delay constraints
124.3.2 Skew constraints
124.4 PMD MDIO function mapping
124.5 PMD functional specifications
124.5.1 PMD block diagram
124.5.2 PMD transmit function
124.5.3 PMD receive function
124.5.4 PMD global signal detect function
124.5.5 PMD lane-by-lane signal detect function
124.5.6 PMD reset function
124.5.7 PMD global transmit disable function (optional)
124.5.8 PMD lane-by-lane transmit disable function (optional)
124.5.9 PMD fault function (optional)
124.5.10 PMD transmit fault function (optional)
124.5.11 PMD receive fault function (optional)
124.6 Lane assignments
124.7 PMD to MDI optical specifications for 400GBASE-DR4
124.7.1 400GBASE-DR4 transmitter optical specifications
124.7.2 400GBASE-DR4 receive optical specifications
124.7.3 400GBASE-DR4 illustrative link power budget
124.8 Definition of optical parameters and measurement methods
124.8.1 Test patterns for optical parameters
124.8.2 Wavelength
124.8.3 Average optical power
124.8.4 Outer Optical Modulation Amplitude (OMAouter)
124.8.5 Transmitter and dispersion eye closure for PAM4 (TDECQ)
124.8.6 Extinction ratio
124.8.7 Relative intensity noise (RIN21.4OMA)
124.8.8 Receiver sensitivity
124.8.9 Stressed receiver sensitivity
124.9 Safety, installation, environment, and labeling
124.9.1 General safety
124.9.2 Laser safety
124.9.3 Installation
124.9.4 Environment
124.9.5 Electromagnetic emission
124.9.6 Temperature, humidity, and handling
124.9.7 PMD labeling requirements
124.10 Fiber optic cabling model
124.11 Characteristics of the fiber optic cabling (channel)
124.11.1 Optical fiber cable
124.11.2 Optical fiber connection
124.11.2.1 Connection insertion loss
124.11.2.2 Maximum discrete reflectance
124.11.3 Medium Dependent Interface (MDI)
124.11.3.1 Optical lane assignments
124.11.3.2 Medium Dependent Interface (MDI) requirements
124.12 Protocol implementation conformance statement (PICS) proforma for Clause 124, Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-DR4
124.12.1 Introduction
124.12.2 Identification
124.12.2.1 Implementation identification
124.12.2.2 Protocol summary
124.12.3 Major capabilities/options
124.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-DR4
124.12.4.1 PMD functional specifications
124.12.4.2 Management functions
124.12.4.3 PMD to MDI optical specifications for 400GBASE-DR4
124.12.4.4 Optical measurement methods
124.12.4.5 Environmental specifications
124.12.4.6 Characteristics of the fiber optic cabling and MDI
Annex A (informative) Bibliography
Annex 4A (normative) Simplified full duplex media access control
4A.4 Specific implementations
4A.4.2 MAC parameters
Annex 31B (normative) MAC Control PAUSE operation
31B.3 Detailed specification of PAUSE operation
31B.3.7 Timing considerations for PAUSE operation
31B.4 Protocol implementation conformance statement (PICS) proforma for MAC Control PAUSE operation
31B.4.3 Major capabilities/options
31B.4.6 PAUSE command MAC timing considerations
Annex 93A (normative) Specification methods for electrical channels
93A.1 Channel Operating Margin
93A.1.2 Transmitter and receiver device package models
93A.1.2.3 Two-port network for the package transmission line
93A.1.4 Filters
93A.1.4.3 Receiver equalizer
93A.1.6 Determination of variable equalizer parameters
93A.1.7 Interference and noise amplitude
Annex 119A (informative) 200GBASE-R and 400GBASE-R PCS FEC codeword examples
Annex 120A (informative) 200 Gb/s and 400 Gb/s PMA sublayer partitioning examples
120A.1 Partitioning example supporting 400GBASE-SR16
120A.2 Partitioning examples supporting 200GBASE-DR4/FR4/LR4 and 400GBASE-FR8/LR8
120A.3 Partitioning examples supporting 400GBASE-DR4
120A.4 Partitioning example using 200GXS and 400GXS
Annex 120B (normative) Chip-to-chip 200 Gb/s eight-lane Attachment Unit Interface (200GAUI-8 C2C) and 400 Gb/s sixteen-lane Attachment Unit Interface (400GAUI-16 C2C)
120B.1 Overview
120B.2 200GAUI-8 and 400GAUI-16 chip-to-chip compliance point definition
120B.3 200GAUI-8 and 400GAUI-16 chip-to-chip electrical characteristics
120B.3.1 200GAUI-8 and 400GAUI-16 C2C transmitter characteristics
120B.3.2 200GAUI-8 and 400GAUI-16 C2C receiver characteristics
120B.4 200GAUI-8 and 400GAUI-16 chip-to-chip channel characteristics
120B.5 Protocol implementation conformance statement (PICS) proforma for Annex 120B, Chip-to-chip 200 Gb/s eight-lane Attachment Unit Interface (200GAUI-8 C2C) and 400 Gb/s sixteen-lane Attachment Unit Interface (400GAUI-16 C2C)
120B.5.1 Introduction
120B.5.2 Identification
120B.5.2.1 Implementation identification
120B.5.2.2 Protocol summary
120B.5.3 Major capabilities/options
120B.5.4 PICS proforma tables for Chip-to-chip 200 Gb/s eight-lane Attachment Unit Interface (200GAUI-8 C2C) and 400 Gb/s sixteen-lane Attachment Unit Interface (400GAUI-16 C2C)
120B.5.4.1 Transmitter
120B.5.4.2 Receiver
120B.5.4.3 Channel
Annex 120C (normative) Chip-to-module 200 Gb/s eight-lane Attachment Unit Interface (200GAUI-8 C2M) and 400 Gb/s sixteen-lane Attachment Unit Interface (400GAUI-16 C2M)
120C.1 Overview
120C.1.1 Bit error ratio
120C.2 200GAUI-8 and 400GAUI-16 chip-to-module compliance point definitions
120C.3 200GAUI-8 and 400GAUI-16 chip-to-module electrical characteristics
120C.3.1 200GAUI-8 and 400GAUI-16 C2M host output characteristics
120C.3.2 200GAUI-8 and 400GAUI-16 C2M module output characteristics
120C.3.3 200GAUI-8 and 400GAUI-16 C2M host input characteristics
120C.3.4 200GAUI-8 and 400GAUI-16 C2M module input characteristics
120C.4 200GAUI-8 and 400GAUI-16 C2M measurement methodology
120C.5 Protocol implementation conformance statement (PICS) proforma for Annex 120C, Chip-to-module 200 Gb/s eight-lane Attachment Unit Interface (200GAUI-8 C2M) and 400 Gb/s sixteen-lane Attachment Unit Interface (400GAUI-16 C2M)
120C.5.1 Introduction
120C.5.2 Identification
120C.5.2.1 Implementation identification
120C.5.2.2 Protocol summary
120C.5.3 Major capabilities/options
120C.5.4 PICS proforma tables for Chip-to-module 200 Gb/s eight-lane Attachment Unit Interface (200GAUI-8 C2M) and 400 Gb/s sixteen-lane Attachment Unit Interface (400GAUI-16 C2M)
120C.5.4.1 Host output
120C.5.4.2 Module output
120C.5.4.3 Host input
120C.5.4.4 Module input
Annex 120D (normative) Chip-to-chip 200 Gb/s four-lane Attachment Unit Interface (200GAUI-4 C2C) and 400 Gb/s eight-lane Attachment Unit Interface (400GAUI-8 C2C)
120D.1 Overview
120D.2 200GAUI-4 and 400GAUI-8 chip-to-chip compliance point definition
120D.3 200GAUI-4 and 400GAUI-8 chip-to-chip electrical characteristics
120D.3.1 200GAUI-4 and 400GAUI-8 C2C transmitter characteristics
120D.3.1.1 Transmitter differential output return loss
120D.3.1.2 Transmitter linearity
120D.3.1.2.1 Measurement of mean signal levels
120D.3.1.3 Linear fit to the measured waveform
120D.3.1.4 Steady-state voltage and linear fit pulse peak
120D.3.1.5 Transmitter equalization settings
120D.3.1.6 Transmitter output noise and distortion
120D.3.1.7 Transmitter output residual ISI
120D.3.1.8 Output jitter
120D.3.1.8.1 J4u and JRMS jitter
120D.3.1.8.2 Even-odd Jitter
120D.3.2 200GAUI-4 and 400GAUI-8 C2C receiver characteristics
120D.3.2.1 Receiver interference tolerance
120D.3.2.2 Receiver jitter tolerance
120D.3.2.3 Transmitter equalization feedback (optional)
120D.4 200GAUI-4 and 400GAUI-8 chip-to-chip channel characteristics
120D.4.1 Channel Operating Margin
120D.4.2 Channel return loss
120D.5 Protocol implementation conformance statement (PICS) proforma for Annex 120D, Chip-to-chip 200 Gb/s four-lane Attachment Unit Interface (200GAUI-4 C2C) and 400 Gb/s eight-lane Attachment Unit Interface (400GAUI-8 C2C)
120D.5.1 Introduction
120D.5.2 Identification
120D.5.2.1 Implementation identification
120D.5.2.2 Protocol summary
120D.5.3 Major capabilities/options
120D.5.4 PICS proforma tables for Chip-to-chip 200 Gb/s four-lane Attachment Unit Interface (200GAUI-4 C2C) and 400 Gb/s eight-lane Attachment Unit Interface (400GAUI-8 C2C)
120D.5.4.1 Transmitter
120D.5.4.2 Receiver
120D.5.4.3 Channel
Annex 120E (normative) Chip-to-module 200 Gb/s four-lane Attachment Unit Interface (200GAUI-4 C2M) and 400 Gb/s eight-lane Attachment Unit Interface (400GAUI-8 C2M)
120E.1 Overview
120E.1.1 Bit error ratio
120E.2 200GAUI-4 and 400GAUI-8 chip-to-module compliance point definitions
120E.3 200GAUI-4 and 400GAUI-8 chip-to-module electrical characteristics
120E.3.1 200GAUI-4 and 400GAUI-8 C2M host output characteristics
120E.3.1.1 Signaling rate and range
120E.3.1.2 Signal levels
120E.3.1.3 Output return loss
120E.3.1.4 Differential termination mismatch
120E.3.1.5 Transition time
120E.3.1.6 Host output eye width and eye height
120E.3.1.7 Reference receiver for eye width and eye height evaluation
120E.3.2 200GAUI-4 and 400GAUI-8 C2M module output characteristics
120E.3.2.1 Module output eye width, eye height, and pre-cursor ISI ratio
120E.3.2.1.1 Reference receiver for module output evaluation
120E.3.2.1.2 Far-end pre-cursor ISI ratio
120E.3.3 200GAUI-4 and 400GAUI-8 C2M host input characteristics
120E.3.3.1 Input return loss
120E.3.3.2 Host stressed input test
120E.3.3.2.1 Host stressed input test procedure
120E.3.4 200GAUI-4 and 400GAUI-8 C2M module input characteristics
120E.3.4.1 Module stressed input test
120E.3.4.1.1 Module stressed input test procedure
120E.4 200GAUI-4 and 400GAUI-8 C2M measurement methodology
120E.4.1 HCB/MCB characteristics
120E.4.2 Eye width and eye height measurement method
120E.5 Protocol implementation conformance statement (PICS) proforma for Annex 120E, Chip-to-module 200 Gb/s four-lane Attachment Unit Interface (200GAUI-4 C2M) and 400 Gb/s eight-lane Attachment Unit Interface (400GAUI-8 C2M)
120E.5.1 Introduction
120E.5.2 Identification
120E.5.2.1 Implementation identification
120E.5.2.2 Protocol summary
120E.5.3 Major capabilities/options
120E.5.4 PICS proforma tables for Chip-to-module 200 Gb/s four-lane Attachment Unit Interface (200GAUI-4 C2M) and 400 Gb/s eight-lane Attachment Unit Interface (400GAUI-8 C2M)
120E.5.4.1 Host output
120E.5.4.2 Module output
120E.5.4.3 Host input
120E.5.4.4 Module input
IEEE P802.3bs™/D3.5, 10th October 2017
(Amendment of IEEE Std 802.3™-2015 as amended by [list to be populated during publication process])
IEEE P802.3bs™/D3.5
Draft Standard for Ethernet
Amendment 10:
Media Access Control Parameters, Physical
Layers and Management Parameters for
200 Gb/s and 400 Gb/s Operation
Prepared by the
LAN/MAN Standards Committee
of the
IEEE Computer Society
This draft is an amendment of IEEE Std 802.3-2015 as amended by IEEE Std 802.3bw-2015, IEEE Std
802.3by-2016, IEEE Std 802.3bq-2016, IEEE Std 802.3bp-2016, IEEE Std 802.3br-2016, IEEE Std
802.3bn-2016, IEEE Std 802.3bz-2016, IEEE Std 802.3bu-2016, IEEE Std 802.3bv-2017, and IEEE Std
802.3-2015/Cor 1-2017. This amendment defines IEEE 802.3 Media Access Control (MAC) parameters,
Physical Layer specifications, and management parameters for the transfer of IEEE 802.3 format frames at
200 Gb/s and 400 Gb/s. Draft D3.5 is prepared for Sponsor ballot recirculation. This draft expires 6 months
after the date of publication or when the next version is published, whichever comes first.
Copyright © 2017 by The Institute of Electrical and Electronics Engineers, Inc.
Three Park Avenue
New York, New York 10016-5997, USA
All rights reserved.
This document is an unapproved draft of a proposed IEEE Standard. As such, this document is subject to
change. USE AT YOUR OWN RISK! IEEE copyright statements SHALL NOT BE REMOVED from draft
or approved IEEE standards, or modified in any way. Because this is an unapproved draft, this document
must not be utilized for any conformance/compliance purposes. Permission is hereby granted for officers
from each IEEE Standards Working Group or Committee to reproduce the draft document developed by that
Working Group for purposes of standardization consideration by ISO/IEC. IEEE Standards Department
must be informed of the submission for consideration prior to any reproduction (stds.ipr@ieee.org). Prior to
adoption of this document, in whole or in part, by another standards development organization, permission
must first be obtained from the IEEE Standards Department (stds.ipr@ieee.org). When requesting permis-
sion, IEEE Standards Department will require a copy of the standard development organization's document
highlighting the use of IEEE content. Other entities seeking permission to reproduce this document, in
whole or in part, must also obtain permission from the IEEE Standards Department.
IEEE Standards Department
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Abstract: This amendment to IEEE Std 802.3-2015 adds Clause 116 through Clause 124 and
Annex 119A through Annex 120E. This amendment includes IEEE 802.3 Media Access Control
(MAC) parameters, Physical Layer specifications, and management parameters for the transfer of
IEEE 802.3 format frames at 200 Gb/s and 400 Gb/s.
Keywords: 200 Gb/s Ethernet, 200GAUI-4, 200GAUI-8, 200GBASE-DR4, 200GBASE-FR4,
200GBASE-LR4, 200GBASE-R, 200GMII, 200GXS, 400 Gb/s Ethernet, 400GAUI-8, 400GAUI-16,
400GBASE-DR4, 400GBASE-FR8, 400GBASE-LR8, 400GBASE-SR16, 400GBASE-R, 400GMII,
400GXS, Energy Efficient Ethernet (EEE), Ethernet, forward error correction (FEC), IEEE 802.3™,
IEEE Std 802.3bs™, MMF, PAM4, Physical Medium Dependent (PMD) sublayer, SMF
The Institute of Electrical and Electronics Engineers, Inc.
3 Park Avenue, New York, NY 10016-5997, USA
Copyright © 2017 by the Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published xx Month 201x. Printed in the United States of America.
IEEE and 802 are registered trademarks in the U.S. Patent & Trademark Office, owned by the Institute of Electrical and
Electronics Engineers, Incorporated.
PDF:
Print:
ISBN 978-0-7381-xxxx-x STDxxxxx
ISBN 978-0-7381-xxxx-x STDPDxxxxx
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No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission
of the publisher.
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IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force
IEEE Draft P802.3bs/D3.5
10th October 2017
Editor’s Note (to be removed prior to publication):
This front matter is provided for comment only. Front matter is not part of a published standard and is
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in the published standard after approval.
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10th October 2017
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IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force
IEEE Draft P802.3bs/D3.5
10th October 2017
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IEEE Draft P802.3bs/D3.5
10th October 2017
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IEEE Draft P802.3bs/D3.5
10th October 2017
Participants
The following individuals were officers and members of the IEEE 802.3 working group at the beginning of
the IEEE P802.3bs working group ballot. Individuals may have not voted, voted for approval, disapproval or
abstained on this standard.
David J. Law, IEEE 802.3 Working Group Chair
Adam Healey, IEEE 802.3 Working Group Vice-Chair
Pete Anslow, IEEE 802.3 Working Group Secretary
Steven B. Carlson, IEEE 802.3 Working Group Executive Secretary
Valerie Maguire, IEEE 802.3 Working Group Treasurer
John D’Ambrosia, IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force Chair
Pete Anslow, IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force Editor-in-Chief
Mark Gustlin, IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force Editor
Steve Trowbridge, IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force Editor
for Clauses 117, 118, 119, Annex 119A
for Clause 120, Annex 120A
for Clauses 121, 122, 124
for Clause 123
for Annexes 120D, 120E
Peter Stassar, IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force Editor
Jonathan King1, IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force Editor
Andre Szczepanek, IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force Editor
Justin Abbott
David Abramson
Shadi Abughazaleh
Mohammad Ahmed
Eric Baden
Amrik Bains
Thananya Baldwin
Denis Beaudoin
Christian Beia
Michael Bennett
Vipul Bhatt
William Bliss
Brad Booth
Martin Bouda
Ralf-Peter Braun
Theodore Brillhart
Paul Brooks
Alan Brown
Matthew Brown
Chris Bullock
Jairo Bustos Heredia
Adrian Butter
Francesco Caggioni
Anthony Calbone
Clark Carty
Craig Chabot
Geoffrey Chacon Simon
Mandeep Chadha
David Chalupsky
Jacky Chang
Xin Chang
Ahmad Chini
Keng Hua Chuang
Christopher R. Cole
Yair Darshan
Piers Dawe
Fred Dawson
Wael Diab
Eric DiBiaso
John Dillard
Daniel Dillow
Thuyen Dinh
Curtis Donahue
Dan Dove
Mike Dudek
David Dwelley
Frank Effenberger
Hesham Elbakoury
David Estes
John Ewen
Ramin Farjad
Shahar Feldman
James Fife
Alan Flatman
Matthias Fritsche
Richard Frosch
Andrew Gardner
Claude Gauthier
Ali Ghiasi
Joel Goergen
Volker Goetzfried
Zhigang Gong
Steven Gorshe
Robert Grow
Marek Hajduczenia
Takehiro Hayashi
Yasuo Hidaka
Rita Horner
Bernd Horrmeyer
Victor Hou
Yasuhiro Hyakutake
Hideki Isono
Tom Issenhuth
Kenneth Jackson
Andrew Jimenez
Chad Jones
Peter Jones
Manabu Kagami
Upen Kareti
Keisuke Kawahara
Yasuaki Kawatsu
Michael Kelsen
Scott Kipp
Michael Klempa
1Not a member of the IEEE 802.3 working group at the beginning of the working group ballot.
Copyright © 2017 IEEE. All rights reserved.
This is an unapproved IEEE Standards draft, subject to change.
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IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force
IEEE Draft P802.3bs/D3.5
10th October 2017
Curtis Knittle
Shigeru Kobayashi
Daniel Koehler
Paul Kolesar
Tom Kolze
Glen Kramer
Hans Lackner
Jeffrey Lapak
Mark Laubach
Han Hyub Lee
David Lewis
Jon Lewis
Mike Peng Li
Jane Lim
Dekun Liu
Hai-Feng Liu
William Lo
Miklos Lukacs
Kent Lusted
Jeffery Maki
David Malicoat
Yonatan Malkiman
Arthur Marris
Takeo Masuda
Erdem Matoglu
Naoki Matsuda
Mick McCarthy
Brett Mcclellan
Thomas Mcdermott
John McDonough
Larry McMillan
Richard Mei
Richard Mellitz
Bryan Moffitt
Ardeshir Mohammadian
Paul Mooney
Dale Murray
Henry Muyshondt
James Nadolny
Edward Nakamoto
Gary Nicholl
Kevin Noll
Mark Nowell
David Ofelt
Tom Palkert
Hui Pan
Sesha Panguluri
Vasu Parthasarathy
Petar Pepeljugoski
Gerald Pepper
Ruben Perez De Aranda Alonso
Michael Peters
Phong Pham
Jean Picard
William Powell
Rick Rabinovich
Adee Ran
Alon Regev
Duane Remein
Victor Renteria
Christopher Roth
Salvatore Rotolo
Toshiaki Sakai
Jorge Salinger
Sam Sambasivan
Edward Sayre
Dieter Schicketanz
Fred Schindler
Hossein Sedarat
Naoshi Serizawa
Masood Shariff
ramin Shirani
Tom Skaar
Jeff Slavick
Daniel Smith
Scott Sommers
Yoshiaki Sone
Tom Souvignier
Heath Stewart
Robert Stone
David Stover
Junqing Sun
Ken-Ichi Suzuki
Steve Swanson
William Szeto
Bharat Tailor
Takayuki Tajima
Satoshi Takahashi
Kohichi Tamura
Brian Teipen
Geoffrey Thompson
Pirooz Tooyserkani
Albert Tretter
Yoshihiro Tsukamoto
Ed Ulrichs
Alexander Umnov
Sterling A. Vaden
Stefano Valle
Paul Vanderlaan
Robert Wagner
Dylan Walker
Haifei Wang
Roy Wang
Tongtong Wang
Xinyuan Wang
Matthias Wendt
Oded Wertheim
Natalie Wienckowski
Ludwig Winkel
Peter Wu
Dayin Xu
Yu Xu
Jun Yi
Lennart Yseboodt
Hayato Yuki
Andrew Zambell
Yan Zhuang
George Zimmerman
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This is an unapproved IEEE Standards draft, subject to change.
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