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TMS320F28379寄存器手册.pdf
Table of Contents
Preface
1 C2000Ware Quick Start Guide
1.1 Package Structure
1.1.1 Documentation
1.1.2 Devices
1.1.3 Libraries
1.2 C2000Ware GUI
1.3 Updating C2000Ware
1.4 Code Composer Studio
3 System Control
3.1 Introduction
3.2 System Control Functional Description
3.2.1 Device Identification
3.2.2 Device Configuration Registers
3.3 Resets
3.3.1 Reset Sources
3.3.2 External Reset (XRS)
3.3.3 Power-On Reset (POR)
3.3.4 Debugger Reset (SYSRS)
3.3.5 Watchdog Reset (WDRS)
3.3.6 NMI Watchdog Reset (NMIWDRS)
3.3.7 DCSM Safe Code Copy Reset (SCCRESET)
3.3.8 Hibernate Reset (HIBRESET)
3.3.9 Hardware BIST Reset (HWBISTRS)
3.3.10 Test Reset (TRST)
3.4 Peripheral Interrupts
3.4.1 Interrupt Concepts
3.4.2 Interrupt Architecture
3.4.2.1 Peripheral Stage
3.4.2.2 PIE Stage
3.4.2.3 CPU Stage
3.4.2.4 Dual-CPU Interrupt Handling
3.4.3 Interrupt Entry Sequence
3.4.4 Configuring and Using Interrupts
3.4.4.1 Enabling Interrupts
3.4.4.2 Handling Interrupts
3.4.4.3 Disabling Interrupts
3.4.4.4 Nesting Interrupts
3.4.5 PIE Channel Mapping
3.4.6 Vector Tables
3.5 Exceptions and Non-Maskable Interrupts
3.5.1 Configuring and Using NMIs
3.5.2 Emulation Considerations
3.5.3 NMI Sources
3.5.3.1 Missing Clock Detection
3.5.3.2 RAM Uncorrectable ECC Error
3.5.3.3 Flash Uncorrectable ECC Error
3.5.3.4 NMI Vector Fetch Mismatch
3.5.3.5 CPU2 Watchdog or NMI Watchdog Reset
3.5.4 Illegal Instruction Trap (ITRAP)
3.6 Safety Features
3.6.1 Write Protection on Registers
3.6.1.1 LOCK Protection on System Configuration Registers
3.6.1.2 EALLOW Protection
3.6.2 Missing Clock Detection Logic
3.6.3 PLLSLIP Detection
3.6.4 CPU1 and CPU2 PIE Vector Address Validity Check
3.6.5 NMIWDs
3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection
3.6.7 ECC Enabled Flash Memory
3.6.8 ERRORSTS Pin
3.7 Clocking
3.7.1 Clock Sources
3.7.1.1 Primary Internal Oscillator (INTOSC2)
3.7.1.2 Backup Internal Oscillator (INTOSC1)
3.7.1.3 External Oscillator (XTAL)
3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
3.7.2 Derived Clocks
3.7.2.1 Oscillator Clock (OSCCLK)
3.7.2.2 System PLL Output Clock (PLLRAWCLK)
3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
3.7.3 Device Clock Domains
3.7.3.1 System Clock (PLLSYSCLK)
3.7.3.2 CPU Clock (CPUCLK)
3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
3.7.3.6 CAN Bit Clock
3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
3.7.4 XCLKOUT
3.7.5 Clock Connectivity
3.7.6 Clock Source and PLL Setup
3.7.6.1 Choosing PLL Settings
3.7.6.2 System Clock Setup
3.7.6.3 USB Auxiliary Clock Setup
3.7.6.4 Clock Configuration Examples
3.8 32-Bit CPU Timers 0/1/2
3.9 Watchdog Timers
3.9.1 Servicing the Watchdog Timer
3.9.2 Minimum Window Check
3.9.3 Watchdog Reset or Watchdog Interrupt Mode
3.9.4 Watchdog Operation in Low Power Modes
3.9.5 Emulation Considerations
3.10 Low Power Modes
3.10.1 IDLE
3.10.2 STANDBY
3.10.3 HALT
3.10.4 HIB
3.11 Memory Controller Module
3.11.1 Functional Description
3.11.1.1 Dedicated RAM (Dx RAM)
3.11.1.2 Local Shared RAM (LSx RAM)
3.11.1.3 Global Shared RAM (GSx RAM)
3.11.1.4 CPU Message RAM (CPU MSG RAM)
3.11.1.5 CLA Message RAM (CLA MSGRAM)
3.11.1.6 Access Arbitration
3.11.1.7 Access Protection
3.11.1.7.1 CPU Fetch Protection
3.11.1.7.2 CPU Write Protection
3.11.1.7.3 CPU Read Protection
3.11.1.7.4 CLA Fetch Protection
3.11.1.7.5 CLA Write Protection
3.11.1.7.6 CLA Read Protection
3.11.1.7.7 DMA Write Protection
3.11.1.8 Memory Error Detection, Correction and Error Handling
3.11.1.8.1 Error Detection and Correction
3.11.1.8.2 Error Handling
3.11.1.9 Application Test Hooks for Error Detection and Correction
3.11.1.10 RAM Initialization
3.12 Flash and OTP Memory
3.12.1 Features
3.12.2 Flash Tools
3.12.3 Default Flash Configuration
3.12.4 Flash Bank, OTP and Pump
3.12.5 Flash Module Controller (FMC)
3.12.6 Flash and OTP Power-Down Modes and Wakeup
3.12.7 Flash and OTP Performance
3.12.8 Flash Read Interface
3.12.8.1 FMC Flash Read Interface
3.12.8.1.1 Standard Read Mode
3.12.8.1.2 Prefetch Mode
3.12.9 Erase/Program Flash
3.12.9.1 Erase
3.12.9.2 Program
3.12.9.3 Verify
3.12.10 Error Correction Code (ECC) Protection
3.12.10.1 Single-Bit Data Error
3.12.10.2 Uncorrectable Error
3.12.10.3 SECDED Logic Correctness Check
3.12.10.4 Reading ECC Memory From a Higher Address Space
3.12.11 Reserved Locations Within Flash and OTP
3.12.12 Procedure to Change the Flash Control Registers
3.12.13 Flash Pump Ownership Semaphore
3.12.13.1 Clock Configuration Semaphore
3.13 Dual Code Security Module (DCSM)
3.13.1 Functional Description
3.13.1.1 Emulation Code Security Logic (ECSL)
3.13.1.2 CPU Secure Logic
3.13.1.3 Execute-Only Protection
3.13.1.4 Password Lock
3.13.1.5 Link Pointer and Zone Select
3.13.1.5.1 C Code Example to get Zone Select Block Addr for Zone1
3.13.1.6 Flash and OTP Erase/Program
3.13.1.7 Safe Copy Code
3.13.1.8 SafeCRC
3.13.2 CSM Impact on Other On-Chip Resources
3.13.3 Incorporating Code Security in User Applications
3.13.3.1 Environments That Require Security Unlocking
3.13.3.2 CSM Password Match Flow
3.13.3.3 Unsecuring Considerations for Zones With and Without Code Security
3.13.3.3.1 C Code Example to Unsecure C28x Zone1
3.13.3.3.2 C Code Example to Resecure C28x Zone1
3.13.3.4 Environments That Require ECSL Unlocking
3.13.3.5 ECSL Password Match Flow
3.13.3.6 ECSL Disable Considerations for any Zone
3.13.3.6.1 C Code Example to Disable ECSL for C28x-Zone1
3.13.3.7 Device Unique ID
3.14 JTAG
3.15 F2837xD System Control Registers
3.15.1 F2837xD System Control Base Addresses
3.15.2 CPUTIMER_REGS Registers
3.15.2.1 TIM Register (Offset = 0h) [reset = FFFFh]
3.15.2.2 PRD Register (Offset = 2h) [reset = 0001FFFFh]
3.15.2.3 TCR Register (Offset = 4h) [reset = 1h]
3.15.2.4 TPR Register (Offset = 6h) [reset = 0h]
3.15.2.5 TPRH Register (Offset = 7h) [reset = 0h]
3.15.3 PIE_CTRL_REGS Registers
3.15.3.1 PIECTRL Register (Offset = 0h) [reset = 0h]
3.15.3.2 PIEACK Register (Offset = 1h) [reset = 0h]
3.15.3.3 PIEIER1 Register (Offset = 2h) [reset = 0h]
3.15.3.4 PIEIFR1 Register (Offset = 3h) [reset = 0h]
3.15.3.5 PIEIER2 Register (Offset = 4h) [reset = 0h]
3.15.3.6 PIEIFR2 Register (Offset = 5h) [reset = 0h]
3.15.3.7 PIEIER3 Register (Offset = 6h) [reset = 0h]
3.15.3.8 PIEIFR3 Register (Offset = 7h) [reset = 0h]
3.15.3.9 PIEIER4 Register (Offset = 8h) [reset = 0h]
3.15.3.10 PIEIFR4 Register (Offset = 9h) [reset = 0h]
3.15.3.11 PIEIER5 Register (Offset = Ah) [reset = 0h]
3.15.3.12 PIEIFR5 Register (Offset = Bh) [reset = 0h]
3.15.3.13 PIEIER6 Register (Offset = Ch) [reset = 0h]
3.15.3.14 PIEIFR6 Register (Offset = Dh) [reset = 0h]
3.15.3.15 PIEIER7 Register (Offset = Eh) [reset = 0h]
3.15.3.16 PIEIFR7 Register (Offset = Fh) [reset = 0h]
3.15.3.17 PIEIER8 Register (Offset = 10h) [reset = 0h]
3.15.3.18 PIEIFR8 Register (Offset = 11h) [reset = 0h]
3.15.3.19 PIEIER9 Register (Offset = 12h) [reset = 0h]
3.15.3.20 PIEIFR9 Register (Offset = 13h) [reset = 0h]
3.15.3.21 PIEIER10 Register (Offset = 14h) [reset = 0h]
3.15.3.22 PIEIFR10 Register (Offset = 15h) [reset = 0h]
3.15.3.23 PIEIER11 Register (Offset = 16h) [reset = 0h]
3.15.3.24 PIEIFR11 Register (Offset = 17h) [reset = 0h]
3.15.3.25 PIEIER12 Register (Offset = 18h) [reset = 0h]
3.15.3.26 PIEIFR12 Register (Offset = 19h) [reset = 0h]
3.15.4 WD_REGS Registers
3.15.4.1 SCSR Register (Offset = 22h) [reset = 5h]
3.15.4.2 WDCNTR Register (Offset = 23h) [reset = 0h]
3.15.4.3 WDKEY Register (Offset = 25h) [reset = 0h]
3.15.4.4 WDCR Register (Offset = 29h) [reset = 0h]
3.15.4.5 WDWCR Register (Offset = 2Ah) [reset = 0h]
3.15.5 NMI_INTRUPT_REGS Registers
3.15.5.1 NMICFG Register (Offset = 0h) [reset = 0h]
3.15.5.2 NMIFLG Register (Offset = 1h) [reset = 0h]
3.15.5.3 NMIFLGCLR Register (Offset = 2h) [reset = 0h]
3.15.5.4 NMIFLGFRC Register (Offset = 3h) [reset = 0h]
3.15.5.5 NMIWDCNT Register (Offset = 4h) [reset = 0h]
3.15.5.6 NMIWDPRD Register (Offset = 5h) [reset = FFFFh]
3.15.5.7 NMISHDFLG Register (Offset = 6h) [reset = 0h]
3.15.6 XINT_REGS Registers
3.15.6.1 XINT1CR Register (Offset = 0h) [reset = 0h]
3.15.6.2 XINT2CR Register (Offset = 1h) [reset = 0h]
3.15.6.3 XINT3CR Register (Offset = 2h) [reset = 0h]
3.15.6.4 XINT4CR Register (Offset = 3h) [reset = 0h]
3.15.6.5 XINT5CR Register (Offset = 4h) [reset = 0h]
3.15.6.6 XINT1CTR Register (Offset = 8h) [reset = 0h]
3.15.6.7 XINT2CTR Register (Offset = 9h) [reset = 0h]
3.15.6.8 XINT3CTR Register (Offset = Ah) [reset = 0h]
3.15.7 DMA_CLA_SRC_SEL_REGS Registers
3.15.7.1 CLA1TASKSRCSELLOCK Register (Offset = 0h) [reset = 0h]
3.15.7.2 DMACHSRCSELLOCK Register (Offset = 4h) [reset = 0h]
3.15.7.3 CLA1TASKSRCSEL1 Register (Offset = 6h) [reset = 0h]
3.15.7.4 CLA1TASKSRCSEL2 Register (Offset = 8h) [reset = 0h]
3.15.7.5 DMACHSRCSEL1 Register (Offset = 16h) [reset = 0h]
3.15.7.6 DMACHSRCSEL2 Register (Offset = 18h) [reset = 0h]
3.15.8 FLASH_PUMP_SEMAPHORE_REGS Registers
3.15.8.1 PUMPREQUEST Register (Offset = 0h) [reset = 0h]
3.15.9 DEV_CFG_REGS Registers
3.15.9.1 DEVCFGLOCK1 Register (Offset = 0h) [reset = 0h]
3.15.9.2 PARTIDL Register (Offset = 8h) [reset = 0h]
3.15.9.3 PARTIDH Register (Offset = Ah) [reset = 0h]
3.15.9.4 REVID Register (Offset = Ch) [reset = X]
3.15.9.5 DC0 Register (Offset = 10h) [reset = 1h]
3.15.9.6 DC1 Register (Offset = 12h) [reset = 0h]
3.15.9.7 DC2 Register (Offset = 14h) [reset = 0h]
3.15.9.8 DC3 Register (Offset = 16h) [reset = 0h]
3.15.9.9 DC4 Register (Offset = 18h) [reset = 0h]
3.15.9.10 DC5 Register (Offset = 1Ah) [reset = 0h]
3.15.9.11 DC6 Register (Offset = 1Ch) [reset = 0h]
3.15.9.12 DC7 Register (Offset = 1Eh) [reset = 0h]
3.15.9.13 DC8 Register (Offset = 20h) [reset = 0h]
3.15.9.14 DC9 Register (Offset = 22h) [reset = 0h]
3.15.9.15 DC10 Register (Offset = 24h) [reset = 0h]
3.15.9.16 DC11 Register (Offset = 26h) [reset = 0h]
3.15.9.17 DC12 Register (Offset = 28h) [reset = 0h]
3.15.9.18 DC13 Register (Offset = 2Ah) [reset = 0h]
3.15.9.19 DC14 Register (Offset = 2Ch) [reset = 0h]
3.15.9.20 DC15 Register (Offset = 2Eh) [reset = 0h]
3.15.9.21 DC17 Register (Offset = 32h) [reset = 0h]
3.15.9.22 DC18 Register (Offset = 34h) [reset = 0h]
3.15.9.23 DC19 Register (Offset = 36h) [reset = 0h]
3.15.9.24 DC20 Register (Offset = 38h) [reset = 0h]
3.15.9.25 PERCNF1 Register (Offset = 60h) [reset = 0h]
3.15.9.26 FUSEERR Register (Offset = 74h) [reset = 0h]
3.15.9.27 SOFTPRES0 Register (Offset = 82h) [reset = 0h]
3.15.9.28 SOFTPRES1 Register (Offset = 84h) [reset = 0h]
3.15.9.29 SOFTPRES2 Register (Offset = 86h) [reset = 0h]
3.15.9.30 SOFTPRES3 Register (Offset = 88h) [reset = 0h]
3.15.9.31 SOFTPRES4 Register (Offset = 8Ah) [reset = 0h]
3.15.9.32 SOFTPRES6 Register (Offset = 8Eh) [reset = 0h]
3.15.9.33 SOFTPRES7 Register (Offset = 90h) [reset = 0h]
3.15.9.34 SOFTPRES8 Register (Offset = 92h) [reset = 0h]
3.15.9.35 SOFTPRES9 Register (Offset = 94h) [reset = 0h]
3.15.9.36 SOFTPRES11 Register (Offset = 98h) [reset = 0h]
3.15.9.37 SOFTPRES13 Register (Offset = 9Ch) [reset = 0h]
3.15.9.38 SOFTPRES14 Register (Offset = 9Eh) [reset = 0h]
3.15.9.39 SOFTPRES16 Register (Offset = A2h) [reset = 0h]
3.15.9.40 CPUSEL0 Register (Offset = D6h) [reset = 0h]
3.15.9.41 CPUSEL1 Register (Offset = D8h) [reset = 0h]
3.15.9.42 CPUSEL2 Register (Offset = DAh) [reset = 0h]
3.15.9.43 CPUSEL3 Register (Offset = DCh) [reset = 0h]
3.15.9.44 CPUSEL4 Register (Offset = DEh) [reset = 0h]
3.15.9.45 CPUSEL5 Register (Offset = E0h) [reset = 0h]
3.15.9.46 CPUSEL6 Register (Offset = E2h) [reset = 0h]
3.15.9.47 CPUSEL7 Register (Offset = E4h) [reset = 0h]
3.15.9.48 CPUSEL8 Register (Offset = E6h) [reset = 0h]
3.15.9.49 CPUSEL9 Register (Offset = E8h) [reset = 0h]
3.15.9.50 CPUSEL11 Register (Offset = ECh) [reset = 0h]
3.15.9.51 CPUSEL12 Register (Offset = EEh) [reset = 0h]
3.15.9.52 CPUSEL14 Register (Offset = F2h) [reset = 0h]
3.15.9.53 CPU2RESCTL Register (Offset = 122h) [reset = 1h]
3.15.9.54 RSTSTAT Register (Offset = 124h) [reset = 0h]
3.15.9.55 LPMSTAT Register (Offset = 125h) [reset = 0h]
3.15.9.56 SYSDBGCTL Register (Offset = 12Ch) [reset = 0h]
3.15.10 CLK_CFG_REGS Registers
3.15.10.1 CLKSEM Register (Offset = 0h) [reset = 0h]
3.15.10.2 CLKCFGLOCK1 Register (Offset = 2h) [reset = 0h]
3.15.10.3 CLKSRCCTL1 Register (Offset = 8h) [reset = 0h]
3.15.10.4 CLKSRCCTL2 Register (Offset = Ah) [reset = 0h]
3.15.10.5 CLKSRCCTL3 Register (Offset = Ch) [reset = 0h]
3.15.10.6 SYSPLLCTL1 Register (Offset = Eh) [reset = 0h]
3.15.10.7 SYSPLLMULT Register (Offset = 14h) [reset = 0h]
3.15.10.8 SYSPLLSTS Register (Offset = 16h) [reset = 0h]
3.15.10.9 AUXPLLCTL1 Register (Offset = 18h) [reset = 0h]
3.15.10.10 AUXPLLMULT Register (Offset = 1Eh) [reset = 0h]
3.15.10.11 AUXPLLSTS Register (Offset = 20h) [reset = 0h]
3.15.10.12 SYSCLKDIVSEL Register (Offset = 22h) [reset = 2h]
3.15.10.13 AUXCLKDIVSEL Register (Offset = 24h) [reset = 1h]
3.15.10.14 PERCLKDIVSEL Register (Offset = 26h) [reset = 51h]
3.15.10.15 XCLKOUTDIVSEL Register (Offset = 28h) [reset = 3h]
3.15.10.16 LOSPCP Register (Offset = 2Ch) [reset = 2h]
3.15.10.17 MCDCR Register (Offset = 2Eh) [reset = 0h]
3.15.10.18 X1CNT Register (Offset = 30h) [reset = 0h]
3.15.11 CPU_SYS_REGS Registers
3.15.11.1 CPUSYSLOCK1 Register (Offset = 0h) [reset = 0h]
3.15.11.2 HIBBOOTMODE Register (Offset = 6h) [reset = Fh]
3.15.11.3 IORESTOREADDR Register (Offset = 8h) [reset = 003FFFFFh]
3.15.11.4 PIEVERRADDR Register (Offset = Ah) [reset = 003FFFFFh]
3.15.11.5 PCLKCR0 Register (Offset = 22h) [reset = 38h]
3.15.11.6 PCLKCR1 Register (Offset = 24h) [reset = 0h]
3.15.11.7 PCLKCR2 Register (Offset = 26h) [reset = 0h]
3.15.11.8 PCLKCR3 Register (Offset = 28h) [reset = 0h]
3.15.11.9 PCLKCR4 Register (Offset = 2Ah) [reset = 0h]
3.15.11.10 PCLKCR6 Register (Offset = 2Eh) [reset = 0h]
3.15.11.11 PCLKCR7 Register (Offset = 30h) [reset = 0h]
3.15.11.12 PCLKCR8 Register (Offset = 32h) [reset = 0h]
3.15.11.13 PCLKCR9 Register (Offset = 34h) [reset = 0h]
3.15.11.14 PCLKCR10 Register (Offset = 36h) [reset = 0h]
3.15.11.15 PCLKCR11 Register (Offset = 38h) [reset = 0h]
3.15.11.16 PCLKCR12 Register (Offset = 3Ah) [reset = 0h]
3.15.11.17 PCLKCR13 Register (Offset = 3Ch) [reset = 0h]
3.15.11.18 PCLKCR14 Register (Offset = 3Eh) [reset = 0h]
3.15.11.19 PCLKCR16 Register (Offset = 42h) [reset = 0h]
3.15.11.20 SECMSEL Register (Offset = 74h) [reset = 0h]
3.15.11.21 LPMCR Register (Offset = 76h) [reset = FCh]
3.15.11.22 GPIOLPMSEL0 Register (Offset = 78h) [reset = 0h]
3.15.11.23 GPIOLPMSEL1 Register (Offset = 7Ah) [reset = 0h]
3.15.11.24 TMR2CLKCTL Register (Offset = 7Ch) [reset = 0h]
3.15.11.25 RESC Register (Offset = 80h) [reset = X]
3.15.12 ROM_PREFETCH_REGS Registers
3.15.12.1 ROMPREFETCH Register (Offset = 0h) [reset = 0h]
3.15.13 DCSM_Z1_OTP Registers
3.15.13.1 Z1OTP_LINKPOINTER1 Register (Offset = 0h) [reset = FFFFFFFFh]
3.15.13.2 Z1OTP_LINKPOINTER2 Register (Offset = 4h) [reset = FFFFFFFFh]
3.15.13.3 Z1OTP_LINKPOINTER3 Register (Offset = 8h) [reset = FFFFFFFFh]
3.15.13.4 Z1OTP_PSWDLOCK Register (Offset = 10h) [reset = FFFFFFFFh]
3.15.13.5 Z1OTP_CRCLOCK Register (Offset = 14h) [reset = FFFFFFFFh]
3.15.13.6 Z1OTP_BOOTCTRL Register (Offset = 1Eh) [reset = FFFFFFFFh]
3.15.14 DCSM_Z2_OTP Registers
3.15.14.1 Z2OTP_LINKPOINTER1 Register (Offset = 0h) [reset = FFFFFFFFh]
3.15.14.2 Z2OTP_LINKPOINTER2 Register (Offset = 4h) [reset = FFFFFFFFh]
3.15.14.3 Z2OTP_LINKPOINTER3 Register (Offset = 8h) [reset = FFFFFFFFh]
3.15.14.4 Z2OTP_PSWDLOCK Register (Offset = 10h) [reset = FFFFFFFFh]
3.15.14.5 Z2OTP_CRCLOCK Register (Offset = 14h) [reset = FFFFFFFFh]
3.15.14.6 Z2OTP_BOOTCTRL Register (Offset = 1Eh) [reset = FFFFFFFFh]
3.15.15 DCSM_Z1_REGS Registers
3.15.15.1 Z1_LINKPOINTER Register (Offset = 0h) [reset = E0000000h]
3.15.15.2 Z1_OTPSECLOCK Register (Offset = 2h) [reset = FFFh]
3.15.15.3 Z1_BOOTCTRL Register (Offset = 4h) [reset = 0h]
3.15.15.4 Z1_LINKPOINTERERR Register (Offset = 6h) [reset = FFFFFFFFh]
3.15.15.5 Z1_CSMKEY0 Register (Offset = 10h) [reset = 0h]
3.15.15.6 Z1_CSMKEY1 Register (Offset = 12h) [reset = 0h]
3.15.15.7 Z1_CSMKEY2 Register (Offset = 14h) [reset = 0h]
3.15.15.8 Z1_CSMKEY3 Register (Offset = 16h) [reset = 0h]
3.15.15.9 Z1_CR Register (Offset = 19h) [reset = 8h]
3.15.15.10 Z1_GRABSECTR Register (Offset = 1Ah) [reset = 0h]
3.15.15.11 Z1_GRABRAMR Register (Offset = 1Ch) [reset = 0h]
3.15.15.12 Z1_EXEONLYSECTR Register (Offset = 1Eh) [reset = 0h]
3.15.15.13 Z1_EXEONLYRAMR Register (Offset = 20h) [reset = 0h]
3.15.16 DCSM_Z2_REGS Registers
3.15.16.1 Z2_LINKPOINTER Register (Offset = 0h) [reset = E0000000h]
3.15.16.2 Z2_OTPSECLOCK Register (Offset = 2h) [reset = FFFh]
3.15.16.3 Z2_BOOTCTRL Register (Offset = 4h) [reset = 0h]
3.15.16.4 Z2_LINKPOINTERERR Register (Offset = 6h) [reset = FFFFFFFFh]
3.15.16.5 Z2_CSMKEY0 Register (Offset = 10h) [reset = 0h]
3.15.16.6 Z2_CSMKEY1 Register (Offset = 12h) [reset = 0h]
3.15.16.7 Z2_CSMKEY2 Register (Offset = 14h) [reset = 0h]
3.15.16.8 Z2_CSMKEY3 Register (Offset = 16h) [reset = 0h]
3.15.16.9 Z2_CR Register (Offset = 19h) [reset = 8h]
3.15.16.10 Z2_GRABSECTR Register (Offset = 1Ah) [reset = 0h]
3.15.16.11 Z2_GRABRAMR Register (Offset = 1Ch) [reset = 0h]
3.15.16.12 Z2_EXEONLYSECTR Register (Offset = 1Eh) [reset = 0h]
3.15.16.13 Z2_EXEONLYRAMR Register (Offset = 20h) [reset = 0h]
3.15.17 DCSM_COMMON_REGS Registers
3.15.17.1 FLSEM Register (Offset = 0h) [reset = 0h]
3.15.17.2 SECTSTAT Register (Offset = 2h) [reset = 0h]
3.15.17.3 RAMSTAT Register (Offset = 4h) [reset = 0h]
3.15.18 MEM_CFG_REGS Registers
3.15.18.1 DxLOCK Register (Offset = 0h) [reset = 0h]
3.15.18.2 DxCOMMIT Register (Offset = 2h) [reset = 0h]
3.15.18.3 DxACCPROT0 Register (Offset = 8h) [reset = 0h]
3.15.18.4 DxTEST Register (Offset = 10h) [reset = 0h]
3.15.18.5 DxINIT Register (Offset = 12h) [reset = 0h]
3.15.18.6 DxINITDONE Register (Offset = 14h) [reset = 0h]
3.15.18.7 LSxLOCK Register (Offset = 20h) [reset = 0h]
3.15.18.8 LSxCOMMIT Register (Offset = 22h) [reset = 0h]
3.15.18.9 LSxMSEL Register (Offset = 24h) [reset = 0h]
3.15.18.10 LSxCLAPGM Register (Offset = 26h) [reset = 0h]
3.15.18.11 LSxACCPROT0 Register (Offset = 28h) [reset = 0h]
3.15.18.12 LSxACCPROT1 Register (Offset = 2Ah) [reset = 0h]
3.15.18.13 LSxTEST Register (Offset = 30h) [reset = 0h]
3.15.18.14 LSxINIT Register (Offset = 32h) [reset = 0h]
3.15.18.15 LSxINITDONE Register (Offset = 34h) [reset = 0h]
3.15.18.16 GSxLOCK Register (Offset = 40h) [reset = 0h]
3.15.18.17 GSxCOMMIT Register (Offset = 42h) [reset = 0h]
3.15.18.18 GSxMSEL Register (Offset = 44h) [reset = 0h]
3.15.18.19 GSxACCPROT0 Register (Offset = 48h) [reset = 0h]
3.15.18.20 GSxACCPROT1 Register (Offset = 4Ah) [reset = 0h]
3.15.18.21 GSxACCPROT2 Register (Offset = 4Ch) [reset = 0h]
3.15.18.22 GSxACCPROT3 Register (Offset = 4Eh) [reset = 0h]
3.15.18.23 GSxTEST Register (Offset = 50h) [reset = 0h]
3.15.18.24 GSxINIT Register (Offset = 52h) [reset = 0h]
3.15.18.25 GSxINITDONE Register (Offset = 54h) [reset = 0h]
3.15.18.26 MSGxTEST Register (Offset = 70h) [reset = 0h]
3.15.18.27 MSGxINIT Register (Offset = 72h) [reset = 0h]
3.15.18.28 MSGxINITDONE Register (Offset = 74h) [reset = 0h]
3.15.19 ACCESS_PROTECTION_REGS Registers
3.15.19.1 NMAVFLG Register (Offset = 0h) [reset = 0h]
3.15.19.2 NMAVSET Register (Offset = 2h) [reset = 0h]
3.15.19.3 NMAVCLR Register (Offset = 4h) [reset = 0h]
3.15.19.4 NMAVINTEN Register (Offset = 6h) [reset = 0h]
3.15.19.5 NMCPURDAVADDR Register (Offset = 8h) [reset = 0h]
3.15.19.6 NMCPUWRAVADDR Register (Offset = Ah) [reset = 0h]
3.15.19.7 NMCPUFAVADDR Register (Offset = Ch) [reset = 0h]
3.15.19.8 NMDMAWRAVADDR Register (Offset = Eh) [reset = 0h]
3.15.19.9 NMCLA1RDAVADDR Register (Offset = 10h) [reset = 0h]
3.15.19.10 NMCLA1WRAVADDR Register (Offset = 12h) [reset = 0h]
3.15.19.11 NMCLA1FAVADDR Register (Offset = 14h) [reset = 0h]
3.15.19.12 MAVFLG Register (Offset = 20h) [reset = 0h]
3.15.19.13 MAVSET Register (Offset = 22h) [reset = 0h]
3.15.19.14 MAVCLR Register (Offset = 24h) [reset = 0h]
3.15.19.15 MAVINTEN Register (Offset = 26h) [reset = 0h]
3.15.19.16 MCPUFAVADDR Register (Offset = 28h) [reset = 0h]
3.15.19.17 MCPUWRAVADDR Register (Offset = 2Ah) [reset = 0h]
3.15.19.18 MDMAWRAVADDR Register (Offset = 2Ch) [reset = 0h]
3.15.20 MEMORY_ERROR_REGS Registers
3.15.20.1 UCERRFLG Register (Offset = 0h) [reset = 0h]
3.15.20.2 UCERRSET Register (Offset = 2h) [reset = 0h]
3.15.20.3 UCERRCLR Register (Offset = 4h) [reset = 0h]
3.15.20.4 UCCPUREADDR Register (Offset = 6h) [reset = 0h]
3.15.20.5 UCDMAREADDR Register (Offset = 8h) [reset = 0h]
3.15.20.6 UCCLA1READDR Register (Offset = Ah) [reset = 0h]
3.15.20.7 CERRFLG Register (Offset = 20h) [reset = 0h]
3.15.20.8 CERRSET Register (Offset = 22h) [reset = 0h]
3.15.20.9 CERRCLR Register (Offset = 24h) [reset = 0h]
3.15.20.10 CCPUREADDR Register (Offset = 26h) [reset = 0h]
3.15.20.11 CERRCNT Register (Offset = 2Eh) [reset = 0h]
3.15.20.12 CERRTHRES Register (Offset = 30h) [reset = 0h]
3.15.20.13 CEINTFLG Register (Offset = 32h) [reset = 0h]
3.15.20.14 CEINTCLR Register (Offset = 34h) [reset = 0h]
3.15.20.15 CEINTSET Register (Offset = 36h) [reset = 0h]
3.15.20.16 CEINTEN Register (Offset = 38h) [reset = 0h]
3.15.21 ROM_WAIT_STATE_REGS Registers
3.15.21.1 ROMWAITSTATE Register (Offset = 0h) [reset = 0h]
3.15.22 FLASH_CTRL_REGS Registers
3.15.22.1 FRDCNTL Register (Offset = 0h) [reset = F00h]
3.15.22.2 FBAC Register (Offset = 1Eh) [reset = Fh]
3.15.22.3 FBFALLBACK Register (Offset = 20h) [reset = 0h]
3.15.22.4 FBPRDY Register (Offset = 22h) [reset = 0h]
3.15.22.5 FPAC1 Register (Offset = 24h) [reset = 08600000h]
3.15.22.6 FMSTAT Register (Offset = 2Ah) [reset = 0h]
3.15.22.7 FRD_INTF_CTRL Register (Offset = 180h) [reset = 0h]
3.15.23 FLASH_ECC_REGS Registers
3.15.23.1 ECC_ENABLE Register (Offset = 0h) [reset = Ah]
3.15.23.2 SINGLE_ERR_ADDR_LOW Register (Offset = 2h) [reset = 0h]
3.15.23.3 SINGLE_ERR_ADDR_HIGH Register (Offset = 4h) [reset = 0h]
3.15.23.4 UNC_ERR_ADDR_LOW Register (Offset = 6h) [reset = 0h]
3.15.23.5 UNC_ERR_ADDR_HIGH Register (Offset = 8h) [reset = 0h]
3.15.23.6 ERR_STATUS Register (Offset = Ah) [reset = 0h]
3.15.23.7 ERR_POS Register (Offset = Ch) [reset = 0h]
3.15.23.8 ERR_STATUS_CLR Register (Offset = Eh) [reset = 0h]
3.15.23.9 ERR_CNT Register (Offset = 10h) [reset = 0h]
3.15.23.10 ERR_THRESHOLD Register (Offset = 12h) [reset = 0h]
3.15.23.11 ERR_INTFLG Register (Offset = 14h) [reset = 0h]
3.15.23.12 ERR_INTCLR Register (Offset = 16h) [reset = 0h]
3.15.23.13 FDATAH_TEST Register (Offset = 18h) [reset = 0h]
3.15.23.14 FDATAL_TEST Register (Offset = 1Ah) [reset = 0h]
3.15.23.15 FADDR_TEST Register (Offset = 1Ch) [reset = 0h]
3.15.23.16 FECC_TEST Register (Offset = 1Eh) [reset = 0h]
3.15.23.17 FECC_CTRL Register (Offset = 20h) [reset = 0h]
3.15.23.18 FOUTH_TEST Register (Offset = 22h) [reset = 0h]
3.15.23.19 FOUTL_TEST Register (Offset = 24h) [reset = 0h]
3.15.23.20 FECC_STATUS Register (Offset = 26h) [reset = 0h]
3.15.24 CPU_ID_REGS Registers
3.15.24.1 CPUID Register (Offset = 0h) [reset = X]
3.15.25 UID_REGS Registers
3.15.25.1 UID_PSRAND0 Register (Offset = 0h) [reset = X]
3.15.25.2 UID_PSRAND1 Register (Offset = 2h) [reset = X]
3.15.25.3 UID_PSRAND2 Register (Offset = 4h) [reset = X]
3.15.25.4 UID_PSRAND3 Register (Offset = 6h) [reset = X]
3.15.25.5 UID_PSRAND4 Register (Offset = 8h) [reset = X]
3.15.25.6 UID_PSRAND5 Register (Offset = Ah) [reset = X]
3.15.25.7 UID_UNIQUE Register (Offset = Ch) [reset = X]
3.15.25.8 UID_CHECKSUM Register (Offset = Eh) [reset = X]
4 ROM Code and Peripheral Booting
4.1 Introduction
4.2 Device Boot Philosophy
4.3 Device Boot Modes
4.4 Configuring Boot Mode Pins
4.5 Configuring Get Boot Options
4.6 Configuring Emulation Boot Options
4.7 Device Boot Flow Diagrams
4.7.1 Emulation Boot Flow Diagrams
4.7.2 Standalone and Hibernate Boot Flow Diagrams
4.8 Device Reset and Exception Handling
4.8.1 Reset Causes and Handling
4.8.2 Exceptions and Interrupts Handling
4.9 Boot ROM Description
4.9.1 Entry Points
4.9.2 Wait Points
4.9.3 Memory Maps
4.9.3.1 CPU1 Boot ROM Memory Map
4.9.3.2 CPU2 Boot ROM Memory Map
4.9.3.3 CLA Data ROM Memory Map
4.9.3.4 Reserved RAM and Flash Memory Map
4.9.3.5 ROM Tables
4.9.3.5.1 Boot ROM Tables
4.9.3.5.2 CLA ROM Tables
4.9.4 Boot Modes
4.9.4.1 Wait Boot Mode
4.9.4.2 SCI Boot Mode
4.9.4.3 SPI Boot Mode
4.9.4.4 I2C Boot Mode
4.9.4.5 Parallel Boot Mode
4.9.4.6 CAN Boot Mode
4.9.4.7 USB Boot Mode
4.9.5 Boot Data Stream Structure
4.9.5.1 Bootloader Data Stream Structure
4.9.6 GPIO Assignments
4.9.7 Boot IPC
4.9.7.1 CPU1 IPC Commands
4.9.7.2 CPU2 IPC Commands
4.9.7.3 CPU2 IPC Error Commands
4.9.8 Clock Initializations
4.9.9 Wait State Configuration
4.9.10 Boot Status information
4.9.10.1 CPU1 Booting Status
4.9.10.2 CPU2 Booting Status
4.9.10.3 CPU1 IPC NAK Status
4.9.10.4 CPU2 IPC NAK Status
4.9.11 ROM Version
5 Direct Memory Access (DMA)
5.1 Introduction
5.2 Architecture
5.2.1 Block Diagram
5.2.2 Common Peripheral Architecture
5.2.3 Peripheral Interrupt Event Trigger Sources
5.2.4 DMA Bus
5.3 Address Pointer and Transfer Control
5.4 Pipeline Timing and Throughput
5.5 CPU and CLA Arbitration
5.6 Channel Priority
5.6.1 Round-Robin Mode
5.6.2 Channel 1 High Priority Mode
5.7 Overrun Detection Feature
5.8 DMA Registers
5.8.1 DMA Base Addresses
5.8.2 DMA_REGS Registers
5.8.2.1 DMACTRL Register (Offset = 0h) [reset = 0h]
5.8.2.2 DEBUGCTRL Register (Offset = 1h) [reset = 0h]
5.8.2.3 PRIORITYCTRL1 Register (Offset = 4h) [reset = 0h]
5.8.2.4 PRIORITYSTAT Register (Offset = 6h) [reset = 0h]
5.8.3 DMA_CH_REGS Registers
5.8.3.1 MODE Register (Offset = 0h) [reset = 0h]
5.8.3.2 CONTROL Register (Offset = 1h) [reset = 0h]
5.8.3.3 BURST_SIZE Register (Offset = 2h) [reset = 0h]
5.8.3.4 BURST_COUNT Register (Offset = 3h) [reset = 0h]
5.8.3.5 SRC_BURST_STEP Register (Offset = 4h) [reset = 0h]
5.8.3.6 DST_BURST_STEP Register (Offset = 5h) [reset = 0h]
5.8.3.7 TRANSFER_SIZE Register (Offset = 6h) [reset = 0h]
5.8.3.8 TRANSFER_COUNT Register (Offset = 7h) [reset = 0h]
5.8.3.9 SRC_TRANSFER_STEP Register (Offset = 8h) [reset = 0h]
5.8.3.10 DST_TRANSFER_STEP Register (Offset = 9h) [reset = 0h]
5.8.3.11 SRC_WRAP_SIZE Register (Offset = Ah) [reset = 0h]
5.8.3.12 SRC_WRAP_COUNT Register (Offset = Bh) [reset = 0h]
5.8.3.13 SRC_WRAP_STEP Register (Offset = Ch) [reset = 0h]
5.8.3.14 DST_WRAP_SIZE Register (Offset = Dh) [reset = 0h]
5.8.3.15 DST_WRAP_COUNT Register (Offset = Eh) [reset = 0h]
5.8.3.16 DST_WRAP_STEP Register (Offset = Fh) [reset = 0h]
5.8.3.17 SRC_BEG_ADDR_SHADOW Register (Offset = 10h) [reset = 0h]
5.8.3.18 SRC_ADDR_SHADOW Register (Offset = 12h) [reset = 0h]
5.8.3.19 SRC_BEG_ADDR_ACTIVE Register (Offset = 14h) [reset = 0h]
5.8.3.20 SRC_ADDR_ACTIVE Register (Offset = 16h) [reset = 0h]
5.8.3.21 DST_BEG_ADDR_SHADOW Register (Offset = 18h) [reset = 0h]
5.8.3.22 DST_ADDR_SHADOW Register (Offset = 1Ah) [reset = 0h]
5.8.3.23 DST_BEG_ADDR_ACTIVE Register (Offset = 1Ch) [reset = 0h]
5.8.3.24 DST_ADDR_ACTIVE Register (Offset = 1Eh) [reset = 0h]
6 Control Law Accelerator (CLA)
6.1 Control Law Accelerator (CLA) Overview
6.2 CLA Interface
6.2.1 CLA Memory
6.2.2 CLA Memory Bus
6.2.3 Shared Peripherals and EALLOW Protection
6.2.4 CLA Tasks and Interrupt Vectors
6.2.5 CLA Software Interrupt to CPU
6.3 CLA and CPU Arbitration
6.3.1 CLA Message RAM
6.4 CLA Configuration and Debug
6.4.1 Building a CLA Application
6.4.2 Typical CLA Initialization Sequence
6.4.3 Debugging CLA Code
6.4.3.1 Legacy Breakpoint Support (MDEBUGSTOP)
6.4.4 CLA Illegal Opcode Behavior
6.4.5 Resetting the CLA
6.5 Pipeline
6.5.1 Pipeline Overview
6.5.2 CLA Pipeline Alignment
6.5.2.1 ADC Early Interrupt to CLA Response
6.5.3 Parallel Instructions
6.6 Instruction Set
6.6.1 Instruction Descriptions
6.6.2 Addressing Modes and Encoding
6.6.3 Instructions
6.7 CLA Registers
6.7.1 CLA Base Addresses
6.7.2 CLA_REGS Registers
6.7.2.1 MVECT1 Register (Offset = 0h) [reset = 0h]
6.7.2.2 MVECT2 Register (Offset = 1h) [reset = 0h]
6.7.2.3 MVECT3 Register (Offset = 2h) [reset = 0h]
6.7.2.4 MVECT4 Register (Offset = 3h) [reset = 0h]
6.7.2.5 MVECT5 Register (Offset = 4h) [reset = 0h]
6.7.2.6 MVECT6 Register (Offset = 5h) [reset = 0h]
6.7.2.7 MVECT7 Register (Offset = 6h) [reset = 0h]
6.7.2.8 MVECT8 Register (Offset = 7h) [reset = 0h]
6.7.2.9 MCTL Register (Offset = 10h) [reset = 0h]
6.7.2.10 MIFR Register (Offset = 20h) [reset = 0h]
6.7.2.11 MIOVF Register (Offset = 21h) [reset = 0h]
6.7.2.12 MIFRC Register (Offset = 22h) [reset = 0h]
6.7.2.13 MICLR Register (Offset = 23h) [reset = 0h]
6.7.2.14 MICLROVF Register (Offset = 24h) [reset = 0h]
6.7.2.15 MIER Register (Offset = 25h) [reset = 0h]
6.7.2.16 MIRUN Register (Offset = 26h) [reset = 0h]
6.7.2.17 _MPC Register (Offset = 28h) [reset = 0h]
6.7.2.18 _MAR0 Register (Offset = 2Ah) [reset = 0h]
6.7.2.19 _MAR1 Register (Offset = 2Bh) [reset = 0h]
6.7.2.20 _MSTF Register (Offset = 2Eh) [reset = 0h]
6.7.2.21 _MR0 Register (Offset = 30h) [reset = 0h]
6.7.2.22 _MR1 Register (Offset = 34h) [reset = 0h]
6.7.2.23 _MR2 Register (Offset = 38h) [reset = 0h]
6.7.2.24 _MR3 Register (Offset = 3Ch) [reset = 0h]
6.7.3 CLA_SOFTINT_REGS Registers
6.7.3.1 SOFTINTEN Register (Offset = 0h) [reset = 0h]
6.7.3.2 SOFTINTFRC Register (Offset = 2h) [reset = 0h]
7 Interprocessor Communication (IPC)
2 C28x Processor
2.1 Overview
2.2 Floating-Point Unit
2.3 Trigonometric Math Unit
2.4 Viterbi, Complex Math, and CRC Unit II (VCU-II)
7.1 Interprocessor Communication
7.2 Message RAMs
7.3 IPC Flags and Interrupts
7.4 IPC Command Registers
7.5 Free-Running Counter
7.6 IPC Communication Protocol
7.7 IPC Registers
7.7.1 IPC Base Addresses
7.7.2 IPC_REGS_CPU1 Registers
7.7.2.1 IPCACK Register (Offset = 0h) [reset = 0h]
7.7.2.2 IPCSTS Register (Offset = 2h) [reset = 0h]
7.7.2.3 IPCSET Register (Offset = 4h) [reset = 0h]
7.7.2.4 IPCCLR Register (Offset = 6h) [reset = 0h]
7.7.2.5 IPCFLG Register (Offset = 8h) [reset = 0h]
7.7.2.6 IPCCOUNTERL Register (Offset = Ch) [reset = 0h]
7.7.2.7 IPCCOUNTERH Register (Offset = Eh) [reset = 0h]
7.7.2.8 IPCSENDCOM Register (Offset = 10h) [reset = 0h]
7.7.2.9 IPCSENDADDR Register (Offset = 12h) [reset = 0h]
7.7.2.10 IPCSENDDATA Register (Offset = 14h) [reset = 0h]
7.7.2.11 IPCREMOTEREPLY Register (Offset = 16h) [reset = 0h]
7.7.2.12 IPCRECVCOM Register (Offset = 18h) [reset = 0h]
7.7.2.13 IPCRECVADDR Register (Offset = 1Ah) [reset = 0h]
7.7.2.14 IPCRECVDATA Register (Offset = 1Ch) [reset = 0h]
7.7.2.15 IPCLOCALREPLY Register (Offset = 1Eh) [reset = 0h]
7.7.2.16 IPCBOOTSTS Register (Offset = 20h) [reset = 0h]
7.7.2.17 IPCBOOTMODE Register (Offset = 22h) [reset = 0h]
7.7.3 IPC_REGS_CPU2 Registers
7.7.3.1 IPCACK Register (Offset = 0h) [reset = 0h]
7.7.3.2 IPCSTS Register (Offset = 2h) [reset = 0h]
7.7.3.3 IPCSET Register (Offset = 4h) [reset = 0h]
7.7.3.4 IPCCLR Register (Offset = 6h) [reset = 0h]
7.7.3.5 IPCFLG Register (Offset = 8h) [reset = 0h]
7.7.3.6 IPCCOUNTERL Register (Offset = Ch) [reset = 0h]
7.7.3.7 IPCCOUNTERH Register (Offset = Eh) [reset = 0h]
7.7.3.8 IPCRECVCOM Register (Offset = 10h) [reset = 0h]
7.7.3.9 IPCRECVADDR Register (Offset = 12h) [reset = 0h]
7.7.3.10 IPCRECVDATA Register (Offset = 14h) [reset = 0h]
7.7.3.11 IPCLOCALREPLY Register (Offset = 16h) [reset = 0h]
7.7.3.12 IPCSENDCOM Register (Offset = 18h) [reset = 0h]
7.7.3.13 IPCSENDADDR Register (Offset = 1Ah) [reset = 0h]
7.7.3.14 IPCSENDDATA Register (Offset = 1Ch) [reset = 0h]
7.7.3.15 IPCREMOTEREPLY Register (Offset = 1Eh) [reset = 0h]
7.7.3.16 IPCBOOTSTS Register (Offset = 20h) [reset = 0h]
7.7.3.17 IPCBOOTMODE Register (Offset = 22h) [reset = 0h]
8 General-Purpose Input/Output (GPIO)
8.1 GPIO Overview
8.2 Configuration Overview
8.3 Digital General-Purpose I/O Control
8.4 Input Qualification
8.4.1 No Synchronization (Asynchronous Input)
8.4.2 Synchronization to SYSCLKOUT Only
8.4.3 Qualification Using a Sampling Window
8.5 USB Signals
8.6 SPI Signals
8.7 GPIO and Peripheral Muxing
8.8 Internal Pullup Configuration Requirements
8.9 GPIO Registers
8.9.1 GPIO Base Addresses
8.9.2 GPIO_CTRL_REGS Registers
8.9.2.1 GPACTRL Register (Offset = 0h) [reset = 0h]
8.9.2.2 GPAQSEL1 Register (Offset = 2h) [reset = 0h]
8.9.2.3 GPAQSEL2 Register (Offset = 4h) [reset = 0h]
8.9.2.4 GPAMUX1 Register (Offset = 6h) [reset = 0h]
8.9.2.5 GPAMUX2 Register (Offset = 8h) [reset = 0h]
8.9.2.6 GPADIR Register (Offset = Ah) [reset = 0h]
8.9.2.7 GPAPUD Register (Offset = Ch) [reset = FFFFFFFFh]
8.9.2.8 GPAINV Register (Offset = 10h) [reset = 0h]
8.9.2.9 GPAODR Register (Offset = 12h) [reset = 0h]
8.9.2.10 GPAGMUX1 Register (Offset = 20h) [reset = 0h]
8.9.2.11 GPAGMUX2 Register (Offset = 22h) [reset = 0h]
8.9.2.12 GPACSEL1 Register (Offset = 28h) [reset = 0h]
8.9.2.13 GPACSEL2 Register (Offset = 2Ah) [reset = 0h]
8.9.2.14 GPACSEL3 Register (Offset = 2Ch) [reset = 0h]
8.9.2.15 GPACSEL4 Register (Offset = 2Eh) [reset = 0h]
8.9.2.16 GPALOCK Register (Offset = 3Ch) [reset = 0h]
8.9.2.17 GPACR Register (Offset = 3Eh) [reset = 0h]
8.9.2.18 GPBCTRL Register (Offset = 40h) [reset = 0h]
8.9.2.19 GPBQSEL1 Register (Offset = 42h) [reset = 0h]
8.9.2.20 GPBQSEL2 Register (Offset = 44h) [reset = 0h]
8.9.2.21 GPBMUX1 Register (Offset = 46h) [reset = 0h]
8.9.2.22 GPBMUX2 Register (Offset = 48h) [reset = 0h]
8.9.2.23 GPBDIR Register (Offset = 4Ah) [reset = 0h]
8.9.2.24 GPBPUD Register (Offset = 4Ch) [reset = FFFFFFFFh]
8.9.2.25 GPBINV Register (Offset = 50h) [reset = 0h]
8.9.2.26 GPBODR Register (Offset = 52h) [reset = 0h]
8.9.2.27 GPBAMSEL Register (Offset = 54h) [reset = 0h]
8.9.2.28 GPBGMUX1 Register (Offset = 60h) [reset = 0h]
8.9.2.29 GPBGMUX2 Register (Offset = 62h) [reset = 0h]
8.9.2.30 GPBCSEL1 Register (Offset = 68h) [reset = 0h]
8.9.2.31 GPBCSEL2 Register (Offset = 6Ah) [reset = 0h]
8.9.2.32 GPBCSEL3 Register (Offset = 6Ch) [reset = 0h]
8.9.2.33 GPBCSEL4 Register (Offset = 6Eh) [reset = 0h]
8.9.2.34 GPBLOCK Register (Offset = 7Ch) [reset = 0h]
8.9.2.35 GPBCR Register (Offset = 7Eh) [reset = 0h]
8.9.2.36 GPCCTRL Register (Offset = 80h) [reset = 0h]
8.9.2.37 GPCQSEL1 Register (Offset = 82h) [reset = 0h]
8.9.2.38 GPCQSEL2 Register (Offset = 84h) [reset = 0h]
8.9.2.39 GPCMUX1 Register (Offset = 86h) [reset = 0h]
8.9.2.40 GPCMUX2 Register (Offset = 88h) [reset = 0h]
8.9.2.41 GPCDIR Register (Offset = 8Ah) [reset = 0h]
8.9.2.42 GPCPUD Register (Offset = 8Ch) [reset = FFFFFFFFh]
8.9.2.43 GPCINV Register (Offset = 90h) [reset = 0h]
8.9.2.44 GPCODR Register (Offset = 92h) [reset = 0h]
8.9.2.45 GPCGMUX1 Register (Offset = A0h) [reset = 0h]
8.9.2.46 GPCGMUX2 Register (Offset = A2h) [reset = 0h]
8.9.2.47 GPCCSEL1 Register (Offset = A8h) [reset = 0h]
8.9.2.48 GPCCSEL2 Register (Offset = AAh) [reset = 0h]
8.9.2.49 GPCCSEL3 Register (Offset = ACh) [reset = 0h]
8.9.2.50 GPCCSEL4 Register (Offset = AEh) [reset = 0h]
8.9.2.51 GPCLOCK Register (Offset = BCh) [reset = 0h]
8.9.2.52 GPCCR Register (Offset = BEh) [reset = 0h]
8.9.2.53 GPDCTRL Register (Offset = C0h) [reset = 0h]
8.9.2.54 GPDQSEL1 Register (Offset = C2h) [reset = 0h]
8.9.2.55 GPDQSEL2 Register (Offset = C4h) [reset = 0h]
8.9.2.56 GPDMUX1 Register (Offset = C6h) [reset = 0h]
8.9.2.57 GPDMUX2 Register (Offset = C8h) [reset = 0h]
8.9.2.58 GPDDIR Register (Offset = CAh) [reset = 0h]
8.9.2.59 GPDPUD Register (Offset = CCh) [reset = FFFFFFFFh]
8.9.2.60 GPDINV Register (Offset = D0h) [reset = 0h]
8.9.2.61 GPDODR Register (Offset = D2h) [reset = 0h]
8.9.2.62 GPDGMUX1 Register (Offset = E0h) [reset = 0h]
8.9.2.63 GPDGMUX2 Register (Offset = E2h) [reset = 0h]
8.9.2.64 GPDCSEL1 Register (Offset = E8h) [reset = 0h]
8.9.2.65 GPDCSEL2 Register (Offset = EAh) [reset = 0h]
8.9.2.66 GPDCSEL3 Register (Offset = ECh) [reset = 0h]
8.9.2.67 GPDCSEL4 Register (Offset = EEh) [reset = 0h]
8.9.2.68 GPDLOCK Register (Offset = FCh) [reset = 0h]
8.9.2.69 GPDCR Register (Offset = FEh) [reset = 0h]
8.9.2.70 GPECTRL Register (Offset = 100h) [reset = 0h]
8.9.2.71 GPEQSEL1 Register (Offset = 102h) [reset = 0h]
8.9.2.72 GPEQSEL2 Register (Offset = 104h) [reset = 0h]
8.9.2.73 GPEMUX1 Register (Offset = 106h) [reset = 0h]
8.9.2.74 GPEMUX2 Register (Offset = 108h) [reset = 0h]
8.9.2.75 GPEDIR Register (Offset = 10Ah) [reset = 0h]
8.9.2.76 GPEPUD Register (Offset = 10Ch) [reset = FFFFFFFFh]
8.9.2.77 GPEINV Register (Offset = 110h) [reset = 0h]
8.9.2.78 GPEODR Register (Offset = 112h) [reset = 0h]
8.9.2.79 GPEGMUX1 Register (Offset = 120h) [reset = 0h]
8.9.2.80 GPEGMUX2 Register (Offset = 122h) [reset = 0h]
8.9.2.81 GPECSEL1 Register (Offset = 128h) [reset = 0h]
8.9.2.82 GPECSEL2 Register (Offset = 12Ah) [reset = 0h]
8.9.2.83 GPECSEL3 Register (Offset = 12Ch) [reset = 0h]
8.9.2.84 GPECSEL4 Register (Offset = 12Eh) [reset = 0h]
8.9.2.85 GPELOCK Register (Offset = 13Ch) [reset = 0h]
8.9.2.86 GPECR Register (Offset = 13Eh) [reset = 0h]
8.9.2.87 GPFCTRL Register (Offset = 140h) [reset = 0h]
8.9.2.88 GPFQSEL1 Register (Offset = 142h) [reset = 0h]
8.9.2.89 GPFMUX1 Register (Offset = 146h) [reset = 0h]
8.9.2.90 GPFDIR Register (Offset = 14Ah) [reset = 0h]
8.9.2.91 GPFPUD Register (Offset = 14Ch) [reset = FFFFFFFFh]
8.9.2.92 GPFINV Register (Offset = 150h) [reset = 0h]
8.9.2.93 GPFODR Register (Offset = 152h) [reset = 0h]
8.9.2.94 GPFGMUX1 Register (Offset = 160h) [reset = 0h]
8.9.2.95 GPFCSEL1 Register (Offset = 168h) [reset = 0h]
8.9.2.96 GPFCSEL2 Register (Offset = 16Ah) [reset = 0h]
8.9.2.97 GPFLOCK Register (Offset = 17Ch) [reset = 0h]
8.9.2.98 GPFCR Register (Offset = 17Eh) [reset = 0h]
8.9.3 GPIO_DATA_REGS Registers
8.9.3.1 GPADAT Register (Offset = 0h) [reset = 0h]
8.9.3.2 GPASET Register (Offset = 2h) [reset = 0h]
8.9.3.3 GPACLEAR Register (Offset = 4h) [reset = 0h]
8.9.3.4 GPATOGGLE Register (Offset = 6h) [reset = 0h]
8.9.3.5 GPBDAT Register (Offset = 8h) [reset = 0h]
8.9.3.6 GPBSET Register (Offset = Ah) [reset = 0h]
8.9.3.7 GPBCLEAR Register (Offset = Ch) [reset = 0h]
8.9.3.8 GPBTOGGLE Register (Offset = Eh) [reset = 0h]
8.9.3.9 GPCDAT Register (Offset = 10h) [reset = 0h]
8.9.3.10 GPCSET Register (Offset = 12h) [reset = 0h]
8.9.3.11 GPCCLEAR Register (Offset = 14h) [reset = 0h]
8.9.3.12 GPCTOGGLE Register (Offset = 16h) [reset = 0h]
8.9.3.13 GPDDAT Register (Offset = 18h) [reset = 0h]
8.9.3.14 GPDSET Register (Offset = 1Ah) [reset = 0h]
8.9.3.15 GPDCLEAR Register (Offset = 1Ch) [reset = 0h]
8.9.3.16 GPDTOGGLE Register (Offset = 1Eh) [reset = 0h]
8.9.3.17 GPEDAT Register (Offset = 20h) [reset = 0h]
8.9.3.18 GPESET Register (Offset = 22h) [reset = 0h]
8.9.3.19 GPECLEAR Register (Offset = 24h) [reset = 0h]
8.9.3.20 GPETOGGLE Register (Offset = 26h) [reset = 0h]
8.9.3.21 GPFDAT Register (Offset = 28h) [reset = 0h]
8.9.3.22 GPFSET Register (Offset = 2Ah) [reset = 0h]
8.9.3.23 GPFCLEAR Register (Offset = 2Ch) [reset = 0h]
8.9.3.24 GPFTOGGLE Register (Offset = 2Eh) [reset = 0h]
9 Crossbar (X-BAR)
9.1 GPIO Input X-BAR
9.2 ePWM and GPIO Output X-BAR
9.2.1 ePWM X-BAR
9.2.1.1 ePWM X-BAR Architecture
9.2.2 GPIO Output X-BAR
9.2.2.1 GPIO Output X-BAR Architecture
9.2.3 X-BAR Flags
9.3 XBAR Registers
9.3.1 XBAR Base Addresses
9.3.2 XBAR_REGS Registers
9.3.2.1 XBARFLG1 Register (Offset = 0h) [reset = 0h]
9.3.2.2 XBARFLG2 Register (Offset = 2h) [reset = 0h]
9.3.2.3 XBARFLG3 Register (Offset = 4h) [reset = 0h]
9.3.2.4 XBARCLR1 Register (Offset = 8h) [reset = 0h]
9.3.2.5 XBARCLR2 Register (Offset = Ah) [reset = 0h]
9.3.2.6 XBARCLR3 Register (Offset = Ch) [reset = 0h]
9.3.3 INPUT_XBAR_REGS Registers
9.3.3.1 INPUT1SELECT Register (Offset = 0h) [reset = 0h]
9.3.3.2 INPUT2SELECT Register (Offset = 1h) [reset = 0h]
9.3.3.3 INPUT3SELECT Register (Offset = 2h) [reset = 0h]
9.3.3.4 INPUT4SELECT Register (Offset = 3h) [reset = 0h]
9.3.3.5 INPUT5SELECT Register (Offset = 4h) [reset = 0h]
9.3.3.6 INPUT6SELECT Register (Offset = 5h) [reset = 0h]
9.3.3.7 INPUT7SELECT Register (Offset = 6h) [reset = 0h]
9.3.3.8 INPUT8SELECT Register (Offset = 7h) [reset = 0h]
9.3.3.9 INPUT9SELECT Register (Offset = 8h) [reset = 0h]
9.3.3.10 INPUT10SELECT Register (Offset = 9h) [reset = 0h]
9.3.3.11 INPUT11SELECT Register (Offset = Ah) [reset = 0h]
9.3.3.12 INPUT12SELECT Register (Offset = Bh) [reset = 0h]
9.3.3.13 INPUT13SELECT Register (Offset = Ch) [reset = 0h]
9.3.3.14 INPUT14SELECT Register (Offset = Dh) [reset = 0h]
9.3.3.15 INPUTSELECTLOCK Register (Offset = 1Eh) [reset = 0h]
9.3.4 OUTPUT_XBAR_REGS Registers
9.3.4.1 OUTPUT1MUX0TO15CFG Register (Offset = 0h) [reset = 0h]
9.3.4.2 OUTPUT1MUX16TO31CFG Register (Offset = 2h) [reset = 0h]
9.3.4.3 OUTPUT2MUX0TO15CFG Register (Offset = 4h) [reset = 0h]
9.3.4.4 OUTPUT2MUX16TO31CFG Register (Offset = 6h) [reset = 0h]
9.3.4.5 OUTPUT3MUX0TO15CFG Register (Offset = 8h) [reset = 0h]
9.3.4.6 OUTPUT3MUX16TO31CFG Register (Offset = Ah) [reset = 0h]
9.3.4.7 OUTPUT4MUX0TO15CFG Register (Offset = Ch) [reset = 0h]
9.3.4.8 OUTPUT4MUX16TO31CFG Register (Offset = Eh) [reset = 0h]
9.3.4.9 OUTPUT5MUX0TO15CFG Register (Offset = 10h) [reset = 0h]
9.3.4.10 OUTPUT5MUX16TO31CFG Register (Offset = 12h) [reset = 0h]
9.3.4.11 OUTPUT6MUX0TO15CFG Register (Offset = 14h) [reset = 0h]
9.3.4.12 OUTPUT6MUX16TO31CFG Register (Offset = 16h) [reset = 0h]
9.3.4.13 OUTPUT7MUX0TO15CFG Register (Offset = 18h) [reset = 0h]
9.3.4.14 OUTPUT7MUX16TO31CFG Register (Offset = 1Ah) [reset = 0h]
9.3.4.15 OUTPUT8MUX0TO15CFG Register (Offset = 1Ch) [reset = 0h]
9.3.4.16 OUTPUT8MUX16TO31CFG Register (Offset = 1Eh) [reset = 0h]
9.3.4.17 OUTPUT1MUXENABLE Register (Offset = 20h) [reset = 0h]
9.3.4.18 OUTPUT2MUXENABLE Register (Offset = 22h) [reset = 0h]
9.3.4.19 OUTPUT3MUXENABLE Register (Offset = 24h) [reset = 0h]
9.3.4.20 OUTPUT4MUXENABLE Register (Offset = 26h) [reset = 0h]
9.3.4.21 OUTPUT5MUXENABLE Register (Offset = 28h) [reset = 0h]
9.3.4.22 OUTPUT6MUXENABLE Register (Offset = 2Ah) [reset = 0h]
9.3.4.23 OUTPUT7MUXENABLE Register (Offset = 2Ch) [reset = 0h]
9.3.4.24 OUTPUT8MUXENABLE Register (Offset = 2Eh) [reset = 0h]
9.3.4.25 OUTPUTLATCH Register (Offset = 30h) [reset = 0h]
9.3.4.26 OUTPUTLATCHCLR Register (Offset = 32h) [reset = 0h]
9.3.4.27 OUTPUTLATCHFRC Register (Offset = 34h) [reset = 0h]
9.3.4.28 OUTPUTLATCHENABLE Register (Offset = 36h) [reset = 0h]
9.3.4.29 OUTPUTINV Register (Offset = 38h) [reset = 0h]
9.3.4.30 OUTPUTLOCK Register (Offset = 3Eh) [reset = 0h]
9.3.5 EPWM_XBAR_REGS Registers
9.3.5.1 TRIP4MUX0TO15CFG Register (Offset = 0h) [reset = 0h]
9.3.5.2 TRIP4MUX16TO31CFG Register (Offset = 2h) [reset = 0h]
9.3.5.3 TRIP5MUX0TO15CFG Register (Offset = 4h) [reset = 0h]
9.3.5.4 TRIP5MUX16TO31CFG Register (Offset = 6h) [reset = 0h]
9.3.5.5 TRIP7MUX0TO15CFG Register (Offset = 8h) [reset = 0h]
9.3.5.6 TRIP7MUX16TO31CFG Register (Offset = Ah) [reset = 0h]
9.3.5.7 TRIP8MUX0TO15CFG Register (Offset = Ch) [reset = 0h]
9.3.5.8 TRIP8MUX16TO31CFG Register (Offset = Eh) [reset = 0h]
9.3.5.9 TRIP9MUX0TO15CFG Register (Offset = 10h) [reset = 0h]
9.3.5.10 TRIP9MUX16TO31CFG Register (Offset = 12h) [reset = 0h]
9.3.5.11 TRIP10MUX0TO15CFG Register (Offset = 14h) [reset = 0h]
9.3.5.12 TRIP10MUX16TO31CFG Register (Offset = 16h) [reset = 0h]
9.3.5.13 TRIP11MUX0TO15CFG Register (Offset = 18h) [reset = 0h]
9.3.5.14 TRIP11MUX16TO31CFG Register (Offset = 1Ah) [reset = 0h]
9.3.5.15 TRIP12MUX0TO15CFG Register (Offset = 1Ch) [reset = 0h]
9.3.5.16 TRIP12MUX16TO31CFG Register (Offset = 1Eh) [reset = 0h]
9.3.5.17 TRIP4MUXENABLE Register (Offset = 20h) [reset = 0h]
9.3.5.18 TRIP5MUXENABLE Register (Offset = 22h) [reset = 0h]
9.3.5.19 TRIP7MUXENABLE Register (Offset = 24h) [reset = 0h]
9.3.5.20 TRIP8MUXENABLE Register (Offset = 26h) [reset = 0h]
9.3.5.21 TRIP9MUXENABLE Register (Offset = 28h) [reset = 0h]
9.3.5.22 TRIP10MUXENABLE Register (Offset = 2Ah) [reset = 0h]
9.3.5.23 TRIP11MUXENABLE Register (Offset = 2Ch) [reset = 0h]
9.3.5.24 TRIP12MUXENABLE Register (Offset = 2Eh) [reset = 0h]
9.3.5.25 TRIPOUTINV Register (Offset = 38h) [reset = 0h]
9.3.5.26 TRIPLOCK Register (Offset = 3Eh) [reset = 0h]
10 Analog Subsystem
10.1 Analog Subsystem
10.1.1 Features
10.1.2 Block Diagram
10.1.3 Lock Registers
10.2 Analog Subsystem Registers
10.2.1 Analog Subsystem Base Addresses
10.2.2 ANALOG_SUBSYS_REGS Registers
10.2.2.1 INTOSC1TRIM Register (Offset = 20h) [reset = 0h]
10.2.2.2 INTOSC2TRIM Register (Offset = 22h) [reset = 0h]
10.2.2.3 TSNSCTL Register (Offset = 26h) [reset = 0h]
10.2.2.4 LOCK Register (Offset = 2Eh) [reset = 0h]
10.2.2.5 ANAREFTRIMA Register (Offset = 36h) [reset = 0h]
10.2.2.6 ANAREFTRIMB Register (Offset = 38h) [reset = 0h]
10.2.2.7 ANAREFTRIMC Register (Offset = 3Ah) [reset = 0h]
10.2.2.8 ANAREFTRIMD Register (Offset = 3Ch) [reset = 0h]
11 Analog-to-Digital Converter (ADC)
11.1 Analog-to-Digital Converter (ADC)
11.1.1 Features
11.1.2 ADC Block Diagram
11.1.3 ADC Configurability
11.1.3.1 Clock Configuration
11.1.3.2 Resolution
11.1.3.3 Voltage Reference
11.1.3.3.1 External Reference Mode
11.1.3.4 Signal Mode
11.1.3.5 Expected Conversion Results
11.1.3.6 Interpreting Conversion Results
11.1.4 SOC Principle of Operation
11.1.4.1 SOC Configuration
11.1.4.2 Trigger Operation
11.1.4.3 ADC Acquisition (Sample and Hold) Window
11.1.4.4 ADC Input Models
11.1.4.5 Channel Selection
11.1.5 SOC Configuration Examples
11.1.5.1 Single Conversion from ePWM Trigger
11.1.5.2 Oversampled Conversion from ePWM Trigger
11.1.5.3 Multiple Conversions from CPU Timer Trigger
11.1.5.4 Software Triggering of SOCs
11.1.6 ADC Conversion Priority
11.1.7 Burst Mode
11.1.7.1 Burst Mode Example
11.1.7.2 Burst Mode Priority Example
11.1.8 EOC and Interrupt Operation
11.1.9 Post-Processing Blocks
11.1.9.1 PPB Offset Correction
11.1.9.2 PPB Error Calculation
11.1.9.3 PPB Limit Detection and Zero-Crossing Detection
11.1.9.4 PPB Sample Delay Capture
11.1.10 Opens/Shorts Detection Circuit (OSDETECT)
11.1.10.1 Implementation
11.1.10.2 Detecting an Open Input Pin
11.1.10.3 Detecting a Shorted Input Pin
11.1.11 Power-Up Sequence
11.1.12 ADC Calibration
11.1.12.1 ADC Zero Offset Calibration
11.2 ADC Timings
11.2.1 ADC Timing Diagrams
11.3 Additional Information
11.3.1 Ensuring Synchronous Operation
11.3.1.1 Basic Synchronous Operation
11.3.1.2 Synchronous Operation with Multiple Trigger Sources
11.3.1.3 Synchronous Operation with Uneven SOC Numbers
11.3.1.4 Synchronous Operation with Different Resolutions
11.3.1.5 Non-overlapping Conversions
11.3.2 Choosing an Acquisition Window Duration
11.3.3 Achieving Simultaneous Sampling
11.3.4 Designing an External Reference Circuit
11.3.5 Internal Temperature Sensor
11.4 ADC Registers
11.4.1 ADC Base Addresses
11.4.2 ADC_REGS Registers
11.4.2.1 ADCCTL1 Register (Offset = 0h) [reset = 0h]
11.4.2.2 ADCCTL2 Register (Offset = 1h) [reset = 0h]
11.4.2.3 ADCBURSTCTL Register (Offset = 2h) [reset = 0h]
11.4.2.4 ADCINTFLG Register (Offset = 3h) [reset = 0h]
11.4.2.5 ADCINTFLGCLR Register (Offset = 4h) [reset = 0h]
11.4.2.6 ADCINTOVF Register (Offset = 5h) [reset = 0h]
11.4.2.7 ADCINTOVFCLR Register (Offset = 6h) [reset = 0h]
11.4.2.8 ADCINTSEL1N2 Register (Offset = 7h) [reset = 0h]
11.4.2.9 ADCINTSEL3N4 Register (Offset = 8h) [reset = 0h]
11.4.2.10 ADCSOCPRICTL Register (Offset = 9h) [reset = 200h]
11.4.2.11 ADCINTSOCSEL1 Register (Offset = Ah) [reset = 0h]
11.4.2.12 ADCINTSOCSEL2 Register (Offset = Bh) [reset = 0h]
11.4.2.13 ADCSOCFLG1 Register (Offset = Ch) [reset = 0h]
11.4.2.14 ADCSOCFRC1 Register (Offset = Dh) [reset = 0h]
11.4.2.15 ADCSOCOVF1 Register (Offset = Eh) [reset = 0h]
11.4.2.16 ADCSOCOVFCLR1 Register (Offset = Fh) [reset = 0h]
11.4.2.17 ADCSOC0CTL Register (Offset = 10h) [reset = 0h]
11.4.2.18 ADCSOC1CTL Register (Offset = 12h) [reset = 0h]
11.4.2.19 ADCSOC2CTL Register (Offset = 14h) [reset = 0h]
11.4.2.20 ADCSOC3CTL Register (Offset = 16h) [reset = 0h]
11.4.2.21 ADCSOC4CTL Register (Offset = 18h) [reset = 0h]
11.4.2.22 ADCSOC5CTL Register (Offset = 1Ah) [reset = 0h]
11.4.2.23 ADCSOC6CTL Register (Offset = 1Ch) [reset = 0h]
11.4.2.24 ADCSOC7CTL Register (Offset = 1Eh) [reset = 0h]
11.4.2.25 ADCSOC8CTL Register (Offset = 20h) [reset = 0h]
11.4.2.26 ADCSOC9CTL Register (Offset = 22h) [reset = 0h]
11.4.2.27 ADCSOC10CTL Register (Offset = 24h) [reset = 0h]
11.4.2.28 ADCSOC11CTL Register (Offset = 26h) [reset = 0h]
11.4.2.29 ADCSOC12CTL Register (Offset = 28h) [reset = 0h]
11.4.2.30 ADCSOC13CTL Register (Offset = 2Ah) [reset = 0h]
11.4.2.31 ADCSOC14CTL Register (Offset = 2Ch) [reset = 0h]
11.4.2.32 ADCSOC15CTL Register (Offset = 2Eh) [reset = 0h]
11.4.2.33 ADCEVTSTAT Register (Offset = 30h) [reset = 0h]
11.4.2.34 ADCEVTCLR Register (Offset = 32h) [reset = 0h]
11.4.2.35 ADCEVTSEL Register (Offset = 34h) [reset = 0h]
11.4.2.36 ADCEVTINTSEL Register (Offset = 36h) [reset = 0h]
11.4.2.37 ADCOSDETECT Register (Offset = 38h) [reset = 0h]
11.4.2.38 ADCCOUNTER Register (Offset = 39h) [reset = 0h]
11.4.2.39 ADCREV Register (Offset = 3Ah) [reset = 4h]
11.4.2.40 ADCOFFTRIM Register (Offset = 3Bh) [reset = 0h]
11.4.2.41 ADCPPB1CONFIG Register (Offset = 40h) [reset = 0h]
11.4.2.42 ADCPPB1STAMP Register (Offset = 41h) [reset = 0h]
11.4.2.43 ADCPPB1OFFCAL Register (Offset = 42h) [reset = 0h]
11.4.2.44 ADCPPB1OFFREF Register (Offset = 43h) [reset = 0h]
11.4.2.45 ADCPPB1TRIPHI Register (Offset = 44h) [reset = 0h]
11.4.2.46 ADCPPB1TRIPLO Register (Offset = 46h) [reset = 0h]
11.4.2.47 ADCPPB2CONFIG Register (Offset = 48h) [reset = 0h]
11.4.2.48 ADCPPB2STAMP Register (Offset = 49h) [reset = 0h]
11.4.2.49 ADCPPB2OFFCAL Register (Offset = 4Ah) [reset = 0h]
11.4.2.50 ADCPPB2OFFREF Register (Offset = 4Bh) [reset = 0h]
11.4.2.51 ADCPPB2TRIPHI Register (Offset = 4Ch) [reset = 0h]
11.4.2.52 ADCPPB2TRIPLO Register (Offset = 4Eh) [reset = 0h]
11.4.2.53 ADCPPB3CONFIG Register (Offset = 50h) [reset = 0h]
11.4.2.54 ADCPPB3STAMP Register (Offset = 51h) [reset = 0h]
11.4.2.55 ADCPPB3OFFCAL Register (Offset = 52h) [reset = 0h]
11.4.2.56 ADCPPB3OFFREF Register (Offset = 53h) [reset = 0h]
11.4.2.57 ADCPPB3TRIPHI Register (Offset = 54h) [reset = 0h]
11.4.2.58 ADCPPB3TRIPLO Register (Offset = 56h) [reset = 0h]
11.4.2.59 ADCPPB4CONFIG Register (Offset = 58h) [reset = 0h]
11.4.2.60 ADCPPB4STAMP Register (Offset = 59h) [reset = 0h]
11.4.2.61 ADCPPB4OFFCAL Register (Offset = 5Ah) [reset = 0h]
11.4.2.62 ADCPPB4OFFREF Register (Offset = 5Bh) [reset = 0h]
11.4.2.63 ADCPPB4TRIPHI Register (Offset = 5Ch) [reset = 0h]
11.4.2.64 ADCPPB4TRIPLO Register (Offset = 5Eh) [reset = 0h]
11.4.2.65 ADCINLTRIM1 Register (Offset = 70h) [reset = X]
11.4.2.66 ADCINLTRIM2 Register (Offset = 72h) [reset = X]
11.4.2.67 ADCINLTRIM3 Register (Offset = 74h) [reset = X]
11.4.2.68 ADCINLTRIM4 Register (Offset = 76h) [reset = X]
11.4.2.69 ADCINLTRIM5 Register (Offset = 78h) [reset = X]
11.4.2.70 ADCINLTRIM6 Register (Offset = 7Ah) [reset = X]
11.4.3 ADC_RESULT_REGS Registers
11.4.3.1 ADCRESULT0 Register (Offset = 0h) [reset = 0h]
11.4.3.2 ADCRESULT1 Register (Offset = 1h) [reset = 0h]
11.4.3.3 ADCRESULT2 Register (Offset = 2h) [reset = 0h]
11.4.3.4 ADCRESULT3 Register (Offset = 3h) [reset = 0h]
11.4.3.5 ADCRESULT4 Register (Offset = 4h) [reset = 0h]
11.4.3.6 ADCRESULT5 Register (Offset = 5h) [reset = 0h]
11.4.3.7 ADCRESULT6 Register (Offset = 6h) [reset = 0h]
11.4.3.8 ADCRESULT7 Register (Offset = 7h) [reset = 0h]
11.4.3.9 ADCRESULT8 Register (Offset = 8h) [reset = 0h]
11.4.3.10 ADCRESULT9 Register (Offset = 9h) [reset = 0h]
11.4.3.11 ADCRESULT10 Register (Offset = Ah) [reset = 0h]
11.4.3.12 ADCRESULT11 Register (Offset = Bh) [reset = 0h]
11.4.3.13 ADCRESULT12 Register (Offset = Ch) [reset = 0h]
11.4.3.14 ADCRESULT13 Register (Offset = Dh) [reset = 0h]
11.4.3.15 ADCRESULT14 Register (Offset = Eh) [reset = 0h]
11.4.3.16 ADCRESULT15 Register (Offset = Fh) [reset = 0h]
11.4.3.17 ADCPPB1RESULT Register (Offset = 10h) [reset = 0h]
11.4.3.18 ADCPPB2RESULT Register (Offset = 12h) [reset = 0h]
11.4.3.19 ADCPPB3RESULT Register (Offset = 14h) [reset = 0h]
11.4.3.20 ADCPPB4RESULT Register (Offset = 16h) [reset = 0h]
12 Buffered Digital-to-Analog Converter (DAC)
12.1 Buffered Digital-to-Analog Converter (DAC) Overview
12.1.1 Features
12.1.2 Block Diagram
12.2 Using the DAC
12.2.1 Initialization Sequence
12.2.2 DAC Offset Adjustment
12.2.3 EPWMSYNCPER Signal
12.3 Lock Registers
12.4 DAC Registers
12.4.1 DAC Base Addresses
12.4.2 DAC_REGS Registers
12.4.2.1 DACREV Register (Offset = 0h) [reset = 0h]
12.4.2.2 DACCTL Register (Offset = 1h) [reset = 0h]
12.4.2.3 DACVALA Register (Offset = 2h) [reset = 0h]
12.4.2.4 DACVALS Register (Offset = 3h) [reset = 0h]
12.4.2.5 DACOUTEN Register (Offset = 4h) [reset = 0h]
12.4.2.6 DACLOCK Register (Offset = 5h) [reset = 0h]
12.4.2.7 DACTRIM Register (Offset = 6h) [reset = 0h]
13 Comparator Subsystem (CMPSS)
13.1 CMPSS Overview
13.1.1 Features
13.1.2 Block Diagram
13.2 Comparator
13.3 Reference DAC
13.4 Ramp Generator
13.4.1 Ramp Generator Overview
13.4.2 Ramp Generator Behavior
13.4.3 Ramp Generator Behavior at Corner Cases
13.5 Digital Filter
13.5.1 Filter Initialization Sequence
13.6 Using the CMPSS
13.6.1 LATCHCLR and EPWMSYNCPER Signals
13.6.2 Synchronizer, Digital Filter and Latch Delays
13.6.3 Calibrating the CMPSS
13.6.4 Enabling and Disabling the CMPSS Clock
13.7 CMPSS Registers
13.7.1 CMPSS Base Addresses
13.7.2 CMPSS_REGS Registers
13.7.2.1 COMPCTL Register (Offset = 0h) [reset = 0h]
13.7.2.2 COMPHYSCTL Register (Offset = 1h) [reset = 0h]
13.7.2.3 COMPSTS Register (Offset = 2h) [reset = 0h]
13.7.2.4 COMPSTSCLR Register (Offset = 3h) [reset = 0h]
13.7.2.5 COMPDACCTL Register (Offset = 4h) [reset = 0h]
13.7.2.6 DACHVALS Register (Offset = 6h) [reset = 0h]
13.7.2.7 DACHVALA Register (Offset = 7h) [reset = 0h]
13.7.2.8 RAMPMAXREFA Register (Offset = 8h) [reset = 0h]
13.7.2.9 RAMPMAXREFS Register (Offset = Ah) [reset = 0h]
13.7.2.10 RAMPDECVALA Register (Offset = Ch) [reset = 0h]
13.7.2.11 RAMPDECVALS Register (Offset = Eh) [reset = 0h]
13.7.2.12 RAMPSTS Register (Offset = 10h) [reset = 0h]
13.7.2.13 DACLVALS Register (Offset = 12h) [reset = 0h]
13.7.2.14 DACLVALA Register (Offset = 13h) [reset = 0h]
13.7.2.15 RAMPDLYA Register (Offset = 14h) [reset = 0h]
13.7.2.16 RAMPDLYS Register (Offset = 15h) [reset = 0h]
13.7.2.17 CTRIPLFILCTL Register (Offset = 16h) [reset = 0h]
13.7.2.18 CTRIPLFILCLKCTL Register (Offset = 17h) [reset = 0h]
13.7.2.19 CTRIPHFILCTL Register (Offset = 18h) [reset = 0h]
13.7.2.20 CTRIPHFILCLKCTL Register (Offset = 19h) [reset = 0h]
13.7.2.21 COMPLOCK Register (Offset = 1Ah) [reset = 0h]
14 Sigma Delta Filter Module (SDFM)
14.1 SDFM Module Overview
14.1.1 SDFM Features
14.1.2 Block Diagram
14.2 Configuring Device Pins
14.3 Input Control Unit
14.4 Sinc Filter
14.4.1 Data Rate and Latency of the Sinc Filter
14.5 Data (Primary) Filter Unit
14.5.1 32-bit or 16-bit Data Filter Output Representation
14.5.2 SDSYNC Event
14.6 Comparator (Secondary) Filter Unit
14.6.1 Higher threshold (HLT) comparator
14.6.2 Lower Threshold (LLT) comparator
14.7 Interrupt Unit
14.7.1 SDFM (SDINT) Interrupt sources
14.8 Register Descriptions
14.9 SDFM Registers
14.9.1 SDFM Base Addesses
14.9.2 SDFM_REGS Registers
14.9.2.1 SDIFLG Register (Offset = 0h) [reset = 0h]
14.9.2.2 SDIFLGCLR Register (Offset = 2h) [reset = 0h]
14.9.2.3 SDCTL Register (Offset = 4h) [reset = 0h]
14.9.2.4 SDMFILEN Register (Offset = 6h) [reset = 0h]
14.9.2.5 SDCTLPARM1 Register (Offset = 10h) [reset = 0h]
14.9.2.6 SDDFPARM1 Register (Offset = 11h) [reset = 0h]
14.9.2.7 SDDPARM1 Register (Offset = 12h) [reset = 0h]
14.9.2.8 SDCMPH1 Register (Offset = 13h) [reset = 0h]
14.9.2.9 SDCMPL1 Register (Offset = 14h) [reset = 0h]
14.9.2.10 SDCPARM1 Register (Offset = 15h) [reset = 0h]
14.9.2.11 SDDATA1 Register (Offset = 16h) [reset = 0h]
14.9.2.12 SDCTLPARM2 Register (Offset = 20h) [reset = 0h]
14.9.2.13 SDDFPARM2 Register (Offset = 21h) [reset = 0h]
14.9.2.14 SDDPARM2 Register (Offset = 22h) [reset = 0h]
14.9.2.15 SDCMPH2 Register (Offset = 23h) [reset = 0h]
14.9.2.16 SDCMPL2 Register (Offset = 24h) [reset = 0h]
14.9.2.17 SDCPARM2 Register (Offset = 25h) [reset = 0h]
14.9.2.18 SDDATA2 Register (Offset = 26h) [reset = 0h]
14.9.2.19 SDCTLPARM3 Register (Offset = 30h) [reset = 0h]
14.9.2.20 SDDFPARM3 Register (Offset = 31h) [reset = 0h]
14.9.2.21 SDDPARM3 Register (Offset = 32h) [reset = 0h]
14.9.2.22 SDCMPH3 Register (Offset = 33h) [reset = 0h]
14.9.2.23 SDCMPL3 Register (Offset = 34h) [reset = 0h]
14.9.2.24 SDCPARM3 Register (Offset = 35h) [reset = 0h]
14.9.2.25 SDDATA3 Register (Offset = 36h) [reset = 0h]
14.9.2.26 SDCTLPARM4 Register (Offset = 40h) [reset = 0h]
14.9.2.27 SDDFPARM4 Register (Offset = 41h) [reset = 0h]
14.9.2.28 SDDPARM4 Register (Offset = 42h) [reset = 0h]
14.9.2.29 SDCMPH4 Register (Offset = 43h) [reset = 0h]
14.9.2.30 SDCMPL4 Register (Offset = 44h) [reset = 0h]
14.9.2.31 SDCPARM4 Register (Offset = 45h) [reset = 0h]
14.9.2.32 SDDATA4 Register (Offset = 46h) [reset = 0h]
15 Enhanced Pulse Width Modulator (ePWM)
15.1 Introduction
15.1.1 Submodule Overview
15.2 Configuring Device Pins
15.3 ePWM Modules Overview
15.4 Time-Base (TB) Submodule
15.4.1 Purpose of the Time-Base Submodule
15.4.2 Controlling and Monitoring the Time-Base Submodule
15.4.3 Calculating PWM Period and Frequency
15.4.3.1 Time-Base Period Shadow Register
15.4.3.2 Time-Base Clock Synchronization
15.4.3.3 Time-Base Counter Synchronization
15.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
15.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
15.4.6 Time-Base Counter Modes and Timing Waveforms
15.4.7 Global Load
15.4.7.1 Global Load Pulse Pre-Scalar
15.4.7.2 One-Shot Load Mode
15.5 Counter-Compare (CC) Submodule
15.5.1 Purpose of the Counter-Compare Submodule
15.5.2 Controlling and Monitoring the Counter-Compare Submodule
15.5.3 Operational Highlights for the Counter-Compare Submodule
15.5.4 Count Mode Timing Waveforms
15.6 Action-Qualifier (AQ) Submodule
15.6.1 Purpose of the Action-Qualifier Submodule
15.6.2 Action-Qualifier Submodule Control and Status Register Definitions
15.6.3 Action-Qualifier Event Priority
15.6.4 AQCTLA and AQCTLB Shadow Mode Operations
15.6.5 Waveforms for Common Configurations
15.7 Dead-Band Generator (DB) Submodule
15.7.1 Purpose of the Dead-Band Submodule
15.7.2 Dead-band Submodule Additional Operating Modes
15.7.3 Operational Highlights for the Dead-Band Submodule
15.8 PWM Chopper (PC) Submodule
15.8.1 Purpose of the PWM Chopper Submodule
15.8.2 Operational Highlights for the PWM Chopper Submodule
15.8.3 Waveforms
15.8.3.1 One-Shot Pulse
15.8.3.2 Duty Cycle Control
15.9 Trip-Zone (TZ) Submodule
15.9.1 Purpose of the Trip-Zone Submodule
15.9.2 Operational Highlights for the Trip-Zone Submodule
15.9.3 Generating Trip Event Interrupts
15.10 Event-Trigger (ET) Submodule
15.10.1 Operational Overview of the ePWM Type 4 Event-Trigger Submodule
15.11 Digital Compare (DC) Submodule
15.11.1 Purpose of the Digital Compare Submodule
15.11.2 Enhanced Trip Action Using CMPSS
15.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
15.11.4 Operation Highlights of the Digital Compare Submodule
15.11.4.1 Digital Compare Events
15.11.4.2 Event Filtering
15.11.4.3 Valley Switching
15.12 ePWM X-BAR
15.13 Applications to Power Topologies
15.13.1 Overview of Multiple Modules
15.13.2 Key Configuration Capabilities
15.13.3 Controlling Multiple Buck Converters With Independent Frequencies
15.13.4 Controlling Multiple Buck Converters With Same Frequencies
15.13.5 Controlling Multiple Half H-Bridge (HHB) Converters
15.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
15.13.7 Practical Applications Using Phase Control Between PWM Modules
15.13.8 Controlling a 3-Phase Interleaved DC/DC Converter
15.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
15.13.10 Controlling a Peak Current Mode Controlled Buck Module
15.13.11 Controlling H-Bridge LLC Resonant Converter
15.14 High-Resolution Pulse Width Modulator (HRPWM)
15.14.1 Operational Description of HRPWM
15.14.1.1 Controlling the HRPWM Capabilities
15.14.1.2 HRPWM Source Clock
15.14.1.3 Configuring the HRPWM
15.14.1.4 Configuring Hi-Res in Deadband Rising Edge and Falling Edge Delay
15.14.1.5 Principle of Operation
15.14.1.5.1 Edge Positioning
15.14.1.5.2 Scaling Considerations
15.14.1.5.3 Duty Cycle Range Limitation
15.14.1.5.4 High Resolution Period
15.14.1.6 Deadband High Resolution Operation
15.14.1.7 Scale Factor Optimizing Software (SFO)
15.14.1.8 HRPWM Examples Using Optimized Assembly Code.
15.14.1.8.1 Implementing a Simple Buck Converter
15.14.1.8.2 Implementing a DAC function Using an R+C Reconstruction Filter
15.14.2 Appendix A: SFO Library Software - SFO_TI_Build_V7.lib
15.14.2.1 Scale Factor Optimizer Function - int SFO()
15.14.2.2 Software Usage
15.15 ePWM Registers
15.15.1 ePWM Base Addresses
15.15.2 EPWM_REGS Registers
15.15.2.1 TBCTL Register (Offset = 0h) [reset = 83h]
15.15.2.2 TBCTL2 Register (Offset = 1h) [reset = 0h]
15.15.2.3 TBCTR Register (Offset = 4h) [reset = 0h]
15.15.2.4 TBSTS Register (Offset = 5h) [reset = 1h]
15.15.2.5 CMPCTL Register (Offset = 8h) [reset = 0h]
15.15.2.6 CMPCTL2 Register (Offset = 9h) [reset = 0h]
15.15.2.7 DBCTL Register (Offset = Ch) [reset = 0h]
15.15.2.8 DBCTL2 Register (Offset = Dh) [reset = 0h]
15.15.2.9 AQCTL Register (Offset = 10h) [reset = 0h]
15.15.2.10 AQTSRCSEL Register (Offset = 11h) [reset = 0h]
15.15.2.11 PCCTL Register (Offset = 14h) [reset = 0h]
15.15.2.12 VCAPCTL Register (Offset = 18h) [reset = 0h]
15.15.2.13 VCNTCFG Register (Offset = 19h) [reset = 0h]
15.15.2.14 HRCNFG Register (Offset = 20h) [reset = 0h]
15.15.2.15 HRPWR Register (Offset = 21h) [reset = 0h]
15.15.2.16 HRMSTEP Register (Offset = 26h) [reset = 0h]
15.15.2.17 HRCNFG2 Register (Offset = 27h) [reset = 0h]
15.15.2.18 HRPCTL Register (Offset = 2Dh) [reset = 0h]
15.15.2.19 TRREM Register (Offset = 2Eh) [reset = 0h]
15.15.2.20 GLDCTL Register (Offset = 34h) [reset = 0h]
15.15.2.21 GLDCFG Register (Offset = 35h) [reset = 0h]
15.15.2.22 EPWMXLINK Register (Offset = 38h) [reset = X]
15.15.2.23 AQCTLA Register (Offset = 40h) [reset = 0h]
15.15.2.24 AQCTLA2 Register (Offset = 41h) [reset = 0h]
15.15.2.25 AQCTLB Register (Offset = 42h) [reset = 0h]
15.15.2.26 AQCTLB2 Register (Offset = 43h) [reset = 0h]
15.15.2.27 AQSFRC Register (Offset = 47h) [reset = 0h]
15.15.2.28 AQCSFRC Register (Offset = 49h) [reset = 0h]
15.15.2.29 DBREDHR Register (Offset = 50h) [reset = 0h]
15.15.2.30 DBRED Register (Offset = 51h) [reset = 0h]
15.15.2.31 DBFEDHR Register (Offset = 52h) [reset = 0h]
15.15.2.32 DBFED Register (Offset = 53h) [reset = 0h]
15.15.2.33 TBPHS Register (Offset = 60h) [reset = 0h]
15.15.2.34 TBPRDHR Register (Offset = 62h) [reset = 0h]
15.15.2.35 TBPRD Register (Offset = 63h) [reset = 0h]
15.15.2.36 CMPA Register (Offset = 6Ah) [reset = 0h]
15.15.2.37 CMPB Register (Offset = 6Ch) [reset = 0h]
15.15.2.38 CMPC Register (Offset = 6Fh) [reset = 0h]
15.15.2.39 CMPD Register (Offset = 71h) [reset = 0h]
15.15.2.40 GLDCTL2 Register (Offset = 74h) [reset = 0h]
15.15.2.41 SWVDELVAL Register (Offset = 77h) [reset = 0h]
15.15.2.42 TZSEL Register (Offset = 80h) [reset = 0h]
15.15.2.43 TZDCSEL Register (Offset = 82h) [reset = 0h]
15.15.2.44 TZCTL Register (Offset = 84h) [reset = 0h]
15.15.2.45 TZCTL2 Register (Offset = 85h) [reset = 0h]
15.15.2.46 TZCTLDCA Register (Offset = 86h) [reset = 0h]
15.15.2.47 TZCTLDCB Register (Offset = 87h) [reset = 0h]
15.15.2.48 TZEINT Register (Offset = 8Dh) [reset = 0h]
15.15.2.49 TZFLG Register (Offset = 93h) [reset = 0h]
15.15.2.50 TZCBCFLG Register (Offset = 94h) [reset = 0h]
15.15.2.51 TZOSTFLG Register (Offset = 95h) [reset = 0h]
15.15.2.52 TZCLR Register (Offset = 97h) [reset = 0h]
15.15.2.53 TZCBCCLR Register (Offset = 98h) [reset = 0h]
15.15.2.54 TZOSTCLR Register (Offset = 99h) [reset = 0h]
15.15.2.55 TZFRC Register (Offset = 9Bh) [reset = 0h]
15.15.2.56 ETSEL Register (Offset = A4h) [reset = 0h]
15.15.2.57 ETPS Register (Offset = A6h) [reset = 0h]
15.15.2.58 ETFLG Register (Offset = A8h) [reset = 0h]
15.15.2.59 ETCLR Register (Offset = AAh) [reset = 0h]
15.15.2.60 ETFRC Register (Offset = ACh) [reset = 0h]
15.15.2.61 ETINTPS Register (Offset = AEh) [reset = 0h]
15.15.2.62 ETSOCPS Register (Offset = B0h) [reset = 0h]
15.15.2.63 ETCNTINITCTL Register (Offset = B2h) [reset = 0h]
15.15.2.64 ETCNTINIT Register (Offset = B4h) [reset = 0h]
15.15.2.65 DCTRIPSEL Register (Offset = C0h) [reset = 0h]
15.15.2.66 DCACTL Register (Offset = C3h) [reset = 0h]
15.15.2.67 DCBCTL Register (Offset = C4h) [reset = 0h]
15.15.2.68 DCFCTL Register (Offset = C7h) [reset = 0h]
15.15.2.69 DCCAPCTL Register (Offset = C8h) [reset = 0h]
15.15.2.70 DCFOFFSET Register (Offset = C9h) [reset = 0h]
15.15.2.71 DCFOFFSETCNT Register (Offset = CAh) [reset = 0h]
15.15.2.72 DCFWINDOW Register (Offset = CBh) [reset = 0h]
15.15.2.73 DCFWINDOWCNT Register (Offset = CCh) [reset = 0h]
15.15.2.74 DCCAP Register (Offset = CFh) [reset = 0h]
15.15.2.75 DCAHTRIPSEL Register (Offset = D2h) [reset = 0h]
15.15.2.76 DCALTRIPSEL Register (Offset = D3h) [reset = 0h]
15.15.2.77 DCBHTRIPSEL Register (Offset = D4h) [reset = 0h]
15.15.2.78 DCBLTRIPSEL Register (Offset = D5h) [reset = 0h]
15.15.2.79 HWVDELVAL Register (Offset = FDh) [reset = 0h]
15.15.2.80 VCNTVAL Register (Offset = FEh) [reset = 0h]
15.15.3 SYNC_SOC_REGS Registers
15.15.3.1 SYNCSELECT Register (Offset = 0h) [reset = 0h]
15.15.3.2 ADCSOCOUTSELECT Register (Offset = 2h) [reset = 0h]
15.15.3.3 SYNCSOCLOCK Register (Offset = 4h) [reset = 0h]
16 Enhanced Capture (eCAP)
16.1 Introduction
16.2 Description
16.3 Configuring Device Pins for the eCAP
16.4 Capture and APWM Operating Mode
16.5 Capture Mode Description
16.5.1 Event Prescaler
16.5.2 Edge Polarity Select and Qualifier
16.5.3 Continuous/One-Shot Control
16.5.4 32-Bit Counter and Phase Control
16.5.5 CAP1-CAP4 Registers
16.5.6 eCAP Synchronization
16.5.6.1 Example 1 - Using SWSYNC with ECAP Module
16.5.7 Interrupt Control
16.5.8 Shadow Load and Lockout Control
16.5.9 APWM Mode Operation
16.6 Application of the eCAP Module
16.6.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger
16.6.1.1 Code snippet for CAP mode Absolute Time, Rising Edge Trigger
16.6.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger
16.6.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Triggers
16.6.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger
16.6.3.1 Code Snippet for CAP mode Delta Time, Rising Edge Trigger
16.6.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger
16.6.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
16.7 Application of the APWM Mode
16.7.1 Example 1 - Simple PWM Generation (Independent Channel/s)
16.8 eCAP Registers
16.8.1 eCAP Base Addresses
16.8.2 ECAP_REGS Registers
16.8.2.1 TSCTR Register (Offset = 0h) [reset = 0h]
16.8.2.2 CTRPHS Register (Offset = 2h) [reset = 0h]
16.8.2.3 CAP1 Register (Offset = 4h) [reset = 0h]
16.8.2.4 CAP2 Register (Offset = 6h) [reset = 0h]
16.8.2.5 CAP3 Register (Offset = 8h) [reset = 0h]
16.8.2.6 CAP4 Register (Offset = Ah) [reset = 0h]
16.8.2.7 ECCTL1 Register (Offset = 14h) [reset = 0h]
16.8.2.8 ECCTL2 Register (Offset = 15h) [reset = 6h]
16.8.2.9 ECEINT Register (Offset = 16h) [reset = 0h]
16.8.2.10 ECFLG Register (Offset = 17h) [reset = 0h]
16.8.2.11 ECCLR Register (Offset = 18h) [reset = 0h]
16.8.2.12 ECFRC Register (Offset = 19h) [reset = 0h]
17 Enhanced Quadrature Encoder Pulse (eQEP)
17.1 Introduction
17.2 Configuring Device Pins
17.3 Description
17.3.1 EQEP Inputs
17.3.2 Functional Description
17.3.3 eQEP Memory Map
17.4 Quadrature Decoder Unit (QDU)
17.4.1 Position Counter Input Modes
17.4.1.1 Quadrature Count Mode
17.4.1.2 Direction-Count Mode
17.4.1.3 Up-Count Mode
17.4.1.4 Down-Count Mode
17.4.2 eQEP Input Polarity Selection
17.4.3 Position-Compare Sync Output
17.5 Position Counter and Control Unit (PCCU)
17.5.1 Position Counter Operating Modes
17.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
17.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
17.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
17.5.1.4 Position Counter Reset on Unit Time out Event (QEPCTL[PCRM] = 11)
17.5.2 Position Counter Latch
17.5.2.1 Index Event Latch
17.5.2.2 Strobe Event Latch
17.5.3 Position Counter Initialization
17.5.4 eQEP Position-compare Unit
17.6 eQEP Edge Capture Unit
17.7 eQEP Watchdog
17.8 Unit Timer Base
17.9 eQEP Interrupt Structure
17.10 eQEP Registers
17.10.1 eQEP Base Addresses
17.10.2 EQEP_REGS Registers
17.10.2.1 QPOSCNT Register (Offset = 0h) [reset = 0h]
17.10.2.2 QPOSINIT Register (Offset = 2h) [reset = 0h]
17.10.2.3 QPOSMAX Register (Offset = 4h) [reset = 0h]
17.10.2.4 QPOSCMP Register (Offset = 6h) [reset = 0h]
17.10.2.5 QPOSILAT Register (Offset = 8h) [reset = 0h]
17.10.2.6 QPOSSLAT Register (Offset = Ah) [reset = 0h]
17.10.2.7 QPOSLAT Register (Offset = Ch) [reset = 0h]
17.10.2.8 QUTMR Register (Offset = Eh) [reset = 0h]
17.10.2.9 QUPRD Register (Offset = 10h) [reset = 0h]
17.10.2.10 QWDTMR Register (Offset = 12h) [reset = 0h]
17.10.2.11 QWDPRD Register (Offset = 13h) [reset = 0h]
17.10.2.12 QDECCTL Register (Offset = 14h) [reset = 0h]
17.10.2.13 QEPCTL Register (Offset = 15h) [reset = 0h]
17.10.2.14 QCAPCTL Register (Offset = 16h) [reset = 0h]
17.10.2.15 QPOSCTL Register (Offset = 17h) [reset = 0h]
17.10.2.16 QEINT Register (Offset = 18h) [reset = 0h]
17.10.2.17 QFLG Register (Offset = 19h) [reset = 0h]
17.10.2.18 QCLR Register (Offset = 1Ah) [reset = 0h]
17.10.2.19 QFRC Register (Offset = 1Bh) [reset = 0h]
17.10.2.20 QEPSTS Register (Offset = 1Ch) [reset = 0h]
17.10.2.21 QCTMR Register (Offset = 1Dh) [reset = 0h]
17.10.2.22 QCPRD Register (Offset = 1Eh) [reset = 0h]
17.10.2.23 QCTMRLAT Register (Offset = 1Fh) [reset = 0h]
17.10.2.24 QCPRDLAT Register (Offset = 20h) [reset = 0h]
18 Serial Peripheral Interface (SPI)
18.1 SPI Module Overview
18.1.1 Features
18.1.2 SPI CPU Interface
18.2 System-Level Integration
18.2.1 SPI Module Signals
18.2.2 Configuring Device Pins
18.2.2.1 GPIOs Required for High-Speed Mode
18.2.3 SPI Interrupts
18.2.4 DMA Support
18.3 SPI Operation
18.3.1 Introduction to Operation
18.3.2 Master Mode
18.3.3 Slave Mode
18.3.4 Data Format
18.3.5 Baud Rate Selection
18.3.6 SPI Clocking Schemes
18.3.7 SPI FIFO Description
18.3.8 SPI DMA Transfers
18.3.8.1 Transmitting Data Using SPI with DMA
18.3.8.2 Receiving Data Using SPI with DMA
18.3.9 SPI High-Speed Mode
18.3.10 SPI 3-Wire Mode Description
18.4 Programming Procedure
18.4.1 Initialization Upon Reset
18.4.2 Configuring the SPI
18.4.3 Configuring the SPI for High-Speed Mode
18.4.4 Data Transfer Example
18.4.5 SPI 3-Wire Mode Code Examples
18.4.6 SPI STEINV Bit in Digital Audio Transfers
18.5 SPI Registers
18.5.1 SPI Base Addresses
18.5.2 SPI_REGS Registers
18.5.2.1 SPICCR Register (Offset = 0h) [reset = 0h]
18.5.2.2 SPICTL Register (Offset = 1h) [reset = 0h]
18.5.2.3 SPISTS Register (Offset = 2h) [reset = 0h]
18.5.2.4 SPIBRR Register (Offset = 4h) [reset = 0h]
18.5.2.5 SPIRXEMU Register (Offset = 6h) [reset = 0h]
18.5.2.6 SPIRXBUF Register (Offset = 7h) [reset = 0h]
18.5.2.7 SPITXBUF Register (Offset = 8h) [reset = 0h]
18.5.2.8 SPIDAT Register (Offset = 9h) [reset = 0h]
18.5.2.9 SPIFFTX Register (Offset = Ah) [reset = A000h]
18.5.2.10 SPIFFRX Register (Offset = Bh) [reset = 201Fh]
18.5.2.11 SPIFFCT Register (Offset = Ch) [reset = 0h]
18.5.2.12 SPIPRI Register (Offset = Fh) [reset = 0h]
19 Serial Communications Interface (SCI)
19.1 Enhanced SCI Module Overview
19.2 Architecture
19.3 SCI Module Signal Summary
19.4 Configuring Device Pins
19.5 Multiprocessor and Asynchronous Communication Modes
19.6 SCI Programmable Data Format
19.7 SCI Multiprocessor Communication
19.7.1 Recognizing the Address Byte
19.7.2 Controlling the SCI TX and RX Features
19.7.3 Receipt Sequence
19.8 Idle-Line Multiprocessor Mode
19.8.1 Idle-Line Mode Steps
19.8.2 Block Start Signal
19.8.3 Wake-UP Temporary (WUT) Flag
19.8.3.1 Sending a Block Start Signal
19.8.4 Receiver Operation
19.9 Address-Bit Multiprocessor Mode
19.9.1 Sending an Address
19.10 SCI Communication Format
19.10.1 Receiver Signals in Communication Modes
19.10.2 Transmitter Signals in Communication Modes
19.11 SCI Port Interrupts
19.12 SCI Baud Rate Calculations
19.13 SCI Enhanced Features
19.13.1 SCI FIFO Description
19.13.2 SCI Auto-Baud
19.13.3 Autobaud-Detect Sequence
19.14 SCI Registers
19.14.1 SCI Base Addresses
19.14.2 SCI_REGS Registers
19.14.2.1 SCICCR Register (Offset = 0h) [reset = 0h]
19.14.2.2 SCICTL1 Register (Offset = 1h) [reset = 0h]
19.14.2.3 SCIHBAUD Register (Offset = 2h) [reset = 0h]
19.14.2.4 SCILBAUD Register (Offset = 3h) [reset = 0h]
19.14.2.5 SCICTL2 Register (Offset = 4h) [reset = C0h]
19.14.2.6 SCIRXST Register (Offset = 5h) [reset = 0h]
19.14.2.7 SCIRXEMU Register (Offset = 6h) [reset = 0h]
19.14.2.8 SCIRXBUF Register (Offset = 7h) [reset = 0h]
19.14.2.9 SCITXBUF Register (Offset = 9h) [reset = 0h]
19.14.2.10 SCIFFTX Register (Offset = Ah) [reset = A000h]
19.14.2.11 SCIFFRX Register (Offset = Bh) [reset = 201Fh]
19.14.2.12 SCIFFCT Register (Offset = Ch) [reset = 0h]
19.14.2.13 SCIPRI Register (Offset = Fh) [reset = 0h]
20 Inter-Integrated Circuit Module (I2C)
20.1 Introduction to the I2C Module
20.1.1 Features
20.1.2 Features Not Supported
20.1.3 Functional Overview
20.1.4 Clock Generation
20.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
20.1.5.1 Formula for the Master Clock Period
20.2 Configuring Device Pins
20.3 I2C Module Operational Details
20.3.1 Input and Output Voltage Levels
20.3.2 Data Validity
20.3.3 Operating Modes
20.3.4 I2C Module START and STOP Conditions
20.3.5 Serial Data Formats
20.3.5.1 7-Bit Addressing Format
20.3.5.2 10-Bit Addressing Format
20.3.5.3 Free Data Format
20.3.5.4 Using a Repeated START Condition
20.3.6 NACK Bit Generation
20.3.7 Clock Synchronization
20.3.8 Arbitration
20.3.9 Digital Loopback Mode
20.4 Interrupt Requests Generated by the I2C Module
20.4.1 Basic I2C Interrupt Requests
20.4.2 I2C FIFO Interrupts
20.5 Resetting or Disabling the I2C Module
20.6 I2C Registers
20.6.1 I2C Base Addresses
20.6.2 I2C_REGS Registers
20.6.2.1 I2COAR Register (Offset = 0h) [reset = 0h]
20.6.2.2 I2CIER Register (Offset = 1h) [reset = 0h]
20.6.2.3 I2CSTR Register (Offset = 2h) [reset = 0h]
20.6.2.4 I2CCLKL Register (Offset = 3h) [reset = 0h]
20.6.2.5 I2CCLKH Register (Offset = 4h) [reset = 0h]
20.6.2.6 I2CCNT Register (Offset = 5h) [reset = 0h]
20.6.2.7 I2CDRR Register (Offset = 6h) [reset = 0h]
20.6.2.8 I2CSAR Register (Offset = 7h) [reset = 3FFh]
20.6.2.9 I2CDXR Register (Offset = 8h) [reset = 0h]
20.6.2.10 I2CMDR Register (Offset = 9h) [reset = 0h]
20.6.2.11 I2CISRC Register (Offset = Ah) [reset = 0h]
20.6.2.12 I2CEMDR Register (Offset = Bh) [reset = 0h]
20.6.2.13 I2CPSC Register (Offset = Ch) [reset = 0h]
20.6.2.14 I2CFFTX Register (Offset = 20h) [reset = 0h]
20.6.2.15 I2CFFRX Register (Offset = 21h) [reset = 0h]
21 Multichannel Buffered Serial Port (McBSP)
21.1 Overview
21.1.1 Features of the McBSPs
21.1.2 McBSP Pins/Signals
21.1.2.1 McBSP Generic Block Diagram
21.2 Configuring Device Pins
21.3 McBSP Operation
21.3.1 Data Transfer Process of McBSPs
21.3.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits
21.3.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits
21.3.2 Companding (Compressing and Expanding) Data
21.3.2.1 Companding Formats
21.3.2.2 Capability to Compand Internal Data
21.3.2.3 Reversing Bit Order: Option to Transfer LSB First
21.3.3 Clocking and Framing Data
21.3.3.1 Clocking
21.3.3.2 Serial Words
21.3.3.3 Frames and Frame Synchronization
21.3.3.4 Generating Transmit and Receive Interrupts
21.3.3.4.1 Detecting Frame-Synchronization Pulses, Even in Reset State
21.3.3.5 Ignoring Frame-Synchronization Pulses
21.3.3.6 Frame Frequency
21.3.3.7 Maximum Frame Frequency
21.3.4 Frame Phases
21.3.4.1 Number of Phases, Words, and Bits Per Frame
21.3.4.2 Single-Phase Frame Example
21.3.4.3 Dual-Phase Frame Example
21.3.4.4 Implementing the AC97 Standard With a Dual-Phase Frame
21.3.5 McBSP Reception
21.3.6 McBSP Transmission
21.3.7 Interrupts and DMA Events Generated by a McBSP
21.4 McBSP Sample Rate Generator
21.4.1 Block Diagram
21.4.1.1 Clock Generation in the Sample Rate Generator
21.4.1.2 Choosing an Input Clock
21.4.1.3 Choosing a Polarity for the Input Clock
21.4.1.4 Choosing a Frequency for the Output Clock (CLKG)
21.4.1.4.1 CLKG Frequency
21.4.1.5 Keeping CLKG Synchronized to External MCLKR
21.4.2 Frame Synchronization Generation in the Sample Rate Generator
21.4.2.1 Choosing the Width of the Frame-Synchronization Pulse on FSG
21.4.2.2 Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
21.4.2.3 Keeping FSG Synchronized to an External Clock
21.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock
21.4.3.1 Operating the Transmitter Synchronously with the Receiver
21.4.3.2 Synchronization Examples
21.4.4 Reset and Initialization Procedure for the Sample Rate Generator
21.5 McBSP Exception/Error Conditions
21.5.1 Types of Errors
21.5.2 Overrun in the Receiver
21.5.2.1 Example of Overrun Condition
21.5.2.2 Example of Preventing Overrun Condition
21.5.3 Unexpected Receive Frame-Synchronization Pulse
21.5.3.1 Possible Responses to Receive Frame-Synchronization Pulses
21.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
21.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
21.5.4 Overwrite in the Transmitter
21.5.4.1 Example of Overwrite Condition
21.5.4.2 Preventing Overwrites
21.5.5 Underflow in the Transmitter
21.5.5.1 Example of the Underflow Condition
21.5.5.2 Example of Preventing Underflow Condition
21.5.6 Unexpected Transmit Frame-Synchronization Pulse
21.5.6.1 Possible Responses to Transmit Frame-Synchronization Pulses
21.5.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse
21.5.6.3 Preventing Unexpected Transmit Frame-Synchronization Pulses
21.6 Multichannel Selection Modes
21.6.1 Channels, Blocks, and Partitions
21.6.2 Multichannel Selection
21.6.3 Configuring a Frame for Multichannel Selection
21.6.4 Using Two Partitions
21.6.4.1 Assigning Blocks to Partitions A and B
21.6.4.2 Reassigning Blocks During Reception/Transmission
21.6.5 Using Eight Partitions
21.6.6 Receive Multichannel Selection Mode
21.6.7 Transmit Multichannel Selection Modes
21.6.7.1 Disabling/Enabling Versus Masking/Unmasking
21.6.7.2 Activity on McBSP Pins for Different Values of XMCM
21.6.8 Using Interrupts Between Block Transfers
21.7 SPI Operation Using the Clock Stop Mode
21.7.1 SPI Protocol
21.7.2 Clock Stop Mode
21.7.3 Enable and Configure the Clock Stop Mode
21.7.4 Clock Stop Mode Timing Diagrams
21.7.5 Procedure for Configuring a McBSP for SPI Operation
21.7.6 McBSP as the SPI Master
21.7.7 McBSP as an SPI Slave
21.8 Receiver Configuration
21.8.1 Programming the McBSP Registers for the Desired Receiver Operation
21.8.2 Resetting and Enabling the Receiver
21.8.2.1 Reset Considerations
21.8.3 Set the Receiver Pins to Operate as McBSP Pins
21.8.4 Digital Loopback Mode
21.8.4.1 Digital Loopback Mode
21.8.5 Clock Stop Mode
21.8.5.1 Clock Stop Mode
21.8.6 Receive Multichannel Selection Mode
21.8.7 Receive Frame Phases
21.8.8 Receive Word Length(s)
21.8.8.1 Word Length Bits
21.8.9 Receive Frame Length
21.8.9.1 Selected Frame Length
21.8.10 Receive Frame-Synchronization Ignore Function
21.8.10.1 Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
21.8.10.2 Examples of Effects of RFIG
21.8.11 Receive Companding Mode
21.8.11.1 Companding
21.8.11.2 Format of Expanded Data
21.8.11.3 Companding Internal Data
21.8.11.4 Option to Receive LSB First
21.8.12 Receive Data Delay
21.8.12.1 Data Delay
21.8.12.2 0-Bit Data Delay
21.8.12.3 2-Bit Data Delay
21.8.13 Receive Sign-Extension and Justification Mode
21.8.13.1 Sign-Extension and the Justification
21.8.14 Receive Interrupt Mode
21.8.15 Receive Frame-Synchronization Mode
21.8.15.1 Receive Frame-Synchronization Modes
21.8.16 Receive Frame-Synchronization Polarity
21.8.16.1 Frame-Synchronization Pulses, Clock Signals, and Their Polarities
21.8.16.2 Frame-Synchronization Period and the Frame-Synchronization Pulse Width
21.8.17 Receive Clock Mode
21.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
21.8.18 Receive Clock Polarity
21.8.18.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
21.8.19 SRG Clock Divide-Down Value
21.8.19.1 Sample Rate Generator Clock Divider
21.8.20 SRG Clock Synchronization Mode
21.8.21 SRG Clock Mode (Choose an Input Clock)
21.8.21.1 SRG Clock Mode
21.8.22 SRG Input Clock Polarity
21.8.22.1 Using CLKXP/CLKRP to Choose an Input Clock Polarity
21.9 Transmitter Configuration
21.9.1 Programming the McBSP Registers for the Desired Transmitter Operation
21.9.2 Resetting and Enabling the Transmitter
21.9.2.1 Reset Considerations
21.9.3 Set the Transmitter Pins to Operate as McBSP Pins
21.9.4 Digital Loopback Mode
21.9.4.1 Digital Loopback Mode
21.9.5 Clock Stop Mode
21.9.5.1 Clock Stop Mode
21.9.6 Transmit Multichannel Selection
21.9.7 Transmit Frame Phases
21.9.8 Transmit Word Length(s)
21.9.8.1 Word Length Bits
21.9.9 Transmit Frame Length
21.9.9.1 Selected Frame Length
21.9.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function
21.9.10.1 Unexpected Frame-Synchronization Pulses and Frame-Synchronization Ignore
21.9.10.2 Examples Showing the Effects of XFIG
21.9.11 Transmit Companding Mode
21.9.11.1 Companding
21.9.11.2 Format for Data To Be Compressed
21.9.11.3 Capability to Compand Internal Data
21.9.11.4 Option to Transmit LSB First
21.9.12 Transmit Data Delay
21.9.12.1 Data Delay
21.9.12.2 0-Bit Data Delay
21.9.12.3 2-Bit Data Delay
21.9.13 Transmit DXENA Mode
21.9.14 Transmit Interrupt Mode
21.9.15 Transmit Frame-Synchronization Mode
21.9.15.1 Other Considerations
21.9.16 Transmit Frame-Synchronization Polarity
21.9.16.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
21.9.17 SRG Frame-Synchronization Period and Pulse Width
21.9.17.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
21.9.18 Transmit Clock Mode
21.9.18.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
21.9.18.2 Other Considerations
21.9.19 Transmit Clock Polarity
21.9.19.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
21.10 Emulation and Reset Considerations
21.10.1 McBSP Emulation Mode
21.10.2 Resetting and Initializing McBSPs
21.10.2.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
21.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
21.10.2.3 McBSP Initialization Procedure
21.10.2.4 Resetting the Transmitter While the Receiver is Running
21.11 Data Packing Examples
21.11.1 Data Packing Using Frame Length and Word Length
21.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function
21.12 Interrupt Generation
21.12.1 McBSP Receive Interrupt Generation
21.12.2 McBSP Transmit Interrupt Generation
21.12.3 Error Flags
21.13 McBSP Modes
21.14 McBSP Registers
21.14.1 McBSP Base Addresses
21.14.2 Data Receive Registers (DRR[1,2])
21.14.2.1 Data Travel From Data Receive Pins to the Registers
21.14.3 Data Transmit Registers (DXR[1,2])
21.14.3.1 Data Travel From Registers to Data Transmit (DX) Pins
21.14.4 Serial Port Control Registers (SPCR[1,2])
21.14.4.1 Serial Port Control 1 Register (SPCR1)
21.14.4.2 Serial Port Control 2 Register (SPCR2)
21.14.5 Receive Control Registers (RCR[1, 2])
21.14.5.1 Receive Control Register 1 (RCR1)
21.14.5.2 Receive Control Register 2 (RCR2)
21.14.6 Transmit Control Registers (XCR1 and XCR2)
21.14.6.1 Transmit Control 1 Register (XCR1)
21.14.6.2 Transmit Control 2 Register (XCR2)
21.14.7 Sample Rate Generator Registers (SRGR1 and SRGR2)
21.14.7.1 Sample Rate Generator 1 Register (SRGR1)
21.14.7.2 Sample Rate Generator 2 Register (SRGR2)
21.14.8 Multichannel Control Registers (MCR[1,2])
21.14.8.1 Multichannel Control 1 Register (MCR1)
21.14.8.2 Multichannel Control 2 Register (MCR2)
21.14.9 Pin Control Register (PCR)
21.14.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF, RCERG, RCERH)
21.14.10.1 RCERs Used in the Receive Multichannel Selection Mode
21.14.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF, XCERG, XCERH)
21.14.11.1 XCERs Used in a Transmit Multichannel Selection Mode
21.14.12 McBSP Interrupt Enable Register
22 Controller Area Network (CAN)
22.1 Overview
22.1.1 Features
22.1.2 Functional Description
22.1.3 Block Diagram
22.1.3.1 CAN Core
22.1.3.2 Message Handler
22.1.3.3 Message RAM
22.1.3.4 Registers and Message Object Access (IFx)
22.2 Configuring Device Pins
22.3 Address/Data Bus Bridge
22.4 Operating Modes
22.4.1 Initialization
22.4.2 CAN Message Transfer (Normal Operation)
22.4.2.1 Disabled Automatic Retransmission
22.4.2.2 Auto-Bus-On
22.4.3 Test Modes
22.4.3.1 Silent Mode
22.4.3.2 Loopback Mode
22.4.3.3 External Loopback Mode
22.4.3.4 Loopback Combined with Silent Mode
22.5 Multiple Clock Source
22.6 Interrupt Functionality
22.6.1 Message Object Interrupts
22.6.2 Status Change Interrupts
22.6.3 Error Interrupts
22.6.4 PIE Nomenclature for DCAN Interrupts
22.6.5 Interrupt Topologies
22.7 Parity Check Mechanism
22.7.1 Behavior on Parity Error
22.8 Debug Mode
22.9 Module Initialization
22.10 Configuration of Message Objects
22.10.1 Configuration of a Transmit Object for Data Frames
22.10.2 Configuration of a Transmit Object for Remote Frames
22.10.3 Configuration of a Single Receive Object for Data Frames
22.10.4 Configuration of a Single Receive Object for Remote Frames
22.10.5 Configuration of a FIFO Buffer
22.11 Message Handling
22.11.1 Message Handler Overview
22.11.2 Receive/Transmit Priority
22.11.3 Transmission of Messages in Event Driven CAN Communication
22.11.4 Updating a Transmit Object
22.11.5 Changing a Transmit Object
22.11.6 Acceptance Filtering of Received Messages
22.11.7 Reception of Data Frames
22.11.8 Reception of Remote Frames
22.11.9 Reading Received Messages
22.11.10 Requesting New Data for a Receive Object
22.11.11 Storing Received Messages in FIFO Buffers
22.11.12 Reading from a FIFO Buffer
22.12 CAN Bit Timing
22.12.1 Bit Time and Bit Rate
22.12.1.1 Synchronization Segment
22.12.1.2 Propagation Time Segment
22.12.1.3 Phase Buffer Segments and Synchronization
22.12.1.4 Oscillator Tolerance Range
22.12.2 Configuration of the CAN Bit Timing
22.12.2.1 Calculation of the Bit Timing Parameters
22.12.2.2 Example for Bit Timing at High Baudrate
22.12.2.3 Example for Bit Timing at Low Baudrate
22.13 Message Interface Register Sets
22.13.1 Message Interface Register Sets 1 and 2
22.13.2 IF3 Register Set
22.14 Message RAM
22.14.1 Structure of Message Objects
22.14.2 Addressing Message Objects in RAM
22.14.3 Message RAM Representation in Debug Mode
22.15 CAN Registers
22.15.1 CAN Base Addresses
22.15.2 CAN_REGS Registers
22.15.2.1 CAN_CTL Register (Offset = 0h) [reset = 1401h]
22.15.2.2 CAN_ES Register (Offset = 4h) [reset = 7h]
22.15.2.3 CAN_ERRC Register (Offset = 8h) [reset = 0h]
22.15.2.4 CAN_BTR Register (Offset = Ch) [reset = 2301h]
22.15.2.5 CAN_INT Register (Offset = 10h) [reset = 0h]
22.15.2.6 CAN_TEST Register (Offset = 14h) [reset = 0h]
22.15.2.7 CAN_PERR Register (Offset = 1Ch) [reset = 100h]
22.15.2.8 CAN_RAM_INIT Register (Offset = 40h) [reset = 5h]
22.15.2.9 CAN_GLB_INT_EN Register (Offset = 50h) [reset = 0h]
22.15.2.10 CAN_GLB_INT_FLG Register (Offset = 54h) [reset = 0h]
22.15.2.11 CAN_GLB_INT_CLR Register (Offset = 58h) [reset = 0h]
22.15.2.12 CAN_ABOTR Register (Offset = 80h) [reset = 0h]
22.15.2.13 CAN_TXRQ_X Register (Offset = 84h) [reset = 0h]
22.15.2.14 CAN_TXRQ_21 Register (Offset = 88h) [reset = 0h]
22.15.2.15 CAN_NDAT_X Register (Offset = 98h) [reset = 0h]
22.15.2.16 CAN_NDAT_21 Register (Offset = 9Ch) [reset = 0h]
22.15.2.17 CAN_IPEN_X Register (Offset = ACh) [reset = 0h]
22.15.2.18 CAN_IPEN_21 Register (Offset = B0h) [reset = 0h]
22.15.2.19 CAN_MVAL_X Register (Offset = C0h) [reset = 0h]
22.15.2.20 CAN_MVAL_21 Register (Offset = C4h) [reset = 0h]
22.15.2.21 CAN_IP_MUX21 Register (Offset = D8h) [reset = 0h]
22.15.2.22 CAN_IF1CMD Register (Offset = 100h) [reset = 1h]
22.15.2.23 CAN_IF1MSK Register (Offset = 104h) [reset = FFFFFFFFh]
22.15.2.24 CAN_IF1ARB Register (Offset = 108h) [reset = 0h]
22.15.2.25 CAN_IF1MCTL Register (Offset = 10Ch) [reset = 0h]
22.15.2.26 CAN_IF1DATA Register (Offset = 110h) [reset = 0h]
22.15.2.27 CAN_IF1DATB Register (Offset = 114h) [reset = 0h]
22.15.2.28 CAN_IF2CMD Register (Offset = 120h) [reset = 1h]
22.15.2.29 CAN_IF2MSK Register (Offset = 124h) [reset = FFFFFFFFh]
22.15.2.30 CAN_IF2ARB Register (Offset = 128h) [reset = 0h]
22.15.2.31 CAN_IF2MCTL Register (Offset = 12Ch) [reset = 0h]
22.15.2.32 CAN_IF2DATA Register (Offset = 130h) [reset = 0h]
22.15.2.33 CAN_IF2DATB Register (Offset = 134h) [reset = 0h]
22.15.2.34 CAN_IF3OBS Register (Offset = 140h) [reset = 0h]
22.15.2.35 CAN_IF3MSK Register (Offset = 144h) [reset = FFFFFFFFh]
22.15.2.36 CAN_IF3ARB Register (Offset = 148h) [reset = 0h]
22.15.2.37 CAN_IF3MCTL Register (Offset = 14Ch) [reset = 0h]
22.15.2.38 CAN_IF3DATA Register (Offset = 150h) [reset = 0h]
22.15.2.39 CAN_IF3DATB Register (Offset = 154h) [reset = 0h]
22.15.2.40 CAN_IF3UPD Register (Offset = 160h) [reset = 0h]
23 Universal Serial Bus (USB) Controller
23.1 Introduction
23.2 Features
23.2.1 Block Diagram
23.2.2 Signal Description
23.2.3 VBus Recommendations
23.3 Functional Description
23.3.1 Operation as a Device
23.3.1.1 Control and Configurable Endpoints
23.3.1.1.1 IN Transactions as a Device
23.3.1.1.2 Out Transactions as a Device
23.3.1.1.3 Scheduling
23.3.1.1.4 Additional Actions
23.3.1.1.5 Device Mode Suspend
23.3.1.1.6 Start of Frame
23.3.1.1.7 USB Reset
23.3.1.1.8 Connect/Disconnect
23.3.2 Operation as a Host
23.3.2.1 Endpoint Registers
23.3.2.2 IN Transactions as a Host
23.3.2.3 OUT Transactions as a Host
23.3.2.4 Transaction Scheduling
23.3.2.5 USB Hubs
23.3.2.6 Babble
23.3.2.7 Host SUSPEND
23.3.2.8 USB RESET
23.3.2.9 Connect/Disconnect
23.3.3 DMA Operation
23.3.4 Address/Data Bus Bridge
23.4 Initialization and Configuration
23.4.1 Pin Configuration
23.4.2 Endpoint Configuration
23.5 USB Registers
23.5.1 USB Base Address
23.5.2 USB Register Map
23.5.3 USB Register Descriptions
23.5.3.1 USB Device Functional Address Register
23.5.3.2 USB Power Management Register
23.5.3.3 USB Transmit Interrupt Status Register
23.5.3.4 USB Receive Interrupt Status Register
23.5.3.5 USB Transmit Interrupt Enable Register
23.5.3.6 USB Receive Interrupt Enable Register
23.5.3.7 USB General Interrupt Status Register
23.5.3.8 USB Interrupt Enable Register
23.5.3.9 USB Frame Value Register
23.5.3.10 USB Endpoint Index Register
23.5.3.11 USB Test Mode Register
23.5.3.12 USB FIFO Endpoint Registers
23.5.3.13 USB Device Control Register
23.5.3.14 USB Transmit Dynamic FIFO Sizing Register
23.5.3.15 USB Receive Dynamic FIFO Sizing Register
23.5.3.16 USB Transmit FIFO Start Address Register
23.5.3.17 USB Receive FIFO Start Address Register
23.5.3.18 USB Connect Timing Register
23.5.3.19 USB Full-Speed Last Transaction to End of Frame Timing Register
23.5.3.20 USB Low-Speed Last Transaction to End of Frame Timing Register
23.5.3.21 USB Transmit Functional Address Endpoint Registers
23.5.3.22 USB Transmit Hub Address Endpoint Registers
23.5.3.23 USB Transmit Hub Port Endpoint Registers
23.5.3.24 USB Receive Functional Address Endpoint Registers
23.5.3.25 USB Receive Hub Address Endpoint Registers
23.5.3.26 USB Receive Hub Port Endpoint Registers
23.5.3.27 USB Maximum Transmit Data Endpoint Registers
23.5.3.28 USB Control and Status Endpoint 0 Low Register
23.5.3.29 USB Control and Status Endpoint 0 High Register
23.5.3.30 USB Receive Byte Count Endpoint 0 Register
23.5.3.31 USB Type Endpoint 0 Register
23.5.3.32 USB NAK Limit Register
23.5.3.33 USB Transmit Control and Status Endpoint Low Register
23.5.3.34 USB Transmit Control and Status Endpoint High Register
23.5.3.35 USB Maximum Receive Data Endpoint Registers
23.5.3.36 USB Receive Control and Status Endpoint Low Register
23.5.3.37 USB Receive Control and Status Endpoint n High Register
23.5.3.38 USB Receive Byte Count Endpoint Registers
23.5.3.39 USB Host Transmit Configure Type Endpoint Register
23.5.3.40 USB Host Transmit Interval Endpoint Register
23.5.3.41 USB Host Configure Receive Type Endpoint Register
23.5.3.42 USB Host Receive Polling Interval Endpoint Register
23.5.3.43 USB Request Packet Count in Block Transfer Endpoint Registers
23.5.3.44 USB Receive Double Packet Buffer Disable Register
23.5.3.45 USB Transmit Double Packet Buffer Disable Register
23.5.3.46 USB External Power Control Register
23.5.3.47 USB External Power Control Raw Interrupt Status Register
23.5.3.48 USB External Power Control Interrupt Mask Register
23.5.3.49 USB External Power Control Interrupt Status and Clear Register
23.5.3.50 USB Device RESUME Raw Interrupt Status Register
23.5.3.51 USB Device RESUME Raw Interrupt Mask Register
23.5.3.52 USB Device RESUME Interrupt Status and Clear Register
23.5.3.53 USB General-Purpose Control and Status Register
23.5.3.54 USB DMA Select Register
24 Universal Parallel Port (uPP)
24.1 Introduction
24.1.1 Features Supported
24.2 Configuring Device Pins
24.3 Functional Description
24.3.1 Functional Block Diagram
24.3.2 Data Flow
24.3.3 Clock Generation and Control
24.4 IO Interface and System Requirements
24.4.1 Pin Multiplexing
24.4.2 Internal DMA Controller Description
24.4.2.1 DMA Programming Concepts
24.4.2.2 Data Interleave Mode
24.4.3 Protocol Description
24.4.3.1 DATA[7:0] Signals
24.4.3.2 START Signal
24.4.3.3 ENABLE
24.4.3.4 WAIT Signal
24.4.3.5 CLOCK Signal
24.4.3.6 Signal Timing Diagrams
24.4.4 Data Format
24.4.5 Reset Considerations
24.4.5.1 Software Reset
24.4.5.2 Hardware Reset
24.4.6 Interrupt Support
24.4.6.1 End of Line (EOL) Event
24.4.6.2 End of Window (EOW) Event
24.4.6.3 Underrun or Overflow (UOR) Event
24.4.6.4 DMA Programming Error (DPE) Event
24.4.7 Emulation Considerations
24.4.8 Transmit and Receive FIFOs
24.4.9 Transmit and Receive Data (MSG) RAM
24.4.10 Initialization and Operation
24.4.10.1 System Tuning Tips
24.5 UPP Registers
24.5.1 UPP Base Addresses
24.5.2 UPP_REGS Registers
24.5.2.1 PID Register (Offset = 0h) [reset = 44231100h]
24.5.2.2 PERCTL Register (Offset = 2h) [reset = 0h]
24.5.2.3 CHCTL Register (Offset = 8h) [reset = 0h]
24.5.2.4 IFCFG Register (Offset = Ah) [reset = 0h]
24.5.2.5 IFIVAL Register (Offset = Ch) [reset = 0h]
24.5.2.6 THCFG Register (Offset = Eh) [reset = 0h]
24.5.2.7 RAWINTST Register (Offset = 10h) [reset = 0h]
24.5.2.8 ENINTST Register (Offset = 12h) [reset = 0h]
24.5.2.9 INTENSET Register (Offset = 14h) [reset = 0h]
24.5.2.10 INTENCLR Register (Offset = 16h) [reset = 0h]
24.5.2.11 CHIDESC0 Register (Offset = 20h) [reset = 0h]
24.5.2.12 CHIDESC1 Register (Offset = 22h) [reset = 0h]
24.5.2.13 CHIDESC2 Register (Offset = 24h) [reset = 0h]
24.5.2.14 CHIST0 Register (Offset = 28h) [reset = 0h]
24.5.2.15 CHIST1 Register (Offset = 2Ah) [reset = 0h]
24.5.2.16 CHIST2 Register (Offset = 2Ch) [reset = 0h]
24.5.2.17 CHQDESC0 Register (Offset = 30h) [reset = 0h]
24.5.2.18 CHQDESC1 Register (Offset = 32h) [reset = 0h]
24.5.2.19 CHQDESC2 Register (Offset = 34h) [reset = 0h]
24.5.2.20 CHQST0 Register (Offset = 38h) [reset = 0h]
24.5.2.21 CHQST1 Register (Offset = 3Ah) [reset = 0h]
24.5.2.22 CHQST2 Register (Offset = 3Ch) [reset = 0h]
24.5.2.23 GINTEN Register (Offset = 40h) [reset = 0h]
24.5.2.24 GINTFLG Register (Offset = 42h) [reset = 0h]
24.5.2.25 GINTCLR Register (Offset = 44h) [reset = 0h]
24.5.2.26 DLYCTL Register (Offset = 46h) [reset = 1h]
25 External Memory Interface (EMIF)
25.1 Introduction
25.1.1 Purpose of the Peripheral
25.1.2 Features
25.1.2.1 Asynchronous Memory Support
25.1.2.2 Synchronous DRAM Memory Support
25.1.3 Functional Block Diagram
25.2 Configuring Device Pins
25.3 EMIF Module Architecture
25.3.1 EMIF Clock Control
25.3.2 EMIF Requests
25.3.3 EMIF Signal Descriptions
25.3.4 EMIF Signal Multiplexing Control
25.3.5 SDRAM Controller and Interface
25.3.5.1 SDRAM Commands
25.3.5.2 Interfacing to SDRAM
25.3.5.3 SDRAM Configuration Registers
25.3.5.4 SDRAM Auto-Initialization Sequence
25.3.5.5 SDRAM Configuration Procedure
25.3.5.6 EMIF Refresh Controller
25.3.5.6.1 Determining the Appropriate Value for the RR Field
25.3.5.7 Self-Refresh Mode
25.3.5.8 Power Down Mode
25.3.5.9 SDRAM Read Operation
25.3.5.10 SDRAM Write Operations
25.3.5.11 Mapping from Logical Address to EMIF Pins: Changed EM1DQM[1:0] to ED
25.3.6 Asynchronous Controller and Interface
25.3.6.1 Interfacing to Asynchronous Memory
25.3.6.2 Accessing Larger Asynchronous Memories
25.3.6.3 Configuring EMIF for Asynchronous Accesses
25.3.6.4 Read and Write Operations in Normal Mode
25.3.6.4.1 Asynchronous Read Operations (Normal Mode)
25.3.6.4.2 Asynchronous Write Operations (Normal Mode)
25.3.6.5 Read and Write Operation in Select Strobe Mode
25.3.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
25.3.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
25.3.6.6 Extended Wait Mode and the EM1WAIT Pin
25.3.7 Data Bus Parking
25.3.8 Reset and Initialization Considerations
25.3.9 Interrupt Support
25.3.9.1 Interrupt Events
25.3.10 DMA Event Support
25.3.11 EMIF Signal Multiplexing
25.3.12 Memory Map
25.3.13 Priority and Arbitration
25.3.14 System Considerations
25.3.14.1 Asynchronous Request Times
25.3.15 Power Management
25.3.15.1 Power Management Using Self-Refresh Mode
25.3.15.2 Power Management Using Power Down Mode
25.3.16 Emulation Considerations
25.4 Example Configuration
25.4.1 Hardware Interface
25.4.2 Software Configuration
25.4.2.1 Configuring the SDRAM Interface
25.4.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
25.4.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
25.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
25.4.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
25.4.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
25.4.2.2 Configuring the Flash Interface
25.4.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
25.5 EMIF Registers
25.5.1 EMIF Base Addresses
25.5.2 EMIF_REGS Registers
25.5.2.1 RCSR Register (Offset = 0h) [reset = 40000205h]
25.5.2.2 ASYNC_WCCR Register (Offset = 2h) [reset = F0000080h]
25.5.2.3 SDRAM_CR Register (Offset = 4h) [reset = 620h]
25.5.2.4 SDRAM_RCR Register (Offset = 6h) [reset = 80h]
25.5.2.5 ASYNC_CS2_CR Register (Offset = 8h) [reset = 3FFFFFFDh]
25.5.2.6 ASYNC_CS3_CR Register (Offset = Ah) [reset = 3FFFFFFDh]
25.5.2.7 ASYNC_CS4_CR Register (Offset = Ch) [reset = 3FFFFFFDh]
25.5.2.8 SDRAM_TR Register (Offset = 10h) [reset = 19214610h]
25.5.2.9 TOTAL_SDRAM_AR Register (Offset = 18h) [reset = 0h]
25.5.2.10 TOTAL_SDRAM_ACTR Register (Offset = 1Ah) [reset = 0h]
25.5.2.11 SDR_EXT_TMNG Register (Offset = 1Eh) [reset = 7h]
25.5.2.12 INT_RAW Register (Offset = 20h) [reset = 0h]
25.5.2.13 INT_MSK Register (Offset = 22h) [reset = 0h]
25.5.2.14 INT_MSK_SET Register (Offset = 24h) [reset = 0h]
25.5.2.15 INT_MSK_CLR Register (Offset = 26h) [reset = 0h]
25.5.3 EMIF1_CONFIG_REGS Registers
25.5.3.1 EMIF1LOCK Register (Offset = 0h) [reset = 0h]
25.5.3.2 EMIF1COMMIT Register (Offset = 2h) [reset = 0h]
25.5.3.3 EMIF1ACCPROT0 Register (Offset = 8h) [reset = 0h]
25.5.4 EMIF2_CONFIG_REGS Registers
25.5.4.1 EMIF2LOCK Register (Offset = 0h) [reset = 0h]
25.5.4.2 EMIF2COMMIT Register (Offset = 2h) [reset = 0h]
25.5.4.3 EMIF2ACCPROT0 Register (Offset = 8h) [reset = 0h]
Revision History
Important Notice
TMS320F2837xD Dual-Core Delfino
Microcontrollers
Technical Reference Manual
Literature Number: SPRUHM8H
December 2013–Revised January 2019
Contents
2
3
3.3
Preface....................................................................................................................................... 79
C2000Ware Quick Start Guide.............................................................................................. 80
1
Package Structure.......................................................................................................... 81
1.1
1.1.1 Documentation..................................................................................................... 81
1.1.2 Devices ............................................................................................................. 81
1.1.3 Libraries ............................................................................................................ 81
C2000Ware GUI............................................................................................................ 81
1.2
Updating C2000Ware...................................................................................................... 82
1.3
Code Composer Studio.................................................................................................... 82
1.4
C28x Processor.................................................................................................................. 83
Overview..................................................................................................................... 84
2.1
Floating-Point Unit ......................................................................................................... 84
2.2
Trigonometric Math Unit .................................................................................................. 84
2.3
Viterbi, Complex Math, and CRC Unit II (VCU-II) ..................................................................... 85
2.4
System Control .................................................................................................................. 86
Introduction.................................................................................................................. 87
3.1
System Control Functional Description.................................................................................. 87
3.2
3.2.1 Device Identification .............................................................................................. 87
3.2.2 Device Configuration Registers ................................................................................. 88
Resets ....................................................................................................................... 88
3.3.1 Reset Sources ..................................................................................................... 88
3.3.2 External Reset (XRS)............................................................................................. 89
3.3.3 Power-On Reset (POR) .......................................................................................... 89
3.3.4 Debugger Reset (SYSRS) ....................................................................................... 89
3.3.5 Watchdog Reset (WDRS)........................................................................................ 90
3.3.6 NMI Watchdog Reset (NMIWDRS) ............................................................................. 90
3.3.7 DCSM Safe Code Copy Reset (SCCRESET)................................................................. 90
3.3.8 Hibernate Reset (HIBRESET) ................................................................................... 90
3.3.9 Hardware BIST Reset (HWBISTRS)............................................................................ 90
3.3.10 Test Reset (TRST)............................................................................................... 90
Peripheral Interrupts ....................................................................................................... 90
3.4.1 Interrupt Concepts................................................................................................. 91
3.4.2 Interrupt Architecture.............................................................................................. 91
3.4.3 Interrupt Entry Sequence......................................................................................... 93
3.4.4 Configuring and Using Interrupts................................................................................ 94
3.4.5 PIE Channel Mapping ............................................................................................ 96
3.4.6 Vector Tables ...................................................................................................... 97
Exceptions and Non-Maskable Interrupts ............................................................................. 103
3.5.1 Configuring and Using NMIs ................................................................................... 103
3.5.2 Emulation Considerations ...................................................................................... 103
3.5.3 NMI Sources...................................................................................................... 104
3.5.4 Illegal Instruction Trap (ITRAP) ................................................................................ 104
Safety Features ........................................................................................................... 104
3.6.1 Write Protection on Registers .................................................................................. 104
3.6.2 Missing Clock Detection Logic ................................................................................. 105
3.6
3.4
3.5
2
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3.7
3.8
3.9
3.12
3.10
3.6.3 PLLSLIP Detection .............................................................................................. 106
3.6.4 CPU1 and CPU2 PIE Vector Address Validity Check ...................................................... 106
3.6.5 NMIWDs .......................................................................................................... 107
3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 107
3.6.7 ECC Enabled Flash Memory................................................................................... 107
3.6.8 ERRORSTS Pin.................................................................................................. 107
Clocking ................................................................................................................... 108
3.7.1 Clock Sources.................................................................................................... 110
3.7.2 Derived Clocks ................................................................................................... 112
3.7.3 Device Clock Domains .......................................................................................... 112
3.7.4 XCLKOUT......................................................................................................... 113
3.7.5 Clock Connectivity ............................................................................................... 114
3.7.6 Clock Source and PLL Setup .................................................................................. 115
32-Bit CPU Timers 0/1/2................................................................................................. 118
Watchdog Timers ......................................................................................................... 120
3.9.1 Servicing the Watchdog Timer................................................................................. 120
3.9.2 Minimum Window Check ....................................................................................... 121
3.9.3 Watchdog Reset or Watchdog Interrupt Mode............................................................... 121
3.9.4 Watchdog Operation in Low Power Modes .................................................................. 122
3.9.5 Emulation Considerations ...................................................................................... 122
Low Power Modes........................................................................................................ 123
3.10.1 IDLE .............................................................................................................. 123
3.10.2 STANDBY ....................................................................................................... 123
3.10.3 HALT ............................................................................................................. 124
3.10.4 HIB................................................................................................................ 124
3.11 Memory Controller Module .............................................................................................. 126
3.11.1 Functional Description ......................................................................................... 126
Flash and OTP Memory ................................................................................................. 134
3.12.1 Features.......................................................................................................... 134
3.12.2 Flash Tools ...................................................................................................... 134
3.12.3 Default Flash Configuration ................................................................................... 135
3.12.4 Flash Bank, OTP and Pump .................................................................................. 135
3.12.5 Flash Module Controller (FMC) ............................................................................... 135
3.12.6 Flash and OTP Power-Down Modes and Wakeup......................................................... 136
3.12.7 Flash and OTP Performance.................................................................................. 138
3.12.8 Flash Read Interface ........................................................................................... 138
3.12.9 Erase/Program Flash........................................................................................... 140
3.12.10 Error Correction Code (ECC) Protection................................................................... 141
3.12.11 Reserved Locations Within Flash and OTP ............................................................... 145
3.12.12 Procedure to Change the Flash Control Registers ....................................................... 145
3.12.13 Flash Pump Ownership Semaphore........................................................................ 145
3.13 Dual Code Security Module (DCSM)................................................................................... 147
3.13.1 Functional Description ......................................................................................... 147
3.13.2 CSM Impact on Other On-Chip Resources ................................................................. 153
3.13.3 Incorporating Code Security in User Applications.......................................................... 154
JTAG ....................................................................................................................... 158
F2837xD System Control Registers.................................................................................... 160
3.15.1 F2837xD System Control Base Addresses ................................................................. 160
3.15.2 CPUTIMER_REGS Registers................................................................................. 161
3.15.3 PIE_CTRL_REGS Registers.................................................................................. 168
3.15.4 WD_REGS Registers .......................................................................................... 220
3.15.5 NMI_INTRUPT_REGS Registers............................................................................. 226
3.15.6 XINT_REGS Registers......................................................................................... 240
3.14
3.15
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3.15.7 DMA_CLA_SRC_SEL_REGS Registers .................................................................... 249
3.15.8 FLASH_PUMP_SEMAPHORE_REGS Registers .......................................................... 256
3.15.9 DEV_CFG_REGS Registers .................................................................................. 258
3.15.10 CLK_CFG_REGS Registers................................................................................. 325
3.15.11 CPU_SYS_REGS Registers................................................................................. 348
3.15.12 ROM_PREFETCH_REGS Registers ....................................................................... 388
3.15.13 DCSM_Z1_OTP Registers................................................................................... 390
3.15.14 DCSM_Z2_OTP Registers................................................................................... 397
3.15.15 DCSM_Z1_REGS Registers................................................................................. 404
3.15.16 DCSM_Z2_REGS Registers................................................................................. 424
3.15.17 DCSM_COMMON_REGS Registers ....................................................................... 444
3.15.18 MEM_CFG_REGS Registers................................................................................ 451
3.15.19 ACCESS_PROTECTION_REGS Registers ............................................................... 496
3.15.20 MEMORY_ERROR_REGS Registers...................................................................... 516
3.15.21 ROM_WAIT_STATE_REGS Registers..................................................................... 533
3.15.22 FLASH_CTRL_REGS Registers ............................................................................ 535
3.15.23 FLASH_ECC_REGS Registers ............................................................................. 544
3.15.24 CPU_ID_REGS Registers ................................................................................... 567
3.15.25 UID_REGS Registers......................................................................................... 569
ROM Code and Peripheral Booting ..................................................................................... 578
Introduction ................................................................................................................ 579
4.1
Device Boot Philosophy.................................................................................................. 579
4.2
Device Boot Modes....................................................................................................... 579
4.3
Configuring Boot Mode Pins ............................................................................................ 580
4.4
Configuring Get Boot Options........................................................................................... 581
4.5
Configuring Emulation Boot Options ................................................................................... 582
4.6
Device Boot Flow Diagrams............................................................................................. 584
4.7
4.7.1 Emulation Boot Flow Diagrams ................................................................................ 585
4.7.2 Standalone and Hibernate Boot Flow Diagrams............................................................. 587
Device Reset and Exception Handling................................................................................. 589
4.8.1 Reset Causes and Handling.................................................................................... 589
4.8.2 Exceptions and Interrupts Handling ........................................................................... 590
Boot ROM Description ................................................................................................... 590
4.9.1 Entry Points....................................................................................................... 590
4.9.2 Wait Points........................................................................................................ 591
4.9.3 Memory Maps .................................................................................................... 591
4.9.4 Boot Modes....................................................................................................... 594
4.9.5 Boot Data Stream Structure.................................................................................... 607
4.9.6 GPIO Assignments .............................................................................................. 609
4.9.7 Boot IPC .......................................................................................................... 611
4.9.8 Clock Initializations .............................................................................................. 614
4.9.9 Wait State Configuration........................................................................................ 615
4.9.10 Boot Status information ........................................................................................ 615
4.9.11 ROM Version.................................................................................................... 617
Direct Memory Access (DMA)............................................................................................. 619
Introduction ................................................................................................................ 620
5.1
Architecture................................................................................................................ 621
5.2
5.2.1 Block Diagram.................................................................................................... 621
5.2.2 Common Peripheral Architecture .............................................................................. 621
5.2.3 Peripheral Interrupt Event Trigger Sources .................................................................. 623
5.2.4 DMA Bus.......................................................................................................... 628
Address Pointer and Transfer Control ................................................................................. 628
Pipeline Timing and Throughput........................................................................................ 633
5.3
5.4
4.8
4.9
4
5
4
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6
7
8
6.3
6.4
5.7
5.8
5.5
5.6
CPU and CLA Arbitration ................................................................................................ 634
Channel Priority ........................................................................................................... 635
5.6.1 Round-Robin Mode.............................................................................................. 635
5.6.2 Channel 1 High Priority Mode.................................................................................. 636
Overrun Detection Feature .............................................................................................. 636
DMA Registers ............................................................................................................ 637
5.8.1 DMA Base Addresses........................................................................................... 637
5.8.2 DMA_REGS Registers.......................................................................................... 638
5.8.3 DMA_CH_REGS Registers..................................................................................... 643
Control Law Accelerator (CLA)........................................................................................... 671
Control Law Accelerator (CLA) Overview ............................................................................. 672
6.1
CLA Interface.............................................................................................................. 674
6.2
6.2.1 CLA Memory ..................................................................................................... 674
6.2.2 CLA Memory Bus ................................................................................................ 675
6.2.3 Shared Peripherals and EALLOW Protection................................................................ 675
6.2.4 CLA Tasks and Interrupt Vectors.............................................................................. 676
6.2.5 CLA Software Interrupt to CPU ................................................................................ 678
CLA and CPU Arbitration ................................................................................................ 678
6.3.1 CLA Message RAM ............................................................................................. 678
CLA Configuration and Debug .......................................................................................... 680
6.4.1 Building a CLA Application ..................................................................................... 680
6.4.2 Typical CLA Initialization Sequence........................................................................... 680
6.4.3 Debugging CLA Code........................................................................................... 681
6.4.4 CLA Illegal Opcode Behavior .................................................................................. 682
6.4.5 Resetting the CLA ............................................................................................... 682
Pipeline..................................................................................................................... 684
6.5.1 Pipeline Overview................................................................................................ 684
6.5.2 CLA Pipeline Alignment......................................................................................... 684
6.5.3 Parallel Instructions.............................................................................................. 688
Instruction Set............................................................................................................. 689
6.6.1 Instruction Descriptions ......................................................................................... 689
6.6.2 Addressing Modes and Encoding.............................................................................. 691
6.6.3 Instructions ....................................................................................................... 693
CLA Registers............................................................................................................. 804
6.7.1 CLA Base Addresses............................................................................................ 804
6.7.2 CLA_REGS Registers........................................................................................... 805
6.7.3 CLA_SOFTINT_REGS Registers.............................................................................. 846
Interprocessor Communication (IPC) .................................................................................. 850
Interprocessor Communication ......................................................................................... 851
7.1
Message RAMs ........................................................................................................... 852
7.2
IPC Flags and Interrupts................................................................................................. 852
7.3
IPC Command Registers ................................................................................................ 852
7.4
Free-Running Counter ................................................................................................... 852
7.5
IPC Communication Protocol............................................................................................ 853
7.6
IPC Registers.............................................................................................................. 854
7.7
7.7.1 IPC Base Addresses ............................................................................................ 854
7.7.2 IPC_REGS_CPU1 Registers................................................................................... 855
7.7.3 IPC_REGS_CPU2 Registers................................................................................... 888
General-Purpose Input/Output (GPIO) ................................................................................. 921
GPIO Overview ........................................................................................................... 922
8.1
Configuration Overview .................................................................................................. 923
8.2
Digital General-Purpose I/O Control.................................................................................... 923
8.3
Input Qualification......................................................................................................... 925
8.4
5
Contents
6.5
6.6
6.7
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10
11
8.5
8.6
8.7
8.8
8.9
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8.4.1 No Synchronization (Asynchronous Input) ................................................................... 925
8.4.2 Synchronization to SYSCLKOUT Only........................................................................ 925
8.4.3 Qualification Using a Sampling Window...................................................................... 925
USB Signals ............................................................................................................... 928
SPI Signals ................................................................................................................ 928
GPIO and Peripheral Muxing............................................................................................ 929
Internal Pullup Configuration Requirements........................................................................... 934
GPIO Registers ........................................................................................................... 935
8.9.1 GPIO Base Addresses .......................................................................................... 935
8.9.2 GPIO_CTRL_REGS Registers................................................................................. 936
8.9.3 GPIO_DATA_REGS Registers ............................................................................... 1101
Crossbar (X-BAR)............................................................................................................ 1151
GPIO Input X-BAR ...................................................................................................... 1152
9.1
ePWM and GPIO Output X-BAR...................................................................................... 1153
9.2
9.2.1 ePWM X-BAR................................................................................................... 1153
9.2.2 GPIO Output X-BAR ........................................................................................... 1156
9.2.3 X-BAR Flags .................................................................................................... 1157
XBAR Registers ......................................................................................................... 1159
9.3.1 XBAR Base Addresses........................................................................................ 1159
9.3.2 XBAR_REGS Registers ....................................................................................... 1160
9.3.3 INPUT_XBAR_REGS Registers ............................................................................. 1173
9.3.4 OUTPUT_XBAR_REGS Registers .......................................................................... 1190
9.3.5 EPWM_XBAR_REGS Registers ............................................................................. 1291
Analog Subsystem .......................................................................................................... 1384
Analog Subsystem ...................................................................................................... 1385
10.1
10.1.1 Features ....................................................................................................... 1385
10.1.2 Block Diagram ................................................................................................. 1385
10.1.3 Lock Registers................................................................................................. 1389
Analog Subsystem Registers .......................................................................................... 1390
10.2.1 Analog Subsystem Base Addresses........................................................................ 1390
10.2.2 ANALOG_SUBSYS_REGS Registers...................................................................... 1391
Analog-to-Digital Converter (ADC)..................................................................................... 1401
Analog-to-Digital Converter (ADC).................................................................................... 1402
11.1
11.1.1 Features ........................................................................................................ 1402
11.1.2 ADC Block Diagram........................................................................................... 1402
11.1.3 ADC Configurability ........................................................................................... 1403
11.1.4 SOC Principle of Operation.................................................................................. 1407
11.1.5 SOC Configuration Examples ............................................................................... 1410
11.1.6 ADC Conversion Priority ..................................................................................... 1412
11.1.7 Burst Mode..................................................................................................... 1415
11.1.8 EOC and Interrupt Operation ................................................................................ 1417
11.1.9 Post-Processing Blocks ...................................................................................... 1417
11.1.10 Opens/Shorts Detection Circuit (OSDETECT)........................................................... 1420
11.1.11 Power-Up Sequence ........................................................................................ 1422
11.1.12 ADC Calibration.............................................................................................. 1422
ADC Timings............................................................................................................. 1423
11.2.1 ADC Timing Diagrams........................................................................................ 1424
Additional Information................................................................................................... 1429
11.3.1 Ensuring Synchronous Operation........................................................................... 1429
11.3.2 Choosing an Acquisition Window Duration ................................................................ 1433
11.3.3 Achieving Simultaneous Sampling.......................................................................... 1435
11.3.4 Designing an External Reference Circuit .................................................................. 1435
10.2
9.3
11.2
11.3
6
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12
13
14
11.4
11.3.5 Internal Temperature Sensor ................................................................................ 1437
ADC Registers........................................................................................................... 1438
11.4.1 ADC Base Addresses ........................................................................................ 1438
11.4.2 ADC_REGS Registers........................................................................................ 1439
11.4.3 ADC_RESULT_REGS Registers............................................................................ 1578
Buffered Digital-to-Analog Converter (DAC) ....................................................................... 1599
Buffered Digital-to-Analog Converter (DAC) Overview............................................................. 1600
12.1
12.1.1 Features ........................................................................................................ 1600
12.1.2 Block Diagram ................................................................................................. 1600
12.2 Using the DAC........................................................................................................... 1600
12.2.1 Initialization Sequence........................................................................................ 1601
12.2.2 DAC Offset Adjustment....................................................................................... 1601
12.2.3 EPWMSYNCPER Signal..................................................................................... 1601
Lock Registers........................................................................................................... 1601
12.3
12.4 DAC Registers........................................................................................................... 1602
12.4.1 DAC Base Addresses ........................................................................................ 1602
12.4.2 DAC_REGS Registers........................................................................................ 1603
Comparator Subsystem (CMPSS)...................................................................................... 1611
13.1 CMPSS Overview ....................................................................................................... 1612
13.1.1 Features ........................................................................................................ 1612
13.1.2 Block Diagram ................................................................................................. 1612
13.2 Comparator............................................................................................................... 1613
13.3 Reference DAC.......................................................................................................... 1613
13.4 Ramp Generator......................................................................................................... 1615
13.4.1 Ramp Generator Overview .................................................................................. 1615
13.4.2 Ramp Generator Behavior ................................................................................... 1615
13.4.3 Ramp Generator Behavior at Corner Cases............................................................... 1616
13.5 Digital Filter .............................................................................................................. 1617
13.5.1 Filter Initialization Sequence................................................................................. 1618
13.6 Using the CMPSS....................................................................................................... 1618
13.6.1 LATCHCLR and EPWMSYNCPER Signals ............................................................... 1618
13.6.2 Synchronizer, Digital Filter and Latch Delays ............................................................. 1618
13.6.3 Calibrating the CMPSS....................................................................................... 1618
13.6.4 Enabling and Disabling the CMPSS Clock ................................................................ 1619
13.7 CMPSS Registers....................................................................................................... 1620
13.7.1 CMPSS Base Addresses..................................................................................... 1620
13.7.2 CMPSS_REGS Registers.................................................................................... 1621
Sigma Delta Filter Module (SDFM)..................................................................................... 1646
SDFM Module Overview ............................................................................................... 1647
14.1
14.1.1 SDFM Features................................................................................................ 1647
14.1.2 Block Diagram ................................................................................................. 1648
14.2 Configuring Device Pins................................................................................................ 1649
Input Control Unit........................................................................................................ 1649
14.3
Sinc Filter................................................................................................................. 1651
14.4
14.4.1 Data Rate and Latency of the Sinc Filter .................................................................. 1652
14.5 Data (Primary) Filter Unit............................................................................................... 1653
14.5.1 32-bit or 16-bit Data Filter Output Representation........................................................ 1653
14.5.2 SDSYNC Event................................................................................................ 1654
14.6 Comparator (Secondary) Filter Unit................................................................................... 1655
14.6.1 Higher threshold (HLT) comparator......................................................................... 1656
14.6.2 Lower Threshold (LLT) comparator......................................................................... 1656
Interrupt Unit ............................................................................................................. 1657
14.7.1 SDFM (SDINT) Interrupt sources: .......................................................................... 1657
7
14.7
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Contents
15
15.6
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14.8 Register Descriptions ................................................................................................... 1659
SDFM Registers......................................................................................................... 1661
14.9
14.9.1 SDFM Base Addesses ....................................................................................... 1661
14.9.2 SDFM_REGS Registers...................................................................................... 1662
Enhanced Pulse Width Modulator (ePWM) ......................................................................... 1698
Introduction............................................................................................................... 1699
15.1
15.1.1 Submodule Overview ......................................................................................... 1701
15.2 Configuring Device Pins................................................................................................ 1706
ePWM Modules Overview.............................................................................................. 1706
15.3
Time-Base (TB) Submodule ........................................................................................... 1708
15.4
15.4.1 Purpose of the Time-Base Submodule..................................................................... 1708
15.4.2 Controlling and Monitoring the Time-Base Submodule .................................................. 1709
15.4.3 Calculating PWM Period and Frequency .................................................................. 1710
15.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules..................................... 1714
15.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules .................... 1714
15.4.6 Time-Base Counter Modes and Timing Waveforms...................................................... 1714
15.4.7 Global Load .................................................................................................... 1717
15.5 Counter-Compare (CC) Submodule .................................................................................. 1719
15.5.1 Purpose of the Counter-Compare Submodule ............................................................ 1719
15.5.2 Controlling and Monitoring the Counter-Compare Submodule.......................................... 1719
15.5.3 Operational Highlights for the Counter-Compare Submodule........................................... 1720
15.5.4 Count Mode Timing Waveforms ............................................................................ 1722
Action-Qualifier (AQ) Submodule ..................................................................................... 1725
15.6.1 Purpose of the Action-Qualifier Submodule ............................................................... 1726
15.6.2 Action-Qualifier Submodule Control and Status Register Definitions .................................. 1726
15.6.3 Action-Qualifier Event Priority ............................................................................... 1729
15.6.4 AQCTLA and AQCTLB Shadow Mode Operations....................................................... 1730
15.6.5 Waveforms for Common Configurations ................................................................... 1732
15.7 Dead-Band Generator (DB) Submodule ............................................................................. 1739
15.7.1 Purpose of the Dead-Band Submodule .................................................................... 1739
15.7.2 Dead-band Submodule Additional Operating Modes..................................................... 1739
15.7.3 Operational Highlights for the Dead-Band Submodule................................................... 1741
PWM Chopper (PC) Submodule ..................................................................................... 1745
15.8.1 Purpose of the PWM Chopper Submodule ................................................................ 1745
15.8.2 Operational Highlights for the PWM Chopper Submodule............................................... 1745
15.8.3 Waveforms ..................................................................................................... 1746
Trip-Zone (TZ) Submodule............................................................................................. 1749
15.9.1 Purpose of the Trip-Zone Submodule ...................................................................... 1749
15.9.2 Operational Highlights for the Trip-Zone Submodule..................................................... 1749
15.9.3 Generating Trip Event Interrupts............................................................................ 1752
15.10 Event-Trigger (ET) Submodule........................................................................................ 1754
15.10.1 Operational Overview of the ePWM Type 4 Event-Trigger Submodule.............................. 1755
15.11 Digital Compare (DC) Submodule .................................................................................... 1760
15.11.1 Purpose of the Digital Compare Submodule............................................................. 1761
15.11.2 Enhanced Trip Action Using CMPSS ..................................................................... 1762
15.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis ......................................... 1762
15.11.4 Operation Highlights of the Digital Compare Submodule .............................................. 1762
15.12 ePWM X-BAR ........................................................................................................... 1768
15.13 Applications to Power Topologies .................................................................................... 1770
15.13.1 Overview of Multiple Modules ............................................................................. 1770
15.13.2 Key Configuration Capabilities............................................................................. 1770
15.13.3 Controlling Multiple Buck Converters With Independent Frequencies................................ 1771
15.13.4 Controlling Multiple Buck Converters With Same Frequencies........................................ 1773
15.8
15.9
8
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