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    Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.2
    Table of Contents
    Ch. 1: DDR3 and DDR2 SDRAM Memory Interface Solution
    Introduction
    Features
    Using MIG in the Vivado Design Suite
    Customizing and Generating the Core
    MIG Output Options
    Pin Compatible FPGAs
    Creating 7 Series FPGA DDR3 Memory Controller Block Design
    Memory Selection
    Controller Options
    Create Custom Part
    AXI Parameter Options
    Setting DDR3 Memory Parameter Option
    FPGA Options
    Bank Selection
    Summary
    Memory Model License
    PCB Information
    Design Notes
    Vivado Integrated Design Flow for MIG
    Directory Structure and File Descriptions
    Output Directory Structure
    Directory and File Contents
    /example_design/
    example_design/rtl
    example_design/rtl/traffic_gen
    /example_design/par
    /example_design/sim
    /user_design
    user_design/rtl/clocking
    user_design/rtl/controller
    user_design/rtl/ip_top
    user_design/rtl/phy
    user_design/rtl/ui
    /user_design/xdc
    Verify Pin Changes and Update Design
    Quick Start Example Design
    Overview
    Implementing the Example Design
    Simulating the Example Design (for Designs with the Standard User Interface)
    Traffic Generator Operation
    Modifying the Example Design
    Modifying Port Address Space
    Traffic Generator Signal Description
    Memory Initialization and Traffic Test Flow
    Memory Initialization
    Traffic Test Flow
    Simulating the Example Design (for Designs with the AXI4 Interface)
    Setting Up for Simulation
    Simulation Flow Using IES and VCS Script Files
    Simulation Flow Using Vivado Simulator
    Simulation Flow Using Questa Advanced Simulator
    Simulation Flow Using VCS
    Simulation Flow Using IES
    Synplify Pro Black Box Testing
    Core Architecture
    Overview
    User FPGA Logic
    AXI4 Slave Interface Block
    User Interface Block and User Interface
    Memory Controller and Native Interface
    PHY and the Physical Interface
    IDELAYCTRL
    User Interface
    app_addr[ADDR_WIDTH – 1:0]
    app_cmd[2:0]
    app_en
    app_hi_pri
    app_wdf_data[APP_DATA_WIDTH – 1:0]
    app_wdf_end
    app_wdf_mask[APP_MASK_WIDTH – 1:0]
    app_wdf_wren
    app_rdy
    app_rd_data[APP_DATA_WIDTH – 1:0]
    app_rd_data_end
    app_rd_data_valid
    app_wdf_rdy
    app_ref_req
    app_ref_ack
    app_zq_req
    app_zq_ack
    ui_clk_sync_rst
    ui_clk
    init_calib_complete
    AXI4 Slave Interface Block
    AXI4 Slave Interface Parameters
    AXI4 Slave Interface Signals
    Arbitration in AXI Shim
    Time Division Multiplexing (TDM)
    Round-Robin
    Read Priority (RD_PRI_REG)
    Read Priority with Starve Limit (RD_PRI_REG_STARVE_LIMIT)
    Write Priority (WRITE_PRIORITY, WRITE_PRIORITY_REG)
    AXI4-Lite Slave Control/Status Register Interface Block
    ECC Enable/Disable
    Single Error and Double Error Reporting
    Interrupt Generation
    Fault Collection
    Fault Injection
    AXI4-Lite Slave Control/Status Register Interface Parameters
    AXI4-Lite Slave Control/Status Register Interface Signals
    AXI4-Lite Slave Control/Status Register Map
    AXI4-Lite Slave Control/Status Register Map Detailed Descriptions
    ECC_STATUS
    ECC_EN_IRQ
    ECC_ON_OFF
    CE_CNT
    CE_FFA[31:0]
    CE_FFA[63:32]
    CE_FFD[31:0]
    CE_FFD[63:32]
    CE_FFD[95:64]
    CE_FFD[127:96]
    CE_FFE
    UE_FFA[31:0]
    UE_FFA[63:32]
    UE_FFD[31:0]
    UE_FFD[63:32]
    UE_FFD[95:64]
    UE_FFD[127:96]
    UE_FFE
    FI_D0
    FI_D1
    FI_D2
    FI_D3
    FI_ECC
    User Interface Block
    Native Interface
    Command Request Signals
    accept
    use_addr
    data_buf_addr
    Write Command Signals
    wr_data
    wr_data_addr
    wr_data_mask
    wr_data_en
    wr_data_offset
    Read Command Signals
    rd_data
    rd_data_addr
    rd_data_en
    rd_data_offset
    Native Interface Maintenance Command Signals
    app_ref_req
    app_ref_ack
    app_zq_req
    app_zq_ack
    Clocking Architecture
    Internal (FPGA) Logic Clock
    Write Path (Output) I/O Logic Clock
    Read Path (Input) I/O Logic Clock
    IDELAY Reference Clock
    Memory Controller
    Bank Machines
    Rank Machines
    Column Machine
    Arbitration Block
    Reordering
    Precharge Policy
    Error Correcting Code
    Read-Modify-Write
    ECC Self-Test Functionality
    PHY
    Overall PHY Architecture
    Memory Initialization and Calibration Sequence
    I/O Architecture
    PHY Control Block
    Command Path
    Datapath
    Power-Saving Features
    Calibration and Initialization Stages
    Memory Initialization
    PHASER_IN Phase Lock
    PHASER_IN DQSFOUND Calibration
    Write Leveling
    Multi-Purpose Register Read Leveling
    OCLKDELAYED Calibration
    Write Calibration
    Read Leveling
    PRBS Read Leveling
    Dynamic Calibration and Periodic Read Behavior
    Temperature Monitor
    Memory Controller to PHY Interface
    Designing with the Core
    Interfacing to the Core
    AXI4 Slave Interface
    AXI Addressing
    Upsizing
    User Interface
    Command Path
    Write Path
    Read Path
    User Refresh
    User ZQ
    Native Interface
    User Refresh
    User ZQ
    Physical Layer Interface (Non-Memory Controller Design)
    Customizing the Core
    Design Guidelines
    DDR3 SDRAM
    Design Rules
    Bank and Pin Selection Guides for DDR3 Designs
    Pin Swapping
    Bank Sharing Among Controllers
    System Clock, PLL and MMCM Locations, and Constraints
    DDR3 Component PCB Routing
    VREF
    VCCAUX_IO
    Power System and Plane Discontinuities
    Termination
    Trace Lengths
    Configuration
    I/O Standards
    DDR2 SDRAM
    Design Rules
    Pin Assignments
    Bank and Pin Selection Guides for DDR2 Designs
    Bank Sharing Among Controllers
    Pin Swapping
    Internal VREF
    System Clock, PLL Location, and Constraints
    Configuration
    Termination
    I/O Standards
    Trace Lengths
    Clocking
    Input Clock Guidelines
    Sharing sys_clk between Controllers
    Information on Sharing BUFG Clock (phy_clk)
    Information on Sync_Pulse
    DDR3 Pinout Examples
    Debugging DDR3/DDR2 Designs
    Finding Help on Xilinx.com
    Documentation
    Solution Centers
    Answer Records
    Technical Support
    Debug Tools
    Example Design
    Debug Signals
    Vivado Design Suite Debug Feature
    Reference Boards
    Hardware Debug
    General Checks
    Calibration Stages
    Memory Initialization
    Determine the Failing Calibration Stage
    Debug Signals
    Debugging PHASER_IN PHASELOCKED Calibration Failures (dbg_pi_phaselock_err = 1)
    Calibration Overview
    Debug
    Debugging PHASER_IN DQSFOUND Calibration Failures (dbg_pi_dqsfound_err = 1)
    Calibration Overview
    Debug
    Expected Vivado Logic Analyzer Tool Results
    Debugging Write Leveling Failures (dbg_wrlvl_err = 1)
    Calibration Overview
    Debug
    Expected Vivado Logic Analyzer Tool Results
    Debugging MPR Read Leveling Failures – DDR3 Only (dbg_rdlvl_err[1] = 1)
    Calibration Overview
    Debug
    Expected Vivado Logic Analyzer Tool Results
    Debugging OCLKDELAYED Calibration Failures
    Calibration Overview
    Debug
    Debugging Write Calibration Failures (dbg_wrcal_err = 1)
    Calibration Overview
    Debug
    Expected Vivado Logic Analyzer Tool Results
    Debugging Read Leveling Failures (dbg_rdlvl_err[0] = 1)
    Calibration Overview
    Debug
    Expected Vivado Logic Analyzer Tool Results
    Debugging PRBS Read Leveling Failures
    Calibration Overview
    Debug
    Calibration Times
    Debugging Data Errors
    General Checks
    Replicating the Error Using the Traffic Generator
    Isolating the Data Error
    Determining If a Data Error is Due to the Write or Read
    Checking and Varying Read Timing
    Automated Window Check
    Manual Window Check
    Analyzing Calibration Results
    Interface Debug
    AXI4-Lite Interfaces
    AXI4-Stream Interfaces
    CLOCK_DEDICATED_ROUTE Constraints
    System Clock
    Reference Clock
    Ch. 2: QDR II+ Memory Interface Solution
    Introduction
    Using MIG in the Vivado Design Suite
    Customizing and Generating the Core
    MIG Output Options
    Pin Compatible FPGAs
    Creating the 7 Series FPGA QDR II+ SRAM Design
    Memory Selection
    Controller Options
    Create Custom Part
    Memory Options
    FPGA Options
    Extended FPGA Options
    I/O Planning Options
    Bank Selection
    System Pins Selection
    Summary
    PCB Information
    Design Notes
    Finish
    Vivado Integrated Design Flow for MIG
    Directory Structure and File Descriptions
    Output Directory Structure
    Directory and File Contents
    /example_design/
    /user_design
    user_design/rtl/clocking
    user_design/rtl/phy
    /user_design/xdc
    Verify Pin Changes and Update Design
    Core Architecture
    Overview
    User Interface
    Command Request Signals
    Interfacing with the Core through the Client Interface
    Clocking Architecture
    Physical Interface
    Interfacing with the Memory Device
    PHY Architecture
    Write Path
    Output Architecture
    Output Path
    PHY Control Block
    Pre-FIFO
    Read Path
    Data Capture
    Calibration
    Calibration of Read Clock and Data
    Implementation Details
    Data Alignment and Valid Generation
    Write Calibration
    Customizing the Core
    Design Guidelines
    Design Rules
    Bank Sharing Among Controllers
    Trace Length Requirements
    Pinout Requirements
    System Clock, PLL Location, and Constraints
    Configuration
    Termination
    I/O Standards
    Clocking
    Input Clock Guidelines
    Sharing sys_clk between Controllers
    Information on Sharing BUFG Clock (phy_clk)
    Information on Sync_Pulse
    Debugging QDR II+ SRAM Designs
    Introduction
    Debug Tools
    Example Design
    Debug Signals
    Vivado Design Suite Debug Feature
    Simulation Debug
    Verifying the Simulation Using the Example Design
    Simulation Flow Using IES and VCS Script Files
    Simulation Flow Using Vivado Simulator
    Simulation Flow Using Questa Advanced Simulator
    Simulation Flow Using VCS
    Simulation Flow Using IES
    Memory Initialization
    Calibration
    Test Bench
    Proper Write and Read Commands
    Synthesis and Implementation Debug
    Verify Successful Synthesis and Implementation
    Verify Modifications to the MIG Tool Output
    Identifying and Analyzing Timing Failures
    Hardware Debug
    Clocking
    Verify Board Pinout
    Run Signal Integrity Simulation with IBIS Models
    Run the Example Design
    Debugging Common Hardware Issues
    Isolating Bit Errors
    Debugging the Core
    Margin Check
    Automated Margin Check
    DEBUG_PORT Signals
    Write Init Debug Signals
    Read Stage 1 Calibration Debug Signals
    Read Stage 2 Calibration Debug
    CLOCK_DEDICATED_ROUTE Constraints
    System Clock
    Reference Clock
    Ch. 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
    Introduction
    Using MIG in the Vivado Design Suite
    Customizing and Generating the Core
    MIG Output Options
    Pin Compatible FPGAs
    Creating the 7 Series FPGAs RLDRAM II/RLDRAM 3 Memory Design
    Memory Selection
    Controller Options
    Memory Options
    FPGA Options
    Extended FPGA Options
    Bank Selection
    System Pins Selection
    Summary
    PCB Information
    Design Notes
    Finish
    Vivado Integrated Design Flow for MIG
    Directory Structure and File Descriptions
    Output Directory Structure
    Directory and File Contents
    /example_design/
    /user_design/
    user_design/rtl/controller
    user_design/rtl/ui
    user_design/rtl/phy
    user_design/rtl/xdc
    Verify Pin Changes and Update Design
    Quick Start Example Design
    Overview
    Implementing the Example Design
    Simulating the Example Design (for Designs with the Standard User Interface)
    Traffic Generator Operation
    Modifying the Example Design
    Core Architecture
    Overview
    Client Interface
    Command Request Signals
    Interfacing with the Core through the Client Interface
    Clocking Architecture
    Physical Interface
    Memory Controller
    PHY Architecture
    Write Path
    Output Architecture
    Read Path
    Data Capture
    Calibration
    Calibration of Read Clock and Data
    Implementation Details
    Data Alignment and Valid Generation
    Write Calibration
    Customizing the Core
    Design Guidelines
    Design Rules
    Bank Sharing Among Controllers
    Trace Length Requirements
    Pinout Requirements
    RLDRAM II
    RLDRAM 3
    System Clock, PLL Location, and Constraints
    Configuration
    Termination
    Manual Pinout Changes
    I/O Standards
    Clocking
    Input Clock Guidelines
    Sharing sys_clk between Controllers
    Information on Sharing BUFG Clock (phy_clk)
    Information on Sync_Pulse
    Debugging RLDRAM II and RLDRAM 3 Designs
    Introduction
    Debug Tools
    Example Design
    Debug Signals
    Vivado Design Suite Debug Feature
    Simulation Debug
    Verifying the Simulation Using the Example Design
    Simulation Flow Using IES and VCS Script Files
    Simulation Flow Using Vivado Simulator
    Simulation Flow Using Questa Advanced Simulator
    Simulation Flow Using VCS
    Simulation Flow Using IES
    Memory Initialization
    Calibration
    Test Bench
    Proper Write and Read Commands
    Synthesis and Implementation Debug
    Verify Successful Synthesis and Implementation
    Verify Modifications to the MIG Tool Output
    Identifying and Analyzing Timing Failures
    Hardware Debug
    Clocking
    Verify Board Pinout
    Run Signal Integrity Simulation with IBIS Models
    Run the Example Design
    Debugging Common Hardware Issues
    Isolating Bit Errors
    Debugging the Core
    DEBUG_PORT Signals
    Write Init Debug Signals
    Read Stage 1 Calibration Debug Signals
    Read Stage 2 Calibration Debug
    Write Calibration Debug Map
    Margin Check
    Automated Margin Check
    Debugging Write Calibration
    CLOCK_DEDICATED_ROUTE Constraints
    System Clock
    Reference Clock
    Ch. 4: LPDDR2 SDRAM Memory Interface Solution
    Introduction
    Features
    Using MIG in the Vivado Design Suite
    Customizing and Generating the Core
    MIG Output Options
    Pin Compatible FPGAs
    Creating 7 Series FPGA LPDDR2 SDRAM Memory Controller Block Design
    Memory Selection
    Controller Options
    Create Custom Part
    Setting LPDDR2 SDRAM Memory Parameter Option
    FPGA Options
    Bank Selection
    Summary
    Memory Model License
    PCB Information
    Design Notes
    Vivado Integrated Design Flow for MIG
    Directory Structure and File Descriptions
    Output Directory Structure
    Directory and File Contents
    /example_design/
    example_design/rtl
    example_design/rtl/traffic_gen
    /example_design/par
    /example_design/sim
    /user_design
    user_design/rtl/clocking
    user_design/rtl/controller
    user_design/rtl/ip_top
    user_design/rtl/phy
    user_design/rtl/ui
    /user_design/xdc
    Verify Pin Changes and Update Design
    Quick Start Example Design
    Overview
    Simulating the Example Design (for Designs with the Standard User Interface)
    Traffic Generator Operation
    Modifying the Example Design
    Modifying Port Address Space
    Traffic Generator Signal Description
    Memory Initialization and Traffic Test Flow
    Memory Initialization
    Traffic Test Flow
    Setting Up for Simulation
    Simulation Flow Using IES and VCS Script Files
    Simulation Flow Using Vivado Simulator
    Simulation Flow Using Questa Advanced Simulator
    Simulation Flow Using VCS
    Simulation Flow Using IES
    Core Architecture
    Overview
    User FPGA Logic
    User Interface Block and User Interface
    Memory Controller and Native Interface
    PHY and the Physical Interface
    IDELAYCTRL
    User Interface
    app_addr[ADDR_WIDTH – 1:0]
    app_cmd[2:0]
    app_en
    app_hi_pri
    app_wdf_data[APP_DATA_WIDTH – 1:0]
    app_wdf_end
    app_wdf_mask[APP_MASK_WIDTH – 1:0]
    app_wdf_wren
    app_rdy
    app_rd_data[APP_DATA_WIDTH – 1:0]
    app_rd_data_end
    app_rd_data_valid
    app_wdf_rdy
    app_ref_req
    app_ref_ack
    app_zq_req
    app_zq_ack
    ui_clk_sync_rst
    ui_clk
    init_calib_complete
    User Interface Block
    Native Interface
    Command Request Signals
    accept
    use_addr
    data_buf_addr
    Write Command Signals
    wr_data
    wr_data_addr
    wr_data_mask
    wr_data_en
    wr_data_offset
    Read Command Signals
    rd_data
    rd_data_addr
    rd_data_en
    rd_data_offset
    Native Interface Maintenance Command Signals
    app_ref_req
    app_ref_ack
    app_zq_req
    app_zq_ack
    Clocking Architecture
    Internal (FPGA) Logic Clock
    Write Path (Output) I/O Logic Clock
    Read Path (Input) I/O Logic Clock
    IDELAY Reference Clock
    Memory Controller
    Bank Machines
    Rank Machines
    Column Machine
    Arbitration Block
    Reordering
    Precharge Policy
    PHY
    Overall PHY Architecture
    Memory Initialization and Calibration Sequence
    I/O Architecture
    PHY Control Block
    Command Path
    Datapath
    Calibration and Initialization Stages
    Memory Initialization
    Read Leveling
    Read Valid Calibration
    PRBS Read Leveling
    Phase Detector
    Memory Controller to PHY Interface
    Designing with the Core
    Interfacing to the Core
    User Interface
    Command Path
    Write Path
    Read Path
    User ZQ
    Native Interface
    User ZQ
    Customizing the Core
    Design Guidelines
    LPDDR2 SDRAM
    Design Rules
    Pin Assignments
    Bank and Pin Selection Guides for LPDDR2 Designs
    Bank Sharing Among Controllers
    Pin Swapping
    Internal VREF
    System Clock, MMCM Location, and Constraints
    Configuration
    Termination
    I/O Standards
    Trace Lengths
    Clocking
    Input Clock Guidelines
    Sharing sys_clk between Controllers
    Information on Sharing BUFG Clock (phy_clk)
    Information on Sync_Pulse
    LPDDR2 Pinout Examples
    CLOCK_DEDICATED_ROUTE Constraints
    System Clock
    Reference Clock
    Ch. 5: Multicontroller Design
    Introduction
    Using MIG in the Vivado Design Suite
    Customizing and Generating the Core
    Multiple Controllers
    Creating 7 Series FPGA Multicontroller Block Design
    Memory Selection
    FPGA Options
    Extended FPGA Options Page
    System Clock Pins Selection
    System Clock Sharing
    Vivado Integrated Design Flow for MIG
    Directory Structure
    Ch. 6: Upgrading the ISE/CORE Generator MIG Core in Vivado
    Appx. A: General Memory Routing Guidelines
    Appx. B: Additional Resources and Legal Notices
    Xilinx Resources
    Documentation Navigator and Design Hubs
    References
    Please Read: Important Legal Notices
    Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.2 User Guide UG586 October 4, 2017
    Date Version 10/04/2017 06/07/2017 04/05/2017 4.2 4.2 4.2 11/30/2016 4.1 Revision DDR3 and DDR2 • Updated CLOCK_DEDICATED_ROUTE description in Reference Clock section. Vivado Design Suite release for MIG v4.2. DDR3 and DDR2 • Updated Fig. 1-93 and Fig. 1-94 captions. • Renamed QuestaSim to Questa Advanced Simulator. QDR II+ • Updated qdr_k_n/p directions in Physical Interface Signals table. • Updated in qdr_k_n/p directions I/O Standards table. RLDRAM II/RLDRAM 3 • Updated rld_dk_p/n directions in Physical Interface Signals table. • Updated rld_dk_p/n directions in RLDRAM II I/O Standards and RLDRAM 3 Standards tables. 10/05/2016 4.1 06/08/2016 4.0 04/06/2016 3.0 • Updated to core version 4.1. • Updated file name path to _ex/imports in all sections. DDR3 and DDR2 • Updated Controller Options Page figure. • Added Number of Bank Machines bullet in the Controller Options section. DDR3 and DDR2 • Updated Memory Part description in Controller Option section. • Added app_ecc_single_err[7:0] in Table 1-17: User Interface table. • Added app_ecc_single_err[7:0] and note in Table 1-56: User Interface for ECC Operation. • Updated description in dbg_pi_phase_locked_phy4lanes and dbg_pi_dqs_found_lanes_phy4lanes in Table 1-74: DDR2/DDR3 Debug Signals. • Updated to core version 3.0. • Updated Termination for all sections. • Updated 1.0 µF capacitor in General Memory Routing Guideline chapter. DDR3 and DDR2 • Added note in FPGA Options section. • Added note in Interfacing to the Core section. • Updated sys_rst descriptions in DDR3 and DD2 Configuration sections. • Added note in Debug Signals section. • Updated reset description in General Checks section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.2 UG586 October 4, 2017 www.xilinx.com 2 Send Feedback
    Date Version 11/18/2015 2.4 09/30/2015 2.4 06/24/2015 2.3 Revision • Added asynchronous to sys_rst in all sections. • Added note to RELAXED mode in DDR3/DDR2 and LDDR2 sections. • Updated code in all Configuration sections • Added Important jitter note in Pinout Requirements in all sections. DDR3 and DDR2 • Added Synplify Pro Black Box Testing section. QDR II+ • Updated DEBUG_PORT Signal Descriptions, Write Init Debug Signal Map, and Read Stage 1 Debug Signal Map tables. • Updated Calibration of Read Clock and Data description. • Updated Write Calibration description. RLDRAM II/ RLDRAM 3 • Updated Read Stage 1 Debug Signal Map table. • Updated Calibration of Read Clock and Data description. • Added CLOCK_DEDICATED_ROUTE Constraints in all sections. DDR3 and DDR2 • Updated Trace Lengths section. QDR II+ • Added Termination section. RLDRAM II/ RLDRAM 3 • Added Termination section. • Updated Margin Check section. • Updated Automatic Margin Check section. • Updated Table 3-33: Debug Port Signals. LPDDR2 • Updated Trace Lengths section. Appendix • Added General Memory Routing Guidelines. • Added Simulation Flow Using VCS and IES to all sections. • Added Clocking sections to QDR II+, RLDRAM II/RLDRAM 3, and LPDDR2 chapters. RLDRAM II/ RLDRAM 3 • Added address/control signal and SSI descriptions in Pinout Requirements section. • Updated Input Clock Guidelines section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.2 UG586 October 4, 2017 www.xilinx.com 3 Send Feedback
    Date Version Revision • Updated description in all Configuration sections. • Updated SIM_BYPASS_INIT_CAL. Chapter 1 • Added description in Setting DDR3 Memory Parameter Option section. • Added Note to Answer Record: 54025 in Controller Options section. • Added description to app_rd_data_end in Table 1-17: User Interface. • Updated Table 1-19: AXI4 Slave Interface Parameters. • Updated description in AXI4 Slave Interface Signals section. • Updated Time Division Multiplexing (TDM), Round-Robin, and Read Priority (RD_PRI_REG) sections. • Updated GES description in Calibration Times section. • Updated Fig. 1-50: Clocking Architecture. • Updated Table 1-87: Memory Controller to Calibration Logic Interface Signals. • Updated AXI Addressing section. • Updated Write Path section. • Updated Fig. 1-84: Command Processing. • Updated Physical Layer Interface (Non-Memory Controller Design) section. • Updated CK signal description in Trace Length section. • Updated Fig. 1-93: Calibration Stages. • Updated description in Determine the Failing Calibration Stage section. • Updated Table 1-100: DDR2/DDR3 Debug Signals. • Updated Table 1-102: Debug Signals of Interest for Write Leveling Calibration. • Updated Table 1-103: Debug Signals of Interest for MPR Read Leveling Calibration. • Updated calibration overview in Debugging OCLKDELAYED Calibration Failures section. • Updated Debug bullets in Debugging OCLKDELAYED Calibration Failures section. • Updated Table 1-104: Debug Signals of Interest for OCLKDELAYED Calibration to Table 1-106: Debug Signals of Interest for Read Leveling Stage 1 Calibration. • Updated Table 1-108: Calibration Time in Hardware. • Updated Checking and Varying Read Timing to Manual Window Check sections. • Updated Calibration Times section. Chapter 2 • Updated Fig. 2-43: High-Level PHY Block Diagram for a 36-Bit QDR II+ Interface. • Updated Margin Check and Automated Margin Check sections. Chapter 3 • Updated description in Interfacing with the Core through the Client Interface section. Chapter 4 • Corrected app_wdf_data[APP_DATA_WIDTH – 1:0] and app_wdf_mask[APP_MASK_WIDTH – 1:0] sections. • Updated Fig. 4-43: Clocking Architecture. • Updated Read Path section. 04/01/2015 2.3 Continued Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.2 UG586 October 4, 2017 www.xilinx.com 4 Send Feedback
    Date Version Revision 11/19/2014 2.3 10/01/2014 2.2 Continued Chapter 1 • Updated description in Round-Robin section. • Updated RTT_WR in Table 1-92: 7 Series FPGA Memory Solution Configuration Parameters. • Updated description in Debugging OCLKDELAYED Calibration Failures section. • Updated Table 1-106: Debug Signals of Interest for OCLKDELAYED Calibration. • Updated GES time in Calibration Times section. • Updated bits in left_loss_pb and right_gain_pb in Table 1-109: Debug Signals of Interest for PRBS Read Leveling Calibration. • Global update to example design link in Files in example_design/sim Directory tables, updated links in Simulation Flow Using IES and VCS Script Files section, updated Simulation Flow Using Vivado Simulator section, and updated Simulation Flow Using QuestaSim section. Chapter 1 • Updated Reference Clock description in FPGA Option section. • Updated C_S_AXI_DATA_WIDTH description in Table 1-19: AXI4 Slave Interface Parameters. • Updated Fig. 1-50: Clocking Architecture. • Updated OCLKDELAYED Calibration section. • Updated Write Path section. • Added REF_CLK_MMCM_IODELAY_CTRL in Table 1-92: 7 Series FPGA Memory Solution Configuration Parameters. • Added note for nBANK_MACHS in Table 1-93: Embedded 7 Series FPGAs Memory Solution Configuration Parameters. • Added row and updated Table 1-94: DDR2/DDR3 SDRAM Memory Interface Solution Pinout Parameters • Updated CK/CK# bullet in Trace Length section. • Updated Table 1-102: DDR2/DDR3 Debug Signals. • Updated debug signals in Table 1-112: Debug Signals Used for Checking and Varying Read/Write Timing. Chapter 2 • Added Bank Sharing Among Controllers section in Design Guideline section. Chapter 3 • Added Bank Sharing Among Controllers section in Design Guideline section. Chapter 4 • Updated Figs. 4-57 to 4-59 and Figs. 4-62 to 4-63. • Updated 2:1 description in Write Path section. • Updated rules in Termination section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.2 UG586 October 4, 2017 www.xilinx.com 5 Send Feedback
    Date Version Revision Chapter 1 • Added reference to data sheet in Features section. • Added Important note about Data Mask in Controller Options section. • Added note in Precharge Policy section. • Added PRBS_SADDR_ MASK)POS to Table 1-11: Traffic Generator Parameters Set in the example_top Module. • Updated IDELAYCTRL frequency in IDELAYCTRL section. • Updated IDELAY Reference Clock section. • Updated PRBS Read Leveling section. • Updated CL description for DDR3 in Table 1-93: Embedded 7 Series FPGAs Memory Solution Configuration Parameters. • Updated package length descriptions in Trace Length section. • Added simulation description in Note in Debugging DDR3/DDR2 Designs. • Updated description in Debugging PRBS Read Leveling Failures section. • Updated Table 109: Debug Signals of Interest for PRBS Read Leveling Calibration. Chapter 2 • Added reference to data sheet in Introduction section. • Updated package length descriptions in Trace Length Requirements section. • Added CPT_CLK_SEL_* row in Table 2-11: QDR II+ SRAM Memory Interface Solution Pinout Parameters. • Added simulation description in Note in Debugging QDR II+ Designs. Chapter 3 • Added reference to data sheet in Features section. • Added note in Memory Controller section. • Added PRBS_SADDR_ MASK)POS to Table 3-8: Traffic Generator Parameters Set in the example_top Module. • Updated rules and package length descriptions in Trace Length Requirements section. • Added simulation description in Note in Debugging RLDRAM II and 3 Designs. Chapter 4 • Added note in Precharge Policy section. • Added PRBS_SADDR_ MASK)POS to Table 4-11: Traffic Generator Parameters Set in the example_top Module. • Updated package length descriptions in Trace Length Requirements section. • Added simulation description in Note in Read Path section. 06/04/2014 2.1 Continued Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.2 UG586 October 4, 2017 www.xilinx.com 6 Send Feedback
    Date Version Revision 04/02/2014 2.0 Chapter 1 • Updated book to DQS. • Updated Table 1-4: Files in example_design/sim Directory. • Updated file description in Simulation Flow Using IES and VCS Script Files section. • Added No Buffer description in the System Clock bullet in FPGA Options section. • Updated mc_data_offset description in Memory Controller to Calibration Logic Interface Signals table. • Added MPR read leveling process in Multi-Purpose Register Read Leveling section. • Updated Temperature Monitor section. • Added tempmon information in Physical Layer Interface (Non-Memory Controller Design) section. • Added description in address and control signals in Termination section for DDR3. • Added description in address and control signals and updated CKE signal bullet in Termination section for DDR2. • Added CK description in Trace Lengths section. • Added new code constraints for DDR3/DDR2 Configuration sections. • Added Clocking section. • Updated ocal signals in Table 1-102: DDR2/DDR3 Debug Signals. Chapter 2 • Added new code constraints in Configuration section. • Updated Table 2-3: Files in example_design/sim Directory. • Updated file description in Simulation Flow Using IES and VCS Script Files section. Chapter 3 • Added new code constraints in Configuration section. • Updated Table 3-3: Files in example_design/sim Directory. • Added important note on write and read commands in Interfacing with the Core through the Client Interface section. • Updated option for MRS_RD_LATENCY in RLDRAM II Memory Interface Solution Configurable Parameters table. • Updated file description in Simulation Flow Using IES and VCS Script Files section. Chapter 4 • Added new code constraints in Configuration section. • Updated Table 4-4: Files in example_design/sim Directory. • Updated file description in Simulation Flow Using IES and VCS Script Files section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.2 UG586 October 4, 2017 www.xilinx.com 7 Send Feedback
    Date Version 12/18/2013 2.0 Revision • Vivado Design Suite release only for MIG v2.0. Chapter 1 • Added Out of Context content. • Updated Table 1-4: Modules in example_design/sim Directory. • Updated /user_design section. • Updated Fig. 1-39: Synthesizable Example Design Block Diagram. • Added simulator flows. • Added Bits[39:32] to Table 1-15: Debug Status for the Write Transaction. • Added Bits[39:32] to Table 1-16: Debug Status for the Read Transaction. • Added OOC description in Customizing the Core section. • Added ILA trigger settings in Vivado Lab Tools section. • Added note on read latency in Debug section. • Updated Chipscope triggers to R in Debug section. Chapter 2 • Added Out of Context content. • Updated Table 2-3: Modules in example_design/sim Directory. • Updated /user_design section. • Added OOC description in Customizing the Core section. • Added simulator flows. • Added ILA trigger settings in Vivado Lab Tools section. Chapter 3 • Added Out of Context content. • Updated Table 3-3: Modules in example_design/sim Directory. • Updated /user_design section. • Updated Fig. 3-35: Synthesizable Example Design Block Diagram. • Added OOC description in Customizing the Core section. • Added simulator flows. • Added ILA trigger settings in Vivado Lab Tools section. • Updated Fig. 3-48 Write Path Block Diagram of the RLDRAM II Interface Solution. • Added note on read latency in Debug section. Chapter 4 • Added Out of Context content. • Updated Table 4-4: Modules in example_design/sim Directory. • Updated /user_design section. • Updated Fig. 4-37: Synthesizable Example Design Block Diagram. • Added OOC description in Customizing the Core section. • Added simulator flows. • Added note on read latency in Debug section. Chapter 5 • Added Out of Context content. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.2 UG586 October 4, 2017 www.xilinx.com 8 Send Feedback
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