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USB 3.2最新规范.pdf

发布时间：2022-06-01 发布人：admin 分类：说明书 资料大小：10.02M 资料格式：pdf 举报 版权申诉
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    1 Introduction
    1.1 Background
    1.2 Objective of the Specification
    1.3 Scope of the Document
    1.4 USB Product Compliance
    1.5 Document Organization
    1.6 Design Goals
    1.7 Related Documents
    1.8 Conventions
    1.8.1 Precedence
    1.8.2 Keywords
    1.8.2.1 Informative
    1.8.2.2 May
    1.8.2.3 N/A
    1.8.2.4 Normative
    1.8.2.5 Optional
    1.8.2.6 Reserved
    1.8.2.7 Shall
    1.8.2.8 Should
    1.8.2.9 Numbering
    2 Terms and Abbreviations
    3 Architectural Overview
    3.1 USB 3.2 System Description
    3.1.1 USB 3.2 Mechanical
    3.1.2 USB 3.2 Power
    3.1.3 USB 3.2 System Configuration
    3.1.4 Architectural Differences between USB 3.2 and USB 2.0
    3.2 Enhanced SuperSpeed Bus Architecture
    3.2.1 Physical Layer
    3.2.1.1 Gen 1 Physical Layer
    3.2.1.2 Gen 2 Physical Layer
    3.2.1.3 Dual-Lane Operation
    3.2.2 Link Layer
    3.2.3 Protocol Layer
    3.2.3.1 SuperSpeed Protocol
    3.2.3.2 SuperSpeedPlus Protocol
    3.2.4 Robustness
    3.2.4.1 Error Detection
    3.2.4.2 Error Handling
    3.2.5 Enhanced SuperSpeed Power Management
    3.2.6 Devices
    3.2.6.1 Peripheral Devices
    3.2.6.2 Hubs
    3.2.6.2.1 SuperSpeed Hub
    3.2.6.2.2 SuperSpeedPlus Hub
    3.2.7 Hosts
    3.3 Enhanced SuperSpeed Bus Data Flow Models
    4 Enhanced SuperSpeed Data Flow Model
    4.1 Implementer Viewpoints
    4.2 Enhanced SuperSpeed Communication Flow
    4.2.1 Pipes
    4.3 Enhanced SuperSpeed Protocol Overview
    4.3.1 Differences from USB 2.0
    4.3.1.1 Comparing USB 2.0 and Enhanced SuperSpeed Transactions
    4.3.1.2 Introduction to Enhanced SuperSpeed Packets
    4.4 Generalized Transfer Description
    4.4.1 Data Bursting
    4.4.2 IN Transfers
    4.4.3 OUT Transfers
    4.4.4 Power Management and Performance
    4.4.5 Control Transfers
    4.4.5.1 Control Transfer Packet Size
    4.4.5.2 Control Transfer Bandwidth Requirements
    4.4.5.3 Control Transfer Data Sequences
    4.4.6 Bulk Transfers
    4.4.6.1 Bulk Transfer Data Packet Size
    4.4.6.2 Bulk Transfer Bandwidth Requirements
    4.4.6.3 Bulk Transfer Data Sequences
    4.4.6.4 Bulk Streams
    4.4.7 Interrupt Transfers
    4.4.7.1 Interrupt Transfer Packet Size
    4.4.7.2 Interrupt Transfer Bandwidth Requirements
    4.4.7.3 Interrupt Transfer Data Sequences
    4.4.8 Isochronous Transfers
    4.4.8.1 Isochronous Transfer Packet Size
    4.4.8.2 Isochronous Transfer Bandwidth Requirements
    4.4.8.3 Isochronous Transfer Data Sequences
    4.4.8.4 Special Considerations for Isochronous Transfers
    4.4.8.4.1 Explicit Feedback
    4.4.9 Device Notifications
    4.4.10 Reliability
    4.4.10.1 Physical Layer
    4.4.10.2 Link Layer
    4.4.10.3 Protocol Layer
    4.4.11 Efficiency
    5 Mechanical
    6 Physical Layer
    6.1 Physical Layer Overview
    6.2 Physical Layer Functions
    6.2.1 Measurement Overview
    6.2.2 Channel Overview
    6.3 Symbol Encoding
    6.3.1 Gen 1 Encoding
    6.3.1.1 Serialization and Deserialization of Data
    6.3.1.2 Normative 8b/10b Decode Rules for Gen 1 Operation
    6.3.1.3 Gen 1 Data Scrambling
    6.3.1.4 8b/10b Decode Errors for Gen 1 Operation
    6.3.2 Gen 2 Encoding
    6.3.2.1 Serialization and Deserialization of Data
    6.3.2.2 Normative 128b/132b Decode Rules
    6.3.2.3 Data Scrambling for Gen 2 Operation
    6.3.2.4 128b/132b Decode Errors
    6.3.3 Special Symbols for Framing and Link Management
    6.4 Link Initialization and Training
    6.4.1 Link Training
    6.4.1.1 Gen 1 Operation
    6.4.1.1.1 Normative Training Sequence Rules for Gen 1 Operation
    6.4.1.1.2 Training Control Bits for Gen 1 Operation
    6.4.1.1.3 Training Sequence Values for Gen 1 Operation
    6.4.1.2 Gen 2 Operation
    6.4.1.2.1 Normative Training Sequence Rules for Gen 2 Operation
    6.4.1.2.2 Training Sequence Values for Gen 2 Operation
    6.4.1.2.3 Training Control Bits for Gen 2 Operation
    6.4.1.2.4 Informative Block Alignment for Gen 2 Operation
    6.4.2 Lane Polarity Inversion
    6.4.2.1 Gen 1 Operation
    6.4.2.2 Gen 2 Operation
    6.4.3 Elasticity Buffer and SKP Ordered Set
    6.4.3.1 SKP Rules (Host/Device/Hub) for Gen 1x1 Operation
    6.4.3.2 SKP Rules (Host/Device/Hub) for Gen 1x2 Operation
    6.4.3.3 SKP Rules (Host/Device/Hub) for Gen 2 Operation
    6.4.4 Compliance Pattern
    6.4.4.1 Gen 2 Compliance Pattern CP9
    6.5 Clock and Jitter
    6.5.1 Informative Jitter Budgeting
    6.5.2 Normative Clock Recovery Function
    6.5.3 Normative Spread Spectrum Clocking (SSC)
    6.5.4 Normative Slew Rate Limit
    6.5.5 Reference Clock Requirements
    6.6 Signaling
    6.6.1 Eye Diagrams
    6.6.2 Voltage Level Definitions
    6.6.3 Tx and Rx Input Parasitics
    6.7 Transmitter Specifications
    6.7.1 Transmitter Electrical Parameters
    6.7.2 Low Power Transmitter
    6.7.3 Transmitter Eye
    6.7.4 Tx Compliance Reference Receiver Equalizer Function
    6.7.5 Transmitter De-emphasis
    6.7.5.1 Gen 1 (5GT/sec)
    6.7.5.2 Gen 2 (10GT/sec)
    6.7.6 Entry into Electrical Idle, U1
    6.8 Receiver Specifications
    6.8.1 Receiver Equalization Training
    6.8.2 Informative Receiver CTLE Function
    6.8.2.1 Gen 1 Reference CTLE
    6.8.2.2 Gen 2 Reference Equalizer Function
    6.8.2.2.1 Reference CTLE
    6.8.2.2.2 Reference DFE
    6.8.3 Receiver Electrical Parameters
    6.8.4 Receiver Loopback
    6.8.4.1 Loopback BERT for Gen 1 Operation
    6.8.5 Normative Receiver Tolerance Compliance Test
    6.9 Low Frequency Periodic Signaling (LFPS)
    6.9.1 LFPS Signal Definition
    6.9.2 Example LFPS Handshake for U1/U2 Exit, Loopback Exit, and U3 Wakeup
    6.9.3 Warm Reset
    6.9.4 SuperSpeedPlus Capability Declaration
    6.9.4.1 Binary Representation of Polling.LFPS
    6.9.4.2 SCD1/SCD2 Definition and Transmission
    6.9.5 SuperSpeedPlus LFPS Based PWM Message (LBPM)
    6.9.5.1 Introduction to LFPS Based PWM Signaling (LBPS)
    6.9.5.2 LBPM Definition and Transmission
    6.10 Transmitter and Receiver DC Specifications
    6.10.1 Informative ESD Protection
    6.10.2 Informative Short Circuit Requirements
    6.10.3 Normative High Impedance Reflections
    6.11 Receiver Detection
    6.11.1 Rx Detect Overview
    6.11.2 Rx Detect Sequence
    6.11.3 Upper Limit on Channel Capacitance
    6.12 Re-timers
    6.13 Dual-lane Requirements
    6.13.1 Operation
    6.13.2 Capability Determination
    6.13.3 Lane Numbering
    6.13.4 Data Striping
    6.13.5 Data Scrambling
    6.13.6 Ordered Set Rules
    6.13.7 Lane Polarity Inversion
    6.13.8 Lane-to-Lane Skew
    6.13.9 Compliance Patterns
    6.13.10 Receiver Detection
    6.13.11 Receiver Loopback
    6.13.12 LFPS
    6.13.13 Ux Exit
    7 Link Layer
    7.1 Byte Ordering
    7.1.1 Gen 1 Line Code
    7.1.2 Gen 2 Line Code
    7.2 Link Management and Flow Control
    7.2.1 Packets and Packet Framing
    7.2.1.1 Header Packet Structure
    7.2.1.1.1 Header Packet Framing
    7.2.1.1.2 Packet Header
    7.2.1.1.3 Link Control Word
    7.2.1.2 Data Packet Payload Structure
    7.2.1.2.1 Data Packet Payload Framing
    7.2.1.2.2 Data Packet Payload
    7.2.1.2.3 Data Payload Structure and Spacing between DPH and DPP
    7.2.1.3 Gen 2 Packet Placement
    7.2.2 Link Commands
    7.2.2.1 Link Command Structure
    7.2.2.2 Link Command Word Definition
    7.2.2.3 Link Command Placement
    7.2.3 Logical Idle
    7.2.4 Link Command Usage for Flow Control, Error Recovery, and Power Management
    7.2.4.1 Header Packet Flow Control and Error Recovery
    7.2.4.1.1 Initialization
    7.2.4.1.2 General Rules of LGOOD_n and LCRD_x/LCRD1_x/LCRD2_x Usage
    7.2.4.1.3 Transmitting Packets
    7.2.4.1.4 Deferred DPH
    7.2.4.1.5 Receiving Header Packets
    7.2.4.1.6 Receiving Data Packet Header in Gen 2 Operation
    7.2.4.1.7 SuperSpeed Rx Header Buffer Credit
    7.2.4.1.8 SuperSpeedPlus Type 1/Type 2 Rx Buffer Credit
    7.2.4.1.9 Receiving Data Packet Payload
    7.2.4.1.10 Receiving LGOOD_n
    7.2.4.1.11 Receiving LCRD_x/LCRD1_x/LCRD2_x
    7.2.4.1.12 Receiving LBAD
    7.2.4.1.13 Transmitter Timers
    7.2.4.2 Link Power Management and Flow
    7.2.4.2.1 Power Management Link Timers
    7.2.4.2.2 Low Power Link State Initiation
    7.2.4.2.3 U1/U2 Entry Flow
    7.2.4.2.4 U3 Entry Flow
    7.2.4.2.5 Concurrent Low Power Link Management Flow
    7.2.4.2.6 Concurrent Low Power Link Management and Recovery Flow
    7.2.4.2.7 Low Power Link State Exit Flow
    7.3 Link Error Rules/Recovery
    7.3.1 Overview of Enhanced SuperSpeed Bit Errors
    7.3.2 Link Error Types, Detection, and Recovery
    7.3.3 Link Error Statistics
    7.3.3.1 Link Error Count
    7.3.3.2 Soft Error Count
    7.3.4 Header Packet Errors
    7.3.4.1 Packet Framing Error
    7.3.4.2 Header Packet Error
    7.3.4.3 Rx Header Sequence Number Error
    7.3.5 Link Command Errors
    7.3.6 ACK Tx Header Sequence Number Error
    7.3.7 Header Sequence Number Advertisement Error
    7.3.8 SuperSpeed Rx Header Buffer Credit Advertisement Error
    7.3.9 SuperSpeedPlus Type 1/Type 2 Rx Buffer Credit Advertisement Error
    7.3.10 Training Sequence Error
    7.3.11 Gen 1 8b/10b Errors
    7.3.12 Gen 2x1 Block Header Errors
    7.3.13 Gen 2x2 Block Header Errors
    7.3.14 Summary of Error Types and Recovery
    7.4 PowerOn Reset and Inband Reset
    7.4.1 PowerOn Reset
    7.4.2 Inband Reset
    7.5 Link Training and Status State Machine (LTSSM)
    7.5.1 eSS.Disabled
    7.5.1.1 eSS.Disabled for Downstream Ports and Hub Upstream Ports
    7.5.1.1.1 eSS.Disabled Requirements
    7.5.1.1.2 Exit from eSS.Disabled
    7.5.1.2 eSS.Disabled for Upstream Ports of Peripheral Devices
    7.5.1.2.1 eSS.Disabled Substate Machine
    7.5.1.2.2 eSS.Disabled Requirements
    7.5.1.2.3 Exit from eSS.Disabled.Default
    7.5.1.2.4 Exit from eSS.Disabled.Error
    7.5.2 eSS.Inactive
    7.5.2.1 eSS.Inactive Substate Machines
    7.5.2.2 eSS.Inactive Requirements
    7.5.2.3 eSS.Inactive.Quiet
    7.5.2.3.1 eSS.Inactive.Quiet Requirements
    7.5.2.3.2 Exit from eSS.Inactive.Quiet
    7.5.2.4 eSS.Inactive.Disconnect.Detect
    7.5.2.4.1 eSS.Inactive.Disconnect.Detect Requirements
    7.5.2.4.2 Exit from eSS.Inactive.Disconnect.Detect
    7.5.3 Rx.Detect
    7.5.3.1 Rx.Detect Substate Machines
    7.5.3.2 Rx.Detect Requirements
    7.5.3.3 Rx.Detect.Reset
    7.5.3.3.1 Rx.Detect.Reset Requirements
    7.5.3.3.2 Exit from Rx.Detect.Reset
    7.5.3.4 Rx.Detect.Active
    7.5.3.5 Rx.Detect.Active Requirements
    7.5.3.6 Exit from Rx.Detect.Active
    7.5.3.7 Rx.Detect.Quiet
    7.5.3.7.1 Rx.Detect.Quiet Requirements
    7.5.3.7.2 Exit from Rx.Detect.Quiet
    7.5.4 Polling
    7.5.4.1 Polling Substate Machines
    7.5.4.2 Polling Requirements
    7.5.4.3 Polling.LFPS
    7.5.4.3.1 Polling.LFPS Requirements
    7.5.4.3.2 Exit from Polling.LFPS
    7.5.4.4 Polling.LFPSPlus
    7.5.4.4.1 Polling.LFPSPlus Requirements
    7.5.4.4.2 Exit from Polling.LFPSPlus
    7.5.4.5 Polling.PortMatch
    7.5.4.5.1 PHY Capability LBPM Definition, Rank and Fallback
    7.5.4.5.2 Polling.PortMatch Requirements
    7.5.4.5.3 Exit from Polling.PortMatch
    7.5.4.6 Polling.PortConfig
    7.5.4.6.1 Polling.PortConfig Requirements
    7.5.4.6.2 Exit from Polling.PortConfig
    7.5.4.7 Polling.RxEQ
    7.5.4.7.1 Polling.RxEQ Requirements
    7.5.4.7.2 Exit from Polling.RxEQ
    7.5.4.8 Polling.Active
    7.5.4.8.1 Polling.Active Requirements
    7.5.4.8.2 Exit from Polling.Active
    7.5.4.9 Polling.Configuration
    7.5.4.9.1 Polling.Configuration Requirements
    7.5.4.9.2 Exit from Polling.Configuration
    7.5.4.10 Polling.Idle
    7.5.4.10.1 Polling.Idle Requirements
    7.5.4.10.2 Exit from Polling.Idle
    7.5.5 Compliance Mode
    7.5.5.1 Compliance Mode Requirements
    7.5.5.2 Exit from Compliance Mode
    7.5.6 U0
    7.5.6.1 U0 Requirements
    7.5.6.2 Exit from U0
    7.5.7 U1
    7.5.7.1 U1 Requirements
    7.5.7.2 Exit from U1
    7.5.8 U2
    7.5.8.1 U2 Requirements
    7.5.8.2 Exit from U2
    7.5.9 U3
    7.5.9.1 U3 Requirements
    7.5.9.2 Exit from U3
    7.5.10 Recovery
    7.5.10.1 Recovery Substate Machines
    7.5.10.2 Recovery Requirements
    7.5.10.3 Recovery.Active
    7.5.10.3.1 Recovery.Active Requirements
    7.5.10.3.2 Exit from Recovery.Active
    7.5.10.4 Recovery.Configuration
    7.5.10.4.1 Recovery.Configuration Requirements
    7.5.10.4.2 Exit from Recovery.Configuration
    7.5.10.5 Recovery.Idle
    7.5.10.5.1 Recovery.Idle Requirements
    7.5.10.5.2 Exit from Recovery.Idle
    7.5.11 Loopback
    7.5.11.1 Loopback Substate Machines
    7.5.11.2 Loopback Requirements
    7.5.11.3 Loopback.Active
    7.5.11.3.1 Loopback.Active Requirements
    7.5.11.3.2 Exit from Loopback.Active
    7.5.11.4 Loopback.Exit
    7.5.11.4.1 Loopback.Exit Requirements
    7.5.11.4.2 Exit from Loopback.Exit
    7.5.12 Hot Reset
    7.5.12.1 Hot Reset Substate Machines
    7.5.12.2 Hot Reset Requirements
    7.5.12.3 Hot Reset.Active
    7.5.12.3.1 Hot Reset.Active Requirements
    7.5.12.3.2 Exit from Hot Reset.Active
    7.5.12.4 Hot Reset.Exit
    7.5.12.4.1 Hot Reset.Exit Requirements
    7.5.12.4.2 Exit from Hot Reset.Exit
    8 Protocol Layer
    8.1 Enhanced SuperSpeed Transactions
    8.1.1 Transactions on a SuperSpeed Bus Instance
    8.1.2 Transactions on a SuperSpeedPlus Bus Instance
    8.1.2.1 Simultaneous IN Transactions
    8.1.2.2 Transaction Reordering
    8.2 Packet Types
    8.3 Packet Formats
    8.3.1 Fields Common to all Headers
    8.3.1.1 Reserved Values and Reserved Field Handling
    8.3.1.2 Type Field
    8.3.1.3 CRC-16
    8.3.1.4 Link Control Word
    8.4 Link Management Packet (LMP)
    8.4.1 Subtype Field
    8.4.2 Set Link Function
    8.4.3 U2 Inactivity Timeout
    8.4.4 Vendor Device Test
    8.4.5 Port Capabilities
    8.4.6 Port Configuration
    8.4.7 Port Configuration Response
    8.4.8 Precision Time Measurement
    8.4.8.1 PTM Bus Interval Boundary Counters
    8.4.8.2 LDM Protocol
    8.4.8.2.1 LDM Timestamp Exchange
    8.4.8.2.2 PTM ITP Transfer
    8.4.8.3 LDM State Machines
    8.4.8.3.1 Requester Operation
    8.4.8.3.1.1 Init Request
    8.4.8.3.1.2 Init Response
    8.4.8.3.1.3 Timestamp Request
    8.4.8.3.1.4 Timestamp Response
    8.4.8.3.1.5 LDM Disabled
    8.4.8.3.2 Responder Operation
    8.4.8.3.2.1 Responder Disabled
    8.4.8.3.2.2 Timestamp Request
    8.4.8.3.2.3 Timestamp Response
    8.4.8.4 LDM Link Delay
    8.4.8.4.1 Calculation
    8.4.8.5 PTM Bus Interval Boundary Device Calculation
    8.4.8.6 PTM Bus Interval Boundary Host Calculation
    8.4.8.7 PTM Hub ITP Regeneration
    8.4.8.8 Performance
    8.4.8.9 LDM Rules
    8.4.8.10 LDM and Hubs
    8.4.8.11 Link Delay Measurement (LDM) LMP
    8.5 Transaction Packet (TP)
    8.5.1 Acknowledgement (ACK) Transaction Packet
    8.5.2 Not Ready (NRDY) Transaction Packet
    8.5.3 Endpoint Ready (ERDY) Transaction Packet
    8.5.4 STATUS Transaction Packet
    8.5.5 STALL Transaction Packet
    8.5.6 Device Notification (DEV_NOTIFICATION) Transaction Packet
    8.5.6.1 Function Wake Device Notification
    8.5.6.2 Latency Tolerance Message (LTM) Device Notification
    8.5.6.3 Bus Interval Adjustment Message Device Notification
    8.5.6.4 Function Wake Notification
    8.5.6.5 Latency Tolerance Messaging
    8.5.6.5.1 Optional Normative LTM and BELT Requirements
    8.5.6.6 Bus Interval Adjustment Message
    8.5.6.7 Sublink Speed Device Notification
    8.5.7 PING Transaction Packet
    8.5.8 PING_RESPONSE Transaction Packet
    8.6 Data Packet (DP)
    8.7 Isochronous Timestamp Packet (ITP)
    8.8 Addressing Triple
    8.9 Route String Field
    8.9.1 Route String Port Field
    8.9.2 Route String Port Field Width
    8.9.3 Port Number
    8.10 Transaction Packet Usages
    8.10.1 Flow Control Conditions
    8.10.2 Burst Transactions
    8.10.2.1 Enhanced SuperSpeed Burst Transactions
    8.10.2.2 SuperSpeedPlus Burst Transactions
    8.10.3 Short Packets
    8.10.4 SuperSpeedPlus Transaction Reordering
    8.11 TP or DP Responses
    8.11.1 Device Response to TP Requesting Data
    8.11.2 Host Response to Data Received from a Device
    8.11.3 Device Response to Data Received from the Host
    8.11.4 Device Response to a SETUP DP
    8.12 TP Sequences
    8.12.1 Bulk Transactions
    8.12.1.1 State Machine Notation Information
    8.12.1.2 Bulk IN Transactions
    8.12.1.3 Bulk OUT Transactions
    8.12.1.4 Bulk Streaming Protocol
    8.12.1.4.1 Stream IDs
    8.12.1.4.2 Device IN Stream Protocol
    8.12.1.4.2.1 Disabled
    8.12.1.4.2.2 Prime Pipe
    8.12.1.4.2.3 Deferred Prime Pipe
    8.12.1.4.2.4 Idle
    8.12.1.4.2.5 Start Stream
    8.12.1.4.2.6 Move Data
    8.12.1.4.2.7 INMvData Device
    8.12.1.4.2.8 INMvData Host
    8.12.1.4.2.9 INMvData Device Terminate
    8.12.1.4.2.10 8.12.1.4.2.10 INMvData Burst End
    8.12.1.4.3 Device OUT Stream Protocol
    8.12.1.4.3.1 Disabled
    8.12.1.4.3.2 Prime Pipe
    8.12.1.4.3.3 Deferred Prime Pipe
    8.12.1.4.3.4 Idle
    8.12.1.4.3.5 Start Stream
    8.12.1.4.3.6 Start Stream End
    8.12.1.4.3.7 Move Data
    8.12.1.4.3.8 OUTMvData Device
    8.12.1.4.3.9 OUTMvData Host
    8.12.1.4.3.10 OUTMvData Host Terminate
    8.12.1.4.4 Host IN Stream Protocol
    8.12.1.4.4.1 Disabled
    8.12.1.4.4.2 Prime Pipe
    8.12.1.4.4.3 Idle
    8.12.1.4.4.4 Start Stream
    8.12.1.4.4.5 Move Data
    8.12.1.4.4.6 INMvData Device
    8.12.1.4.4.7 INMvData Host
    8.12.1.4.4.8 INMvData Burst End
    8.12.1.4.4.9 INMvData Device Terminate
    8.12.1.4.5 Host OUT Stream Protocol
    8.12.1.4.5.1 Disabled
    8.12.1.4.5.2 Prime Pipe
    8.12.1.4.5.3 Idle
    8.12.1.4.5.4 Start Stream
    8.12.1.4.5.5 Start Stream End
    8.12.1.4.5.6 Move Data
    8.12.1.4.5.7 OUTMvData Device
    8.12.1.4.5.8 OUTMvData Host
    8.12.1.4.5.9 OUTMvData Host Terminate
    8.12.2 Control Transfers
    8.12.2.1 Reporting Status Results
    8.12.2.2 Variable-length Data Stage
    8.12.2.3 STALL TPs Returned by Control Pipes
    8.12.3 Bus Interval and Service Interval
    8.12.4 Interrupt Transactions
    8.12.4.1 Interrupt IN Transactions
    8.12.4.2 Interrupt OUT Transactions
    8.12.5 Host Timing Information
    8.12.6 Isochronous Transactions
    8.12.6.1 Enhanced SuperSpeed Isochronous Transactions
    8.12.6.1.1 Smart Isochronous Scheduling Protocol
    8.12.6.2 Host Flexibility in Performing SuperSpeed Isochronous Transactions
    8.12.6.3 SuperSpeedPlus Isochronous Transactions
    8.12.6.3.1 Pipelined Isochronous IN Transactions
    8.12.6.4 Host Flexibility in Performing SuperSpeedPlus Isochronous Transactions
    8.12.6.5 Device Response to Isochronous IN Transactions
    8.12.6.6 Host Processing of Isochronous IN Transactions
    8.12.6.7 Device Response to an Isochronous OUT Data Packet
    8.13 Timing Parameters
    9 Device Framework
    9.1 USB Device States
    9.1.1 Visible Device States
    9.1.1.1 Attached
    9.1.1.2 Powered
    9.1.1.2.1 Far-end Receiver Termination Substate
    9.1.1.2.2 Link Training Substate
    9.1.1.3 Default
    9.1.1.4 Address
    9.1.1.5 Configured
    9.1.1.6 Suspended
    9.1.1.7 Error
    9.1.2 Bus Enumeration
    9.2 Generic Device Operations
    9.2.1 Dynamic Attachment and Removal
    9.2.2 Address Assignment
    9.2.3 Configuration
    9.2.4 Data Transfer
    9.2.5 Power Management
    9.2.5.1 Power Budgeting
    9.2.5.2 Changing Device Suspend State
    9.2.5.3 Function Suspend
    9.2.5.4 Changing Function Suspend State
    9.2.6 Request Processing
    9.2.6.1 Request Processing Timing
    9.2.6.2 Reset/Resume Recovery Time
    9.2.6.3 Set Address Processing
    9.2.6.4 Standard Device Requests
    9.2.6.5 Class-specific Requests
    9.2.6.6 Speed Dependent Descriptors
    9.2.7 Request Error
    9.3 USB Device Requests
    9.3.1 bmRequestType
    9.3.2 bRequest
    9.3.3 wValue
    9.3.4 wIndex
    9.3.5 wLength
    9.4 Standard Device Requests
    9.4.1 Clear Feature
    9.4.2 Get Configuration
    9.4.3 Get Descriptor
    9.4.4 Get Interface
    9.4.5 Get Status
    9.4.6 Set Address
    9.4.7 Set Configuration
    9.4.8 Set Descriptor
    9.4.9 Set Feature
    9.4.10 Set Interface
    9.4.11 Set Isochronous Delay
    9.4.12 Set SEL
    9.4.13 Synch Frame
    9.4.14 Events and Their Effect on Device Parameters
    9.5 Descriptors
    9.6 Standard USB Descriptor Definitions
    9.6.1 Device
    9.6.2 Binary Device Object Store (BOS)
    9.6.2.1 USB 2.0 Extension
    9.6.2.2 SuperSpeed USB Device Capability
    9.6.2.3 Container ID
    9.6.2.4 Platform Descriptor
    9.6.2.5 SuperSpeedPlus USB Device Capability
    9.6.2.6 Precision Time Measurement
    9.6.2.7 Configuration Summary Descriptor
    9.6.3 Configuration
    9.6.4 Interface Association
    9.6.5 Interface
    9.6.6 Endpoint
    9.6.7 SuperSpeed Endpoint Companion
    9.6.8 SuperSpeedPlus Isochronous Endpoint Companion
    9.6.9 String
    9.7 Device Class Definitions
    9.7.1 Descriptors
    9.7.2 Interface(s)
    9.7.3 Requests
    9.8 Constants
    10 Hub, Host Downstream Port, and Device Upstream Port Specification
    10.1 Hub Feature Summary
    10.1.1 Connecting to an Enhanced SuperSpeed Capable Host
    10.1.2 Connecting to a USB 2.0 Host
    10.1.3 Hub Connectivity
    10.1.3.1 Routing Information
    10.1.3.2 SuperSpeed Hub Packet Signaling Connectivity
    10.1.3.3 SuperSpeedPlus Hub Packet Routing
    10.1.4 Resume Connectivity
    10.1.5 Hub Fault Recovery Mechanisms
    10.1.6 Hub Buffer Architecture
    10.1.6.1 SuperSpeed Hub Buffer Architecture
    10.1.6.1.1 SuperSpeed Hub Header Packet Buffer Architecture
    10.1.6.1.2 Hub Data Buffer Architecture
    10.1.6.2 SuperSpeedPlus Hub Buffer Architecture
    10.2 Hub Power Management
    10.2.1 Link States
    10.2.2 Hub Downstream Port U1/U2 Timers
    10.2.3 Downstream/Upstream Port Link State Transitions
    10.3 Hub Downstream Facing Ports
    10.3.1 Hub Downstream Facing Port State Descriptions
    10.3.1.1 DSPORT.Powered-off
    10.3.1.2 DSPORT.Disconnected (Waiting for eSS Connect)
    10.3.1.3 DSPORT.Training
    10.3.1.4 DSPORT.ERROR
    10.3.1.5 DSPORT.Enabled
    10.3.1.6 DSPORT.Resetting
    10.3.1.7 DSPORT.Compliance
    10.3.1.8 DSPORT.Loopback
    10.3.1.9 DSPORT.Disabled
    10.3.1.10 DSPORT.Powered-off-detect
    10.3.1.11 DSPORT.Powered-off-reset
    10.3.2 Disconnect Detect Mechanism
    10.3.3 Labeling
    10.4 Hub Downstream Facing Port Power Management
    10.4.1 Downstream Facing Port PM Timers
    10.4.2 Hub Downstream Facing Port State Descriptions
    10.4.2.1 Enabled U0 States
    10.4.2.2 Attempt U0 – U1 Transition
    10.4.2.3 Attempt U0 – U2 Transition
    10.4.2.4 Link in U1
    10.4.2.5 Link in U2
    10.4.2.6 Link in U3
    10.5 Hub Upstream Facing Ports
    10.5.1 Upstream Facing Port State Descriptions
    10.5.1.1 USPORT.Powered-off
    10.5.1.2 USPORT.Powered-on
    10.5.1.3 USPORT.Training
    10.5.1.4 USPORT.Connected/Enabled
    10.5.1.5 USPORT.Error
    10.5.2 Hub Connect State Machine
    10.5.2.1 Hub Connect State Descriptions
    10.5.2.2 HCONNECT.Powered-off
    10.5.2.3 HCONNECT.Attempt ESS Connect
    10.5.2.4 HCONNECT.Connected on ESS
    10.6 Upstream Facing Port Power Management
    10.6.1 Upstream Facing Port PM Timer
    10.6.2 Hub Upstream Facing Port State Descriptions
    10.6.2.1 Enabled U0 States
    10.6.2.2 Attempt U0 – U1 Transition
    10.6.2.3 Attempt U0 – U2 Transition
    10.6.2.4 Link in U1
    10.6.2.5 Link in U2
    10.6.2.6 Link in U3
    10.7 SuperSpeed Hub Header Packet Forwarding and Data Repeater
    10.7.1 SuperSpeed Hub Elasticity Buffer
    10.7.2 SKP Ordered Sets
    10.7.3 Interpacket Spacing
    10.7.4 SuperSpeed Header Packet Buffer Architecture
    10.7.5 SuperSpeed Packet Connectivity
    10.8 SuperSpeedPlus Store and Forward Behavior
    10.8.1 Hub Elasticity Buffer
    10.8.2 SKP Ordered Sets
    10.8.3 Interpacket Spacing
    10.8.4 Upstream Flowing Buffering
    10.8.5 Downstream Flowing Buffering
    10.8.6 SuperSpeedPlus Hub Arbitration of Packets
    10.8.6.1 Arbitration Weight
    10.8.6.2 Direction Independent Packet Selection
    10.8.6.3 Downstream Flowing Packet Reception and Selection
    10.8.6.4 Upstream Flowing Packet Reception and Selection
    10.8.6.4.1 Partially Buffered DP Selection Candidate
    10.8.6.4.2 Upstream Weighted Round Robin Arbitration
    10.8.7 SuperSpeedPlus Upstream Flowing Packet Modifications
    10.8.8 SuperSpeedPlus Downstream Controller
    10.9 Port State Machines
    10.9.1 Port Transmit State Machine
    10.9.2 Port Transmit State Descriptions
    10.9.2.1 Tx IDLE
    10.9.2.2 Tx Header
    10.9.2.3 Tx Data
    10.9.2.4 Tx Data Abort
    10.9.2.5 Tx Link Command
    10.9.3 Port Receive State Machine
    10.9.4 Port Receive State Descriptions
    10.9.4.1 Rx Default
    10.9.4.2 Rx Data
    10.9.4.3 Rx Header
    10.9.4.4 Process Header Packet
    10.9.4.4.1 SuperSpeed Hub Upstream Facing Port
    10.9.4.4.2 SuperSpeedPlus Hub Upstream Facing Port
    10.9.4.4.3 SuperSpeed Hub Downstream Facing Port
    10.9.4.4.4 SuperSpeedPlus Hub Downstream Facing Port
    10.9.4.5 Rx Link Command
    10.9.4.6 Process Link Command
    10.10 Suspend and Resume
    10.11 Hub Upstream Port Reset Behavior
    10.12 Hub Port Power Control
    10.12.1 Multiple Gangs (Only supported for downstream USB Standard-A ports)
    10.13 Hub Controller
    10.13.1 Endpoint Organization
    10.13.2 Hub Information Architecture and Operation
    10.13.3 Port Change Information Processing
    10.13.4 Hub and Port Status Change Bitmap
    10.13.5 Over-current Reporting and Recovery
    10.13.6 Enumeration Handling
    10.14 Hub Configuration
    10.15 Descriptors
    10.15.1 Standard Descriptors for Hub Class
    10.15.2 Class-specific Descriptors
    10.15.2.1 Hub Descriptor
    10.16 Requests
    10.16.1 Standard Requests
    10.16.2 Class-specific Requests
    10.16.2.1 Clear Hub Feature
    10.16.2.2 Clear Port Feature
    10.16.2.3 Get Hub Descriptor
    10.16.2.4 Get Hub Status
    10.16.2.5 Get Port Error Count
    10.16.2.6 Get Port Status
    10.16.2.6.1 Port Status Bits
    10.16.2.6.2 Port Status Change Bits
    10.16.2.6.3 Extended Port Status Bits
    10.16.2.7 Set Hub Descriptor
    10.16.2.8 Set Hub Feature
    10.16.2.9 Set Hub Depth
    10.16.2.10 Set Port Feature
    10.17 Host Root (Downstream) Ports
    10.18 Peripheral Device Upstream Ports
    10.18.1 Peripheral Device Upstream Ports
    10.18.2 Peripheral Device Upstream Port State Machine
    10.18.2.1 USDPORT.Powered-off
    10.18.2.2 USDPORT.Powered on
    10.18.2.3 USDPORT.Training
    10.18.2.4 USDPORT.Connected/Enabled
    10.18.2.5 USDPORT.Error
    10.18.2.6 USDPORT.Disabled
    10.18.2.7 USDPORT.Disabled_Error
    10.19 Hub Chapter Parameters
    11 Interoperability and Power Delivery
    11.1 USB 3.2 Host Support for USB 2.0
    11.2 USB 3.2 Hub Support for USB 2.0
    11.3 USB 3.2 Device Support for USB 2.0
    11.4 Power Distribution
    11.4.1 Classes of Devices and Connections
    11.4.1.1 Self-powered Hubs
    11.4.1.1.1 Over-Current Protection
    11.4.1.2 Low-power Bus-powered Devices
    11.4.1.3 High-power Bus-powered Devices
    11.4.1.4 Self-powered Devices
    11.4.2 Steady-State Voltage Drop Budget
    11.4.3 Power Control During Suspend/Resume
    11.4.4 Dynamic Attach and Detach
    11.4.4.1 Inrush Current Limiting
    11.4.4.2 Dynamic Detach
    11.4.5 Vbus Electrical Characteristics
    A Gen 1 Symbol Encoding
    B Symbol Scrambling
    B.1 Data Scrambling
    C Power Management
    D Example Packets
    E Repeaters
    E.1 Overview
    E.1.1 Term Definitions
    E.1.2 Scope of the Re-time Connectivity and Link Delay Budget
    E.1.2.1 Re-timer Connectivity Models
    E.1.2.1.1 3-Re-timer Connectivity
    E.1.2.1.2 4-Re-timer Connectivity
    E.1.2.2 Link Delay Budget Requirement
    E.1.2.2.1 Gen 1x1 Link Delay Budget
    E.1.2.2.2 Gen 2x1 Link Delay Budget
    E.2 Re-timer Architectural Overview and Requirement
    E.2.1 Architectural Overview
    E.2.2 General Requirements
    E.2.2.1 Physical Layer Requirements
    E.2.2.2 Link Layer Requirements
    E.2.2.3 x2 Re-timer Requirements
    E.3 Re-timer Training and Status State Machine (RTSSM)
    E.3.1 Warm Reset
    E.3.2 Rx.Detect
    E.3.2.1 Rx.Detect Requirements
    E.3.2.2 Exit from Rx.Detect
    E.3.3 eSS.Disabled
    E.3.3.1 eSS.Disabled Requirements
    E.3.3.2 Exit from eSS.Disabled
    E.3.4 Polling
    E.3.4.1 Polling.SpeedDetect
    E.3.4.1.1 Polling.SpeedDetect Requirements
    E.3.4.1.2 Exit from Polling.SpeedDetect
    E.3.4.2 Polling.PortConfig
    E.3.4.2.1 Mechanism for Re-timer Presence Announcement
    E.3.4.2.2 Polling.PortConfig Requirements
    E.3.4.2.3 Exit from Polling.PortConfig
    E.3.4.3 Polling.RxEQ
    E.3.4.3.1 Polling.RxEQ Requirements
    E.3.4.3.2 Exit from Polling.RxEQ
    E.3.4.4 Polling.TSx
    E.3.4.4.1 Mechanism of the Sequential Clock Switching for Cascaded Bit-Level Re-timer
    E.3.4.4.2 Polling.TSx Requirements
    E.3.4.4.3 Exit from Polling.TSx
    E.3.4.5 Polling.Idle
    E.3.4.5.1 Polling.Idle Requirements
    E.3.4.5.2 Exit from Polling.Idle
    E.3.5 Compliance Mode
    E.3.5.1 Compliance Mode Requirements
    E.3.5.2 Exit from Compliance Mode
    E.3.6 BLR Compliance Mode
    E.3.6.1 BLR Compliance Mode Requirements
    E.3.6.2 Exit from BLR Compliance Mode
    E.3.7 U0
    E.3.7.1 U0 Requirements
    E.3.7.2 Exit from U0
    E.3.8 U1
    E.3.8.1 U1 Requirements
    E.3.8.2 Exit from U1
    E.3.9 U2
    E.3.9.1 U2 Requirements
    E.3.9.2 Exit from U2
    E.3.10 U3
    E.3.10.1 U3 Requirements
    E.3.10.2 Exit from U3
    E.3.11 Recovery
    E.3.11.1 Exit from Recovery.TSx
    E.3.11.2 Recovery.TSx
    E.3.11.2.1 Recovery.TSx Requirements
    E.3.11.3 Recovery.Idle
    E.3.11.3.1 Recovery.Idle Requirements
    E.3.11.3.2 Exit from Recovery.Idle
    E.3.12 PassThrough Loopback
    E.3.12.1 PassThrough Loopback Requirements
    E.3.12.2 Exit from PassThrough Loopback
    E.3.13 Local Loopback
    E.3.13.1 Local Loopback Requirements
    E.3.13.2 Exit from Local Loopback.Active
    E.3.13.3 Exit from Local Loopback.Exit
    E.3.14 Hot Reset
    E.3.14.1 Hot Reset Requirements
    E.3.14.2 Exit from Hot Reset
    E.4 SRIS Re-timer Clock Offset Compensation
    E.4.1 Gen 1x1 Operation
    E.4.2 Gen 1x2 Operation
    E.4.3 Gen 2 Operation
    E.5 Bit-Level Re-timer Jitter Transfer Function
    E.6 Compliance
    E.6.1 Host and Device Product Compliance
    E.6.2 Component-Level Re-timer Compliance
    Universal Serial Bus 3.2 Specification Apple Inc. Hewlett-Packard Inc. Intel Corporation Microsoft Corporation Renesas Corporation STMicroelectronics Texas Instruments September 22, 2017 Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
    Revision 1.0 September 22, 2017 Revision History Revision Comments 1.0 1.0 1.0 Initial Release – USB 3.0 Incorporated errata and ECNs Initial Release – USB 3.1 Incorporated errata and ECNs Initial Release – USB 3.2 - ii - Universal Serial Bus 3.2 Specification Issue Date November 12, 2008 June 6, 2011 July 26, 2013 September 22, 2017 September 22, 2017 INTELLECTUAL PROPERTY DISCLAIMER THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO THE USE OR IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. THE PROVISION OF THIS SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS. Please send comments to techsup@usb.org. For industry information, refer to the USB Implementers Forum web page at http://www.usb.org. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright © 2007 – 2017, USB 3.0 Promoter Group (Apple Inc., Hewlett-Packard Inc., Intel Corporation, Microsoft Corporation, Renesas Corporation, STMicroelectronics, and Texas Instruments). Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
    Revision 1.0 September 22, 2017 - iii - Universal Serial Bus 3.2 Specification Acknowledgement of Technical Contribution Dedication Dedicated to the memory of Brad Hosler, the impact of whose accomplishments made the Universal Serial Bus one of the most successful technology innovations of the Personal Computer era . The authors of this specification would like to recognize the following people who participated in the USB 3.2 Bus Specification technical work group. We would also like to acknowledge the many unnamed others throughout the industry who provided feedba ck and contributed to the development of this specification. Apple Inc. – Promoter Company Employees Sree Anantharaman Brian Baek Bill Cornelius Derek Iwamoto Scott Deandrea Scott Jackson Jason Chung William Ferry David Conroy Rhoads Hollowell Reese Schreiber Jennifer Tsai Colin Whitby-Strevens Jeff Wilcox Dan Wilson Hewlett-Packard Inc. – Promoter Company Employees Alan Berkema Norton Ewart Rahul Lakdawala Intel Corporation – Promoter Company Employees Huimin Chen Raul Gutierrez Rahman Ismail Lev Kolomiets Kaleb Ruof Kuan-Yu Chen Howard Heck James Jaussi Christine Krause Zeeshan Sarwar John Crouter Danny Hofshi Vijaykumar Kadgi Yun Ling Benjamin Graniello John Howard Issy Kipnis Viji Ramachandran Brad Saunders Sarah Sharp Amit Srivastava Shankar Subramani David Thompson Karthi Vadivelu Microsoft Corporation – Promoter Company Employees Randy Aull Jayson Kastens Anthony Chen Toby Nixon Vivek Gupta Rahul Ramadas Robbie Harris Yang You Renesas Corporation – Promoter Company Employees Tam Do Kiichi Muto Bob Dunstan Hajime Nozaki Masami Katagiri Philip Leung STMicroelectronics – Promoter Company Employees Jerome Deroo Abdelaziz Goulahsen Benoit Mercier Richard O’Connor Texas Instruments – Promoter Company Employees Mike Campbell Sue Vining Grant Ley Contributor Company Employees Anwar Sadat James Skidmore Aces Electronics Co., Ltd. Jason Chen Andy Feng Acon Glen Chandler Vicky Chuang Sharon Hsiao Advanced Micro Devices Shadi Barakat Jason Hawken Peter Teng Min Wang Walter Fry Yufei Ma Vishant Tyagi Will Harris Joseph Scanlon Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
    Revision 1.0 September 22, 2017 - iv - Universal Serial Bus 3.2 Specification Allion Labs, Inc. Howard Chang John Lin Analogix Semiconductor, Inc. ASMedia Technology Inc. Brian Shih Ke Ma Chin Chang Han Sung Kuo Daniel Wei Stan Lin Greg Stewart Haijian Sui Weber Chuang ShuYu Lin Luke Peng ShengChung Wu Bizlink Technology, Inc. Ted Hsiao Morphy Hsieh Sean O’Neal Cadence Design Systems, Inc. Corning Optical Communications LLC Cosemi Technologies Inc. Harisankar Aravindakshan Jacek Duda Tomasz Klimek Uyen Nguyen Claire Ying Marcin Behrendt Huzaifa Dalal Pawel Eichler John Lupienski Raja Pounraj Dariusz Kaczmarczyk Jie Min Fred Stivers Wojciech Giziewicz Ian McKay Jamie Silva Samir Desai Devang Parekh Cypress Semiconductor Mark Fu Anup Nayak Rushil Kadakia Veerappan Rajaram Dell Inc. Mohammed Hijazi Sean O’Neal Diodes Incorporated Kay Annamalai Jin-sheng Wang Terry Matula Merle Wood Joseph Juan Michael Zhang DisplayLink (UK) Ltd. Pete Burgers Dan Ellis Electronics Testing Center, Taiwan Sophia Liu Michael Miskho Rangarajan Sundaravaradan Marcin Nowak Qun Song Ellisys EverPro Technologies Company, Ltd. FLIR Integrated Imaging Solutions Abel Astley Chuck Trefts Jiang Hui Rick Bogart Mario Pasquali Tom Yang Andrew Fussell Damian Nesbitt Tim Vlaar Foxconn / Hon Hai Fred Fons Decheng Zou Fresco Logic Inc. Tim Barilovits Jie Ni Bob Hall Bob McVay Jeffrey Yang Granite River Labs Mike Engbretson Hirose Electric Junya Doi Terry Little Christopher Meyers Daisuke Kogure William MacKillop Toshiyuki Takada Japan Aviation Electronics Industry Ltd. (JAE) JMicron Technology Corp. William Kysiak Tadashi Ohshida Shigeo Tezuka Kazu Ichikawa Clement Luk Isamu Saito Sid Tono Toshiyuki Moritake Takeharu Naito Mark Saubert Toshio Shimoyama Takamitsu Wada Charon Chen Kevin Liu Hung-Cheng Lo Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
    Revision 1.0 September 22, 2017 Keysight Technologies Inc. - v - Universal Serial Bus 3.2 Specification Biing-Lin Lem Jit Lim Pedro Merlo Roland Scherzinger Dov Yancu LeCroy Corporation Linden Hsu Lenovo Mike Micheletti Tomoki Harada LG Electronics Inc. Do Kyun Kim Daniel H Jacobs Michael Romm Tyler Joe Chris Webb Lotes Co., Ltd. Ariel Delos Reyes Regina Liu-Hwang John Lynch LSI Corporation Harvey Newman Dave Thompson Srinivas Vura Luxshare-ICT Josue Castillo Stone Lin Pat Young MEC IMEX INC – HPT Daniel Chen MegaChips Corporation Satoru Kumashiro Sally Chiu Scott Shuey Alan Kinningham James Stevens Microchip Technology Inc. Mark Bohm Richard Petrie Mick Davis Adriaan Peeters Andrew Rogers Mouli Subramanian MQP Electronics Ltd. Sten Carlsen Nokia Peter Harrison NXP Semiconductors Jason Chen Gerrit den Besten Vijendra Kuroodi Krishnan TN Ahmad Yazdi ON Semiconductor Eduardo De Reza Parade Technologies, Inc. Craig Wiley Anand Kannan Bart Vertenten Qualcomm, Inc. James Goel Karyn Vuong Jin-sheng Wang Realtek Semiconductor Corp. Samsung Electronics Co., Ltd. Terry Lin Cheolyoon Chung Jagoun Koo Cheolho Lee Jun Bum Lee Seagate Technology LLC Alvin Cox Shenzhen Deren Electronics Co., Ltd Michael Morgan Philip Yin Smark Huo Steven Davis Dan Smith Lucy Zhang Sibridge Technologies Bhavesh Desai Kruti Shah Chirag Dhruv Mishith Shukla Specwertz Amanda Hosler Emmanuel Lemay Cuong Tran Dipak Modi Synopsys, Inc. Subramaniam Aravindhan Chandrashekar B U Bala Babu Tektronix, Inc. Total Phase Morton Christiansen Gervais Fong Kevin Heilman Eric Huang Matthew Myers Zongyao Wen Sarah Boen Joshua OBrien Chris Yokum James Mason Behram Minwalla Saleem Mohammad Tri Nguyen John Stonick Keyur Diwan Srikrishna N.H. Egbert Stellinga Noah Zhang Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
    Revision 1.0 September 22, 2017 Tyco Electronics Corp., a TE Connectivity Ltd. company - vi - Universal Serial Bus 3.2 Specification VIA Technologies, Inc. (including VIA Labs, Inc.) Kent Chen Terrance Shih Fong-Jim Wang Rayman Chiu Jay Tseng Ron Liu Wayne Tseng Western Digital, Branded Xiaomi Communications Co., Ltd. Marvin DeForest Larry McMillan Charles Neumann Cristian Roman Del Nido Curtis Stevens Xiaoxing Yang Juejia Zhou Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
    Revision 1.0 September 22, 2017 - vii - Universal Serial Bus 3.2 Specification Contents 1 Introduction ................................................................................................................................................ 1 1.1 Background ...................................................................................................................................... 1 1.2 Objective of the Specification .................................................................................................... 1 1.3 Scope of the Document ................................................................................................................. 2 1.4 USB Product Compliance ............................................................................................................. 2 1.5 Document Organization ............................................................................................................... 2 1.6 Design Goals .................................................................................................................................... 2 1.7 Related Documents........................................................................................................................ 3 1.8 Conventions ..................................................................................................................................... 3 1.8.1 Precedence ....................................................................................................................... 3 1.8.2 Keywords .......................................................................................................................... 3 Informative ........................................................................................................................ 3 1.8.2.1 1.8.2.2 May........................................................................................................................................ 3 1.8.2.3 N/A ........................................................................................................................................ 4 1.8.2.4 Normative .......................................................................................................................... 4 1.8.2.5 Optional .............................................................................................................................. 4 1.8.2.6 Reserved ............................................................................................................................. 4 1.8.2.7 Shall ...................................................................................................................................... 4 1.8.2.8 Should .................................................................................................................................. 4 1.8.2.9 Numbering ......................................................................................................................... 4 2 Terms and Abbreviations ........................................................................................................................ 5 3 Architectural Overview ......................................................................................................................... 15 3.1 USB 3.2 System Description .................................................................................................... 15 3.1.1 USB 3.2 Mechanical ..................................................................................................... 17 3.1.2 USB 3.2 Power .............................................................................................................. 17 3.1.3 USB 3.2 System Configuration ................................................................................. 17 3.1.4 Architectural Differences between USB 3.2 and USB 2.0 ................................ 17 Enhanced SuperSpeed Bus Architecture ............................................................................. 18 Physical Layer .............................................................................................................. 20 3.2.1 3.2.1.1 Gen 1 Physical Layer .................................................................................................. 21 3.2 3.2.1.2 Gen 2 Physical Layer .................................................................................................. 21 3.2.1.3 Dual-Lane Operation .................................................................................................. 22 3.2.2 3.2.3 Link Layer ...................................................................................................................... 22 Protocol Layer .............................................................................................................. 23 3.2.3.1 SuperSpeed Protocol .................................................................................................. 24 3.2.3.2 SuperSpeedPlus Protocol ......................................................................................... 24 3.2.4 Robustness .................................................................................................................... 24 Error Detection ............................................................................................................. 25 3.2.4.1 Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
    Revision 1.0 September 22, 2017 - viii - Universal Serial Bus 3.2 Specification 3.2.4.2 Error Handling .............................................................................................................. 25 3.2.5 Enhanced SuperSpeed Power Management ........................................................ 25 3.2.6 Devices ............................................................................................................................ 26 Peripheral Devices ...................................................................................................... 26 3.2.6.1 3.2.6.2 Hubs................................................................................................................................... 28 3.2.7 Hosts ................................................................................................................................ 30 Enhanced SuperSpeed Bus Data Flow Models ................................................................... 31 3.3 Enhanced SuperSpeed Data Flow Model ......................................................................................... 32 4 4.1 4.2 4.3 Implementer Viewpoints .......................................................................................................... 32 Enhanced SuperSpeed Communication Flow ..................................................................... 32 4.2.1 Pipes ................................................................................................................................ 32 Enhanced SuperSpeed Protocol Overview .......................................................................... 33 4.3.1 Differences from USB 2.0 .......................................................................................... 33 Comparing USB 2.0 and Enhanced SuperSpeed Transactions ................ 34 4.3.1.1 4.3.1.2 Introduction to Enhanced SuperSpeed Packets ............................................. 34 4.4 Generalized Transfer Description ......................................................................................... 35 4.4.1 Data Bursting ................................................................................................................ 36 4.4.2 IN Transfers .................................................................................................................. 36 4.4.3 OUT Transfers .............................................................................................................. 37 4.4.4 Power Management and Performance .................................................................. 38 Control Transfers ........................................................................................................ 39 4.4.5 4.4.5.1 Control Transfer Packet Size .................................................................................. 39 4.4.5.2 Control Transfer Bandwidth Requirements .................................................... 39 4.4.5.3 Control Transfer Data Sequences ......................................................................... 40 4.4.6 Bulk Transfers .............................................................................................................. 40 Bulk Transfer Data Packet Size ............................................................................. 40 4.4.6.1 4.4.6.2 Bulk Transfer Bandwidth Requirements .......................................................... 41 4.4.6.3 Bulk Transfer Data Sequences ............................................................................... 41 4.4.6.4 Bulk Streams .................................................................................................................. 41 4.4.7 Interrupt Transfers ..................................................................................................... 43 4.4.7.1 Interrupt Transfer Packet Size .............................................................................. 44 4.4.7.2 Interrupt Transfer Bandwidth Requirements ................................................ 44 4.4.7.3 Interrupt Transfer Data Sequences ..................................................................... 45 4.4.8 Isochronous Transfers ............................................................................................... 45 4.4.8.1 Isochronous Transfer Packet Size ........................................................................ 46 4.4.8.2 Isochronous Transfer Bandwidth Requirements.......................................... 46 4.4.8.3 Isochronous Transfer Data Sequences .............................................................. 47 4.4.8.4 Special Considerations for Isochronous Transfers ...................................... 47 4.4.9 Device Notifications .................................................................................................... 49 4.4.10 Reliability ....................................................................................................................... 49 Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
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