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IP175G芯片资料.pdf
1 Pin diagram
1.1 IP175G Pin diagram (QFN48)
2 IP175G application diagram
2.1 An 5 TP port switch application
2.2 An 5-port switch mixed with a fiber port
3 Pin description
3.1 Analog pins
3.2 MDI (Media Dependent Interface)
3.3 System clock & reset pins
3.4 Boundry scan & test mode
TEST
3.5 EEPROM interface /SMI (Serial Management interface)
3.6 Miscellaneous setting pins
COS_EN
3.7 LED interface
3.8 Power & ground pads
4 Functional Description
4.1 Switch Engine and Queue Management
4.1.1 Switch Engine
4.1.2 Packet Forwarding
4.1.3 Flow control
4.1.4 Backpressure
4.1.5 Broadcast storm protection
4.2 Rserved Group MAC Address
4.3 Green Power
4.3.1 Auto Power Saving Mode
4.3.2 IEEE802.3az EEE (Energy Efficient Ethernet)
4.3.3 WOL+ (Wake On LAN Plus)
4.4 Force Power Off
4.5 Auto Factory Test (AFT) Mode
4.6 Reset
4.7 Serial management interface
4.8 CoS
4.8.1 Port base priority
4.8.2 Frame base priority
4.8.2.1 VLAN tag and TCP/IP TOS
4.8.2.2 IPv4/IPv6 DiffServ
4.8.2.3 TCP/UDP logical port priority
4.9 Port Mirroring
4.10 Link Aggergation
4.11 Buffer Aging
4.12 PAD Driving Calibration
4.13 Fiber port configuration
5 Register descriptions
5.1 Register map
5.1.1 MII register map
6 PHY registers
6.1 MII Register
6.2 MMD Control Register
6.3 MMD Data Register
6.4 LED mode Control Register
6.5 Register Page mode Control Register
6.6 WOL+ Control Register
6.7 Switch control registers (I)
6.8 Test mode control registers
6.9 Port mirroring control registers
6.10 Debug Register
6.11 Fiber duplex setting registers
6.12 Backpressure setting registers
6.13 TCP/UDP port priority registers
6.14 Test mode
6.15 CoS control registers – port 0
6.16 CoS control registers – port 1
6.17 CoS control registers – port 2
6.18 CoS control registers – port 3
6.19 CoS control registers – port 4
6.20 Switch control registers (IV)
6.21 Reserved Group MAC addresses
6.22 Switch control registers (II)
6.23 EEE Timing Parameter
6.24 WOL (Wake on LAN)
6.25 Link Aggregation
6.26 VLAN Group Control Register
6.26.1 VLAN Classification
6.26.2 VLAN Ingress Rule
6.26.3 Default VLAN Information
6.26.4 VLAN TAG Control Register
6.26.5 Port Based VLAN Member Register
6.26.6 Leaky VLAN Control Register
6.27 VLAN Table
6.27.1 VLAN Control Register
6.27.2 VLAN Identifier Register
6.27.3 VLAN Member Register
7 Electrical Characteristics
7.1 Absolute Maximum Rating
7.2 DC Characteristic
7.3 AC Timing
7.3.1 Power On Sequence and Reset Timing
8 Crystal Specifications
8.1.1 EEPROM Timing
8.1.1.1 Data read cycle
8.1.1.2 Command cycle
8.2 Thermal Data
9 Order Information
10 Package Detail
10.1 48 QFN Outline Dimensions
IP175G
Data Sheet
5 Port 10/100 Ethernet Integrated Switch
(85nm /Extreme Low Power, PWMT® and AFT® )
Features
General Description
IP175G is fabricated with advanced CMOS
(85nm) technology and only requires a 3.3V sinlge
power supply. This feature makes IP175G used
very low power consume, such as the full load
operation (100Mbps full duplex 5 ports), it only
takes 0.45w.
IP175G also supports Power Management Tool
(PWMT®) for IEEE 802.3az, APS, WOL+ and PWD
for Green Power. While two link devices have no
IEEE 802.3az capability, IP175G use WOL+ to
change link from 100Mbps to 10Mbps for saving
power.
The PWD of IP175G is designed for power
down switch immediately by pushing a botton, user
don’t plug out the power adapter. Push the botton
again, it will power on immediately.
Except Low Power and Rich Power Saving
method, IP175G supports AFT® for saving
Customer Testing Cost. By using a push bottom
and cables, IP175G will Auto test completely by
itself.
IP175G/IP175GI are available in 48 QFN lead
free package.
5 port Embedded 10/100 PHY Switch Controller
Support 5 100BaseTX or 4 100Base TX + 1 FX
10M PHY only support 10BaseTe
Support Auto MDI-MDIX function
Power Management Tool (PWMT®)
IEEE 802.3az protocol based power saving
- APS, auto-power saving while Link-off
-
- WOL+®, light traffic power saving
- PWD, force-off power saving
Support Auto Factory Test (AFT®)
Single Power 3.3V supply
Built in 1.1V core voltage LDO Regulator
Two Priority queues per port
Support 802.1p & DiffServ based QoS
QoS
- Port base
- 802.1p
IP DiffServ IPV4/IPV6
-
- TCP/UDP port number
- Pins configure ports priority (VIP port)
Support max forwarding packet length
1552/1536 bytes option
Support port mirror function
Support 1k MAC address
Support broadcast storm protection
Support port trunking (LACP)
Support 16 VLAN (IEEE Std 802.1q)
- Port-based/Tagged-based VLAN
- Support insert, remove tag
Built-in 50 ohm resistors for simplifying BOM
85nm Process
Package and operation temperature
-
-
IP175G: 48 Pin(6mmx6mm) QFN, 0~70℃
IP175GI: 48 Pin(6mmx6mm) QFN, -40~85℃
Application
5 port 10/100 Dumb swith
4TX+1FX Dumb Switcn
Copyright © 2012, IC Plus Corp.
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July 06, 2012
IP175G-DS-R00
IP175G
Data Sheet
Table of Contents
Features..................................................................................................................................................................................1
General Description...............................................................................................................................................................1
Table of Contents...................................................................................................................................................................2
List of Tables...........................................................................................................................................................................4
List of Figures.........................................................................................................................................................................5
Revision History.....................................................................................................................................................................6
1 Pin diagram....................................................................................................................................................................7
1.1
IP175G Pin diagram (QFN48).................................................................................................. 7
IP175G application diagram........................................................................................................................................8
2
2.1 An 5 TP port switch application................................................................................................ 8
2.2 An 5-port switch mixed with a fiber port................................................................................... 8
3 Pin description...............................................................................................................................................................9
3.1 Analog pins .............................................................................................................................. 9
3.2 MDI (Media Dependent Interface)............................................................................................ 9
3.3 System clock & reset pins...................................................................................................... 10
3.4 Boundry scan & test mode..................................................................................................... 10
3.5 EEPROM interface /SMI (Serial Management interface)........................................................11
3.6 Miscellaneous setting pins ..................................................................................................... 12
3.7 LED interface ......................................................................................................................... 13
3.8 Power & ground pads............................................................................................................. 13
4 Functional Description................................................................................................................................................14
4.1 Switch Engine and Queue Management ............................................................................... 14
4.1.1 Switch Engine .............................................................................................................. 14
4.1.2 Packet Forwarding ....................................................................................................... 14
4.1.3 Flow control.................................................................................................................. 14
4.1.4 Backpressure ............................................................................................................... 14
4.1.5 Broadcast storm protection.......................................................................................... 14
4.2 Rserved Group MAC Address................................................................................................ 15
4.3 Green Power .......................................................................................................................... 16
4.3.1 Auto Power Saving Mode ............................................................................................ 16
IEEE802.3az EEE (Energy Efficient Ethernet) ............................................................ 16
4.3.2
4.3.3 WOL+ (Wake On LAN Plus) ........................................................................................ 16
4.4 Force Power Off ..................................................................................................................... 17
4.5 Auto Factory Test (AFT) Mode............................................................................................... 18
4.6 Reset...................................................................................................................................... 18
4.7 Serial management interface ................................................................................................. 19
System diagram...................................................................................................................................................................19
4.8 CoS ........................................................................................................................................ 20
4.8.1 Port base priority.......................................................................................................... 20
4.8.2 Frame base priority ...................................................................................................... 20
4.8.2.1 VLAN tag and TCP/IP TOS................................................................................ 20
4.8.2.2
IPv4/IPv6 DiffServ.............................................................................................. 21
4.8.2.3 TCP/UDP logical port priority............................................................................. 22
4.9 Port Mirroring ......................................................................................................................... 22
4.10 Link Aggergation .................................................................................................................... 23
4.11 Buffer Aging............................................................................................................................ 25
4.12 PAD Driving Calibration.......................................................................................................... 25
4.13 Fiber port configuration .......................................................................................................... 25
5 Register descriptions..................................................................................................................................................26
5.1 Register map.......................................................................................................................... 26
5.1.1 MII register map ........................................................................................................... 26
6 PHY registers ..............................................................................................................................................................27
6.1 MII Register............................................................................................................................ 28
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IP175G-DS-R00
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Copyright © 2012, IC Plus Corp.
IP175G
Data Sheet
6.2 MMD Control Register............................................................................................................ 35
6.3 MMD Data Register................................................................................................................ 35
6.4 LED mode Control Register ................................................................................................... 39
6.5 Register Page mode Control Register ................................................................................... 40
6.6 WOL+ Control Register.......................................................................................................... 40
6.7 Switch control registers (I)...................................................................................................... 42
6.8 Test mode control registers.................................................................................................... 43
6.9 Port mirroring control registers............................................................................................... 44
6.10 Debug Register ...................................................................................................................... 44
6.11 Fiber duplex setting registers................................................................................................. 45
6.12 Backpressure setting registers............................................................................................... 46
6.13 TCP/UDP port priority registers.............................................................................................. 46
6.14 Test mode............................................................................................................................... 47
6.15 CoS control registers – port 0 ................................................................................................ 47
6.16 CoS control registers – port 1 ................................................................................................ 47
6.17 CoS control registers – port 2 ................................................................................................ 47
6.18 CoS control registers – port 3 ................................................................................................ 48
6.19 CoS control registers – port 4 ................................................................................................ 48
6.20 Switch control registers (IV) ................................................................................................... 48
6.21 Reserved Group MAC addresses .......................................................................................... 50
6.22 Switch control registers (II)..................................................................................................... 54
6.23 EEE Timing Parameter........................................................................................................... 55
6.24 WOL (Wake on LAN).............................................................................................................. 56
6.25 Link Aggregation .................................................................................................................... 56
6.26 VLAN Group Control Register................................................................................................ 57
6.26.1 VLAN Classification ..................................................................................................... 57
6.26.2 VLAN Ingress Rule ...................................................................................................... 57
6.26.3 Default VLAN Information ............................................................................................ 58
6.26.4 VLAN TAG Control Register ........................................................................................ 58
6.26.5 Port Based VLAN Member Register ............................................................................ 59
6.26.6 Leaky VLAN Control Register...................................................................................... 59
6.27 VLAN Table ............................................................................................................................ 59
6.27.1 VLAN Control Register................................................................................................. 59
6.27.2 VLAN Identifier Register .............................................................................................. 59
6.27.3 VLAN Member Register ............................................................................................... 60
7 Electrical Characteristics............................................................................................................................................62
7.1 Absolute Maximum Rating ..................................................................................................... 62
7.2 DC Characteristic ................................................................................................................... 62
7.3 AC Timing............................................................................................................................... 63
7.3.1 Power On Sequence and Reset Timing....................................................................... 63
8 Crystal Specifications..................................................................................................................................................63
8.1.1 EEPROM Timing.......................................................................................................... 65
8.1.1.1 Data read cycle.................................................................................................. 65
8.1.1.2 Command cycle ................................................................................................. 65
8.2 Thermal Data.......................................................................................................................... 65
9 Order Information........................................................................................................................................................66
10 Package Detail............................................................................................................................................................67
10.1 48 QFN Outline Dimensions .................................................................................................. 67
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July 06, 2012
IP175G-DS-R00
List of Tables
IP175G
Data Sheet
Table 1 Pin description................................................................................................................ 9
Table 2 Rserved Group MAC Address table.............................................................................15
Table 3 TCP/UDP logical port priority table ..............................................................................22
Table 4 Fiber port Parameter.................................................................................................... 25
Table 5 MII register map table .................................................................................................. 26
Table 6 PHY Register Map ....................................................................................................... 27
Table 7 MMD Control Register table.........................................................................................35
Table 8 MMD Data Register table.............................................................................................35
Table 9 LED mode Control Register table ................................................................................39
Table 10 Register Page mode Control Register table ..............................................................40
Table 11 WOL+ Control Register table .....................................................................................40
Table 12 Switch control registers (I) table.................................................................................42
Table 13 Test mode control registers table ...............................................................................43
Table 14 Port mirroring control registers table..........................................................................44
Table 15 Debug Register table .................................................................................................44
Table 16 Fiber duplex setting registers table............................................................................45
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July 06, 2012
IP175G-DS-R00
List of Figures
IP175G
Data Sheet
Figure 1 Pin Diagram ................................................................................................................. 7
Figure 2 Application Diagram..................................................................................................... 8
Figure 3 WOL+ Application Diagram........................................................................................ 16
Figure 4 Magic Packet Format ................................................................................................. 17
Figure 5 Force Power Off Application Diagram........................................................................ 17
Figure 6 Auto Factory Test Application Diagram ...................................................................... 18
Figure 7 Serial management interface Read / Write Diagram ................................................. 19
Figure 8 VLAN tag and TCP/IP TOS frame.............................................................................. 20
Figure 9 IPv4/IPv6 DiffServ frame............................................................................................ 21
Figure 10 Port Mirroring Security Block Diagram..................................................................... 23
Figure 11 Trunk Channel Behavior Block Diagram .................................................................. 23
Figure 12 Load Balance Block Diagram................................................................................... 24
Figure 13 Fiber FXSD application circuit.................................................................................. 25
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July 06, 2012
IP175G-DS-R00
Revision History
Revision #
Date
IP175G-DS-R01
2012/0706
Initial release
Change Description
IP175G
Data Sheet
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July 06, 2012
IP175G-DS-R00
1
1.1
IP175G
Data Sheet
Pin diagram
IP175G Pin diagram (QFN48)
(6mm X 6mm Top view)
I
/
S
D
_
S
O
C
A
T
A
D
S
0
D
E
L
_
K
N
L
I
/
0
M
O
X
T
0
P
O
X
T
3
3
V
A
0
M
X
R
I
I
0
P
X
R
0
1
V
A
O
D
L
_
D
D
V
P
O
D
L
_
G
E
R
V
D
D
V
D
I
O
D
M
A
D
S
/
C
D
M
L
C
S
/
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
4
9
3
8
3
7
3
TXOM1
TXOP1
RXIM1
RXIP1
BGRES
PLLGND
PLLVCC
RXIP2
RXIM2
TXOP2
TXOM2
AV33
1
2
3
4
5
6
7
8
9
10
11
12
49 E-Pad Ground
36
35
34
33
32
31
30
29
28
27
26
25
LINK_LED1/SCLK/BF_STM_DIS
LINK_LED2/RSVD_GMAC_FILTER
PVDD
LINK LED3
LINK LED4
F_POWER_OFF_LED / VLAN_DIS
AUTO_FACTORY_TEST
TEST
F_POWER_OFF
DVDD
RESETB
FXSD4
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
A
V
1
0
R
X
P
3
I
R
X
M
3
I
T
X
O
P
3
T
X
O
M
3
A
V
3
3
T
X
O
M
4
T
X
O
P
4
R
X
M
4
I
R
X
P
4
I
O
S
C
I
X
2
Exposed pad (pad 49) is system GND, must be soldered to PCB ground plane
Figure 1 Pin Diagram
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July 06, 2012
IP175G-DS-R00
IP175G
Data Sheet
MAC 0
MAC 1 MAC 2 MAC 3 MAC 4 MAC 5 MAC 6 MAC 7
PHY 0
PHY 1 PHY 2 PHY 3 PHY 4 PHY 5 PHY 6 PHY 7
P3
P4
TP
P0
P1
P2
Switch engine
IP175G
IP178G
2
IP175G application diagram
2.1 An 5 TP port switch application
Here shows the application diagram of 5-port switch.
2.2 An 5-port switch mixed with a fiber port
IP178G
IP175G
Switch engine
P0
P1
P2
TP
Figure 2 Application Diagram
MAC 0 MAC 1 MAC 2 MAC 3 MAC 4 MAC 5 MAC 6 MAC 7
PHY 0
PHY 1 PHY 2 PHY 3 PHY 4 PHY 5 PHY 6 PHY 7
P3
P4
Fiber
MAU
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July 06, 2012
IP175G-DS-R00
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