石家庄经济学院
信息工程学院
数字逻辑课程设计报告
题 目 数字锁的设计
姓 名
学 号 407417080213
班 号
2 班
指导老师
邹慧
成 绩
2009 年 6 月
2
目
录
1. 课程设计目的······························································································ 3
2. 开发工具选择······························································································ 3
3. 设计方案 ···································································································3
4. 模块描述····································································································4
5. VHDL 实现································································································· 5
6. 调试仿真······································································································ 6
7. 课程设计回顾总结 ·······················································································8
参 考 文 献 ····································································································8
附录 ·············································································································52
3
一、 课程设计目的:
设计数字锁(即电子密码锁),实现开锁、修改密码等功能。当输入密码正确时,
开锁,当错误时发生警报。
巩固和加深对基础知识的理解,学会设计中小型数字系统的方法,独立完成调试
过程,增强理论联系实际的能力,提高电路设计和分析的能力。
通过实践,理论指导下有所创新,为后继专业课的学习和日后工程实践奠定基础
二、 开发工具:quartus5.1
三、 设计方案:
设计思路图下图所示,整个系统的输入信号有一个时钟脉冲信号 clk,当 clk 为
上升沿时,信号 rst 控制锁内密码(inkey)初始化;输入密码时,与锁内密码比较,
相等时 lt 信号置 1,错误时 lf 信号为 1。如果输入密码正确,给一个信号 rr,使得
锁内密码重置。如果密码输入错误的话,有一个信号 num 控制计数,当 num 输入
超过三次,进入死锁状态。输入密码为八位二进制代码。
4
四、模块描述:
1、锁内密码初始化
if(rst='1') then
inkey<="11111111";
lt<='0';opn<='0';lf<='0';
co<='0';
elsif(clk'event and clk='1') then
2、重置密码:
if(cc='1' and
opn='1') then
lt<='0';lf<='0';opn<='1';
co<='1';
elsif (cc='0' ) then
co<='0';
end if;
3、密码比较
if(st='1') then
if(inkey=key) then
lt<='1';
lf<='0';
opn<='1';
else lf<='1';
lt<='0';
opn<='0';
end if;
end if;
判断密码正确
lt 灯亮
开锁,信号置 1
密码错误,报警信号 lf 置 1
不开锁,信号置 0
5
五、 vhdl 语言实现:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity
suo is
port(key:in std_logic_vector(7 downto 0);
lt,lf:out std_logic;
rst,cc,clk:in std_logic;
opn:buffer std_logic);
suo;
suo is
end
architecture be_suo of
signal inkey:std_logic_vector(7 downto 0);
signal num:std_logic_vector(1 downto 0);
signal co,st,aa:std_logic;
begin
process(key,num,inkey,co,st,rst,clk)
begin
if(rst='1') then
inkey<="11111111";
lt<='0';opn<='0';lf<='0';
co<='0';
elsif(clk'event and clk='1') then
if(co='1') then
inkey<=key;
lt<='0';opn<='0';lf<='0';
st<='0';
else
st<='1';
lt<='1';opn<='0';lf<='0';
end if;
if(st='1') then
if(inkey=key) then
lt<='1';
opn<='1';
lf<='0';
else lf<='1';
lt<='0';
opn<='0';
end if;
6
if(cc='1' and
opn='1') then
lt<='0';lf<='0';opn<='1';
co<='1';
elsif (cc='0' ) then
co<='0';
end if;
else lt<='0';lf<='0';opn<='1';
end if;
end if;
end process;
end be_suo;
六、 调试仿真
密码正确和错误时的仿真图:
重置密码的仿真图:
7
完整的仿真图:
8
七、课程设计回顾总结:
这次数字逻辑课程设计,让我从中受益匪浅。课程学习过程中学到的真是很浅显,构思程序流程图
时涉及了好多我们以前没有想到过、遇到过的问题,经过这两周的学习,我对 vhdl 有了更深的理解。
在写数字锁的程序时,我发现了好多不理解的问题,例如,1、语句时自上向下执行的,但是当下面
有信号要返到上面寻找时,从哪里开始找,现在我知道是从他的最外层控制信号开始。2、结构体中
定义的信号量,在定义时不能直接赋值,因为 quartus 在运行时不识别这些赋值语句。3、我的数字
锁中用到了计数器,程序中计数器的描述,以及锁内密码需要存储,在程序中如何实现存储和重置。
4、重新认识了时钟脉冲信号,它的使用。以及进程的作用,他们在程序中的作用,对 vhdl 语言的
结构更加清晰。……
总之通过这次课程设计,能够掌握对 vhdl 语言的错误语言的修改,即调试。能够写一些简单的小程
序。
参考文献:
张兴忠 阎宏印 武淑红:数字逻辑与数字系统
侯伯亨 顾新:VHDL 硬件描述语言与数字逻辑电路设计——电子工程师必备知识(电子
版)