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Top Down Digital VLSI Design From Architectures .pdf
Top-Down Digital VLSI Design: From Architectures to Gate-Level Circuits and FPGAs
Copyright
Preface
Why this book
Highlights
Notes to Instructors
Acknowledgments
Introduction to Microelectronics
Economic Impact
The Guinness Book of Records Point of View
The Marketing Point of View
The Fabrication Point of View
Full-custom ICs
Field-programmable logic
Standard parts
The Design Engineer's Point of View
Cell libraries and schematic entry
Automatic circuit synthesis
Design with virtual components
Electronic system-level ESL design automation
The Y-chart, a Map of Digital Electronic Systems
Field-Programmable Logic
General Idea
Configuration Technologies
Static Memory
Flash Memory
Antifuses
Organization of Hardware Resources
Simple Programmable Logic Devices SPLD
Complex Programmable Logic Devices CPLD
Field-Programmable Gate Arrays FPGA
Commercial Aspects
An Overview on FPL Device Families
The Price and the Benefits of Electrical Configurability
Extensions of the Basic Idea
The FPL Design Flow
Conclusions
From Algorithms to Architectures
The Goals of Architecture Design
The Antipodes
What Makes an Algorithm Suitable for a Dedicated VLSI Architecture?
Assemblies of General-Purpose and Dedicated Processing Units
Extendable Instruction set Processors
Platform ICs DSPP
Digest
There is Room for Remodeling in the Algorithmic Domain ...
Systems Engineers and VLSI Designers Must Collaborate
Relative Merits of Architectural Alternatives
Computation Cycle Versus Clock Period
Common Assumptions
Iterative Decomposition
Pipelining
Replication
Performance and cost analysis
Performance and cost analysis
Associativity Transform
Digest
Data Access Patterns
Wiring and the Costs of Going Off-Chip
Digest
Retiming
Iterative Decomposition and Time Sharing Revisited
Replication Revisited
The Feedback Bottleneck
Unfolding of First-Order Loops
Performance and cost analysis
Higher-Order Loops
Performance and cost analysis
Time-Variant Loops
Nonlinear or General Loops
Generalization to other Levels of Detail
Architecture level
Bit level
Bit-Serial Architectures
Distributed Arithmetic
Generalization to other Algebraic Structures
Finite fields
Semirings
Conclusions
The Grand Architectural Alternativesfrom an Energy Point of View
A Guide to Evaluating Architectural Alternatives
Examples with two operations
Circuit Modeling with HDLs
Motivation and Background
Why Hardware Synthesis?
Alternatives for Modeling Digital Hardware
Why Bother Learning Hardware Description Languages?
A First Look at VHDL and SystemVerilog
Circuit Hierarchy and Connectivity
How to compose a circuit from components
Interacting Concurrent Processes
How to describe a register behaviorally
How to model three-state outputs and busses
Selecting adequate data types
An Event-Driven Scheme of Execution
How to safely code sequential circuits for synthesis
How to check timing conditions
Facilities for Model Parametrization
Concepts Borrowed from Programming Languages
Circuit Hierarchy and Connectivity
How to describe combinational logic behaviorally
How to describe a register behaviorally
How to check timing conditions
Facilities for Model Parametrization
Concepts Borrowed from Programming Languages
Synthesis Overview
Finite State Machines and Sequential Subcircuits in General
Explicit versus implicit state models
How to capture a finite state machine
How to formulate timing constraints
How to partition a circuit in view of synthesis and optimization
Some circuits essentially need to be defined as gate-level netlists
How to Establish a Register Transfer Level Model Step by Step
Protected Shared Variables IEEE 1076a
Functional Verification
Goals of Design Verification
Rapid Prototyping
Hardware-Assisted Verification
A First Glimpse at VLSI Testing
Fully Automated Response Checking is a Must
Exhaustive Verification Remains an Elusive Goal
Directed Verification is Indispensable but has its Limitations
Monitoring toggle counts is of limited use
Automatic test pattern generation does not help either
Monitoring code coverage helps but does not suffice
Routine is the dark side of experience
Directed Random Verification Guards Against Human Omissions
Collecting Test Cases from Multiple Sources Helps
A Coherent Schedule for Simulation and Test
Calculating High-Level Figures of Merit
Patterning Simulation Set-Ups after the Target System
Initialization
Trimming Run Times by Skipping Redundant Simulation Sequences
Modularity and Reuse are the Keys to Testbench Design
Equivalence checking
Deductive verification or model proving
External timing requirements imposed by a model under test MUT
Precedence relations captured in a constraint graph
Solving the constraint graph
Anceau diagrams help visualize periodic events and timing
The Case for Synchronous Design
Introduction
The Grand Alternatives for Regulating State Changes
Synchronous Clocking
Asynchronous Clocking
Self-Timed Clocking
The Pros and Cons of Synchronous Clocking
Clock-as-Clock-Can is not an Option in VLSI
Fully Self-Timed Clocking is not Normally an Option Either
Hybrid Approaches to System Clocking
First Guiding Principle: Dissociate Signal Classes!
Synchronous Design Rules at a More Detailed Level
Unclocked bistables prohibited
Zero-latency loops prohibited
Monoflops, one-shots, edge detectors and clock chopping prohibited
Clock and reset signals to be distributed by fanout trees
Beware of unsafe clock gates
Bistables with both asynchronous reset and preset inputs prohibited
Signal Class
Three-State Capability
Present State vs. Next State
Signal Naming Convention Syntax
A Note on the Portability of Names Across EDA Platforms
Clocking of Synchronous Circuits
What is the Difficulty With Clock Distribution?
Timing Quantities Related to Clock Distribution
Basics
Single-Edge-Triggered One-Phase Clocking
Hardware resources and operation principle
Detailed analysis
Implications
Symmetric Level-Sensitive Two-Phase Clocking
Hardware resources and operation principle
Unsymmetric Level-Sensitive Two-Phase Clocking
Hardware resources and operation principle
Detailed analysis
Implications
Single-Wire Level-Sensitive Two-Phase Clocking
Hardware resources and operation principle
Implications
Detailed analysis
Clock Waveforms
Collective Clock Buffers
Hybrid Clock Distribution Networks
Friendly as Opposed to Unfriendly I/O Timing
Registered Inputs and Outputs
Adding Artificial Contamination Delay to Data Inputs
Traditional Feedback-Type Registers with Enable
A Crude and Unsafe Approach to Clock Gating
A Simple Clock Gating Scheme that May Work Under Certain Conditions
Acquisition of Asynchronous Data
Motivation
Plain Bit-Parallel Synchronization
Unit-Distance Coding
Suppression of Jumbled Data Patterns
Handshaking
Partial Handshaking
No Synchronization Whatsoever
Synchronization From a Slow Clock
Metastability and How it Becomes Manifest
Plesiochronous Interfaces
Elementary Digital Electronics
Introduction
Floating Point Number Formats
Notational Conventions for Two-Valued Logic
Truth Table
The n-Cube
Karnaugh Map
Two-Level Logic
Sum-of-products
Product-of-sums
Symmetric and Monotone Functions
Threshold Functions
Complete Gate Sets
Logic Minimization
Metrics for logic complexity and implementation costs
Minimal versus unredundant expressions
Multi-level versus two-level logic
Random Logic
Programmable Logic Array PLA
Digest
Flip-Flops or Edge-Triggered Bistables
The data or D-type flip-flop
Latches or Level-Sensitive Bistables
The data or D-type latch
The SR-seesaw
The edge-triggered SR-seesaw
The Muller-C element
Glitches, a Phenomenological Perspective
Function Hazards, a Circuit-Independent Mechanism
Digest
Delay Parameters Serve for Combinational and Sequential Circuits
Timing Constraints Address Synthesis Needs
Summary
Finite State Machines
Abstract Automata
Mealy Machine
Moore Machine
Relationships Between Finite State Machine Models
Equivalence of Mealy and Moore machines in the context of hardware design
Taxonomy of Finite State Machines
Parasitic States and Symbols
Mealy-, Moore-, Medvedev-Type, and Combinational Output Bits
Through Paths and Logic Instability
Concurrency, hierarchy and modularity are key to efficiency
State reduction
State encoding
Summary
Symbols and Constants
Abbreviations
Mathematical Symbols
Physical and Material Constants
A note on carbon allotropes
Bibliography
Index
Symbols
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
Top-Down Digital
VLSI Design
Top-Down Digital
VLSI Design
From Architectures
to Gate-Level Circuits and FPGAs
Hubert Kaeslin
Microelectronics Design Center
Department of Information Technology and Electrical Engineering
ETH Zürich
Switzerland
AMSTERDAM BOSTON HEIDELBERG LONDON
NEW YORK OXFORD PARIS SAN DIEGO
SAN FRANCISCO SINGAPORE SYDNEY TOKYO
Morgan Kaufmann is an imprint of Elsevier
Acquiring Editor: Stephen Merken
Editorial Project Manager: Nate McFadden
Project Manager: Poulouse Joseph
Cover Designer: Maria Inês Cruz
Morgan Kaufmann is an imprint of Elsevier
225 Wyman Street, Waltham, MA 02451, USA
Copyright © 2015 Published by Elsevier Inc. All rights reserved.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
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Center and the Copyright Licensing Agency, can be found at our website: www.elsevier.com/permissions.
This book and the individual contributions contained in it are protected under copyright by the Publisher (other
than as may be noted herein).
Notices
Knowledge and best practice in this field are constantly changing. As new research and experience broaden our
understanding, changes in research methods, professional practices, or medical treatment may become necessary.
Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using
any information, methods, compounds, or experiments described herein. In using such information or methods
they should be mindful of their own safety and the safety of others, including parties for whom they have a
professional responsibility.
To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability
for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or
from any use or operation of any methods, products, instructions, or ideas contained in the material herein.
Library of Congress Cataloging-in-Publication Data
Kaeslin, Hubert, author.
Top-down digital VLSI design : from architectures to gate-level circuits and FPGAS / Hubert Kaeslin,
Microelectronics Design Center, Dept. of Information Technology and Electrical Engineering,
ETH Zurich, Switzerland.
pages cm
ISBN 978-0-12-800730-3
1. Digital integrated circuits–Design and construction. 2. Integrated circuits–Very large scale
integration–Design and construction. I. Title.
TK7874.65.K336 2015
621.39
5–dc23
British Library Cataloguing in Publication Data
A catalogue record for this book is available from the British Library
ISBN: 978-0-12-800730-3
For information on all MK publications
visit our website at www.mkp.com
2014035133
Preface
WHY THIS BOOK?
Designing integrated electronics has become a multidisciplinary enterprise that involves solving
problems from fields as disparate as
• Hardware architecture
Software engineering
Marketing and investment
Semiconductor physics
Systems engineering and verification
Circuit design
Discrete mathematics
Layout design
Electronic design automation
Hardware test equipment and measurement techniques
Covering all these subjects is clearly beyond the scope of this text and also beyond the author’s
proficiency. Yet, I have made an attempt to collect material from the above fields that I have found
to be relevant for making major design decisions and for carrying out the actual engineering work
when developing Very Large Scale Integration (VLSI) circuits.
The present volume covers front-end design, that is all steps required to turn a software model into a
gate-level netlist or, alternatively, into a bit stream for configuring field-programmable logic devices.
A second volume on back-end design may follow at a later date.
The text has been written with two audiences in mind. As a textbook, it wants to introduce engineering
students to the beauty and the challenges of digital VLSI design while preventing them from repeating
mistakes that others have made before. Practising electronics engineers should find it appealing as a
reference book because of the many tables, checklists, diagrams, and case studies intended to help
them not to overlook important action items and alternative options when planning to develop their
own circuits.
What sets this book apart from others in the field is its top-down approach. Beginning with hardware
architectures, rather than with solid-state physics, naturally follows the normal VLSI design flow and
makes the material more accessible to readers with a background in systems engineering, information
technology, digital signal processing, or management.
xv
xvi
Preface
HIGHLIGHTS
Top-down approach.
Systematic overview on architecture optimization techniques.
A chapter on field-programmable logic devices, their technologies and architectures.
Key concepts behind both VHDL and SystemVerilog without too many syntactical details.
A proven naming convention for signals and variables.
Introduction to assertion-based verification.
Concepts for re-usable simulation testbenches.
Emphasis on synchronous design and HDL code portability.
Comprehensive discussion of clocking disciplines.
Largely self-contained (required previous knowledge summarized in two appendices).
Emphasis on knowledge likely to remain useful in the years to come.
Plenty of detailed illustrations.
Checklists, hints and warnings for various situations.
A concept proven in classroom teaching and actual design projects.
NOTES TO INSTRUCTORS
Over the past decade, the capabilities of Field-Programmable Gate Arrays (FPGA) have grown to a point
where they compete with custom-fabricated ICs in many electronic designs, especially for products
marketed by small and medium enterprises.
Beginning with the higher levels of abstraction enables instructors to focus on those topics that are
equally relevant irrespective of whether a design eventually gets implemented as “mask-programmed”
chip or from components that are configured electrically. That material is collected in chapters 1 to 6
of the book and best taught as part of a Bachelor program for maximum dissemination. No prior
introduction to semiconductor physics or devices is required. For audiences with little exposure to
digital logic and finite state machines, the material can always be complemented with appendices A
and B.
Chapter 7 is the only one to have a clear orientation towards mask-programmed circuits as clocking and
clock distribution are largely pre-defined in field-programmable logic devices. As opposed to this, the
material on synchronization in chapter 8 is equally important to FPGA users and to persons specializing
in full- or semi-custom design.
Probably the best way of preparing for an engineering career in the electronics and microelectronics
industry is to complete a design project where circuits are not just being modeled and simulated on
a computer but actually fabricated and tested. At ETH Zürich, students are given this opportunity as
part of a three-semester course given by the author and his colleagues, see figure below. The 6th term
covers front-end design. Building a circuit of modest size with an FPGA is practiced in a series of
exercises. Provided they come up with a meaningful proposal, students then get accepted for a much
more substantial project that runs in parallel with their regular lectures and exercises during the 7th term.
Preface
xvii
Typically working in teams of two, students are expected to devote at least half of their working time
to that project. Following tapeout at the end of the term, chip fabrication via an external multi-project
wafer service roughly takes three months. Circuit samples then get systematically tested by their very
developers in the 8th and final term. Needless to say that students accepting this offer feel very motivated
and that industry highly values the practical experience of graduates formed in this way.
Most chapters in this book come with student problems. Some of them expose ideas left aside in the
main text for the sake of conciseness. Problems are graded as a function of the effort required to solve
them.
∗ A few thoughts lead to a brief answer.
∗∗ Details need to be worked out, count between 20 min and 90 min.
∗∗∗ A small engineering project, multiple solutions may exist. Access to EDA and other computer
tools may help.
Solutions and presentation slides are available to instructors who register with the publisher from the
book’s companion website http://booksite.elsevier.com/9780128007303.
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e
f
a
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Syllabus of ETH Zurich in
Digital VLSI Design and Test
Degree
Bachelor
Microelectronics Design Center
Prof. Hubert Kaeslin
Integrated Systems Laboratory
Dr. Norbert Felber
Master
Calendar
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
Jan
Feb
Mar
Apr
May
Specials
Lectures
6th term
student projects
✰
7th term
✰
low pwr research
8th term
industry
✰
VLSI I:
Architectures of VLSI Circuits
VLSI II:
Design of VLSI Circuits
VLSI III: Fabrication and
Testing of VLSI Circuits
Key topics
top
✦ Architecture design
✦ HW Description Languages
✦ Functional verification
✦ Clocking & synchronization
✦ Back-end design
✦ Parasitic effects
✦ VLSI economics
✦ VLSI testing
✦ CMOS fabrication
✦ Technology outlook
down
Exercises
From VHDL to FPGA
IC design through to final layout
Testing of fabricated ICs
Student project
(optional)
Milestones
hk 16.1.2014
Speci-
fication
Modeling
Circuit design
Fabrication on MPWs
Testing
accepted
proposal
software
model
overall
architecture
synthesis
model
verified
netlist
verified
layout,
project report
test vectors
test report
Acknowledgments
This text collects the insight and the experience that many persons have accumulated over more than
twenty years. While I was fortunate enough to author the book, I am indebted to all those who have
been willing to share their expertise with me.
My thanks thus go to many past and present colleagues of mine including Christoph Balmer,
David Bellasi, Prof. Andreas Burg, Dr. Felix Bürgin, Dr. Norbert Felber, Prof. em. Wolfgang Fichtner,
Michael Gautschi, Dr. Pierre Greisen, Dr. Frank Gürkaynak, Christoph Keller, Prof. Mathieu Luisier,
Dr. Patrick Mächler, Beat Muheim, Michael Mühlberghuber, Michael Schaffner, Prof. Christoph Studer,
Prof. Jürgen Wassner, Dr. Markus Wenk, Prof. Paul Zbinden, and Dr. Reto Zimmermann. As long-time
VHDL users, our staff and me are grateful to Dr. Christoph Sühnel who made us become fluent in
SystemVerilog with as few detours and misunderstandings as possible. Most of these experts have
contributed examples, have reviewed parts of my manuscript, or have otherwise helped improve its
quality. Still, the only person to blame for all errors and other shortcomings that have remained in the
text is me.
Next, I would like to extend my sincere thanks to all students who have followed our courses on Digital
VLSI Design and Test. Not only their comments and questions, but also results and data from many of
their projects have found their way into this text. Sebastian Axmann deserves special credit for helping
with the solutions on a voluntary basis.
Giving students the opportunity to design microchips, to have them fabricated, and to test physical
samples is a rather onerous undertaking that would clearly have been impossible without the continuous
funding by ETH Zürich. Let me express our gratitude for that on behalf of all our graduates.
In cooperation with Christoph Wicki and his IT support team, the staff of the local Microelectronics
Design Center does a superb job in setting up and maintaining the EDA infrastructure and the services
indispensable for VLSI design in spite of the frequent landslides caused by rapid technological evolution
and by unforeseeable business changes. I am particularly grateful to them for occasionally filling all
sorts of gaps in my technical knowledge without making me feel too badly about it.
I am further indebted to Todd Green, Nate McFadden, Poulouse Joseph, and many more members of
the staff at Morgan Kaufmann Publishers for their support with turning my LaTeX manuscript into a
printed book. Finally, I would like to thank all persons and organizations who have taken their time to
answer my reprint requests and who have granted me the right to reproduce illustrations of theirs.
xix
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