DSP的EMIF接口使用手册.pdf

发布时间：2022-06-14 发布人：admin 分类：说明书资料大小：0.74M 资料格式：pdf 举报版权申诉

52fc8361-5cef-402c-8642-0d787f03d152.pdf-第1页.png

第1页 / 共70页

52fc8361-5cef-402c-8642-0d787f03d152.pdf-第2页.png

第2页 / 共70页

52fc8361-5cef-402c-8642-0d787f03d152.pdf-第3页.png

第3页 / 共70页

52fc8361-5cef-402c-8642-0d787f03d152.pdf-第4页.png

第4页 / 共70页

52fc8361-5cef-402c-8642-0d787f03d152.pdf-第5页.png

第5页 / 共70页

52fc8361-5cef-402c-8642-0d787f03d152.pdf-第6页.png

第6页 / 共70页

52fc8361-5cef-402c-8642-0d787f03d152.pdf-第7页.png

第7页 / 共70页

52fc8361-5cef-402c-8642-0d787f03d152.pdf-第8页.png

第8页 / 共70页

文本预览

Application Report SPRA433B - December 2001 Kyle Castille TMS320C6000 EMIF-to-External SDRAM Interface Digital Signal Processing Solutions ABSTRACT Interfacing external SDRAM to the Texas Instruments TMS320C6000 digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variety of external memory devices. This application report describes the EMIF’s control registers and SDRAM signals along with SDRAM functionality, including functions supported by the EMIF and performance considerations when used with the EMIF. General examples include several SDRAM configurations supported by the EMIF, including timing analysis. In addition, specific examples are provided using Micron SDRAM. 1 2 Interface of C6000 EMIF With SDRAM 1.1 C620x/C670x Compatible Memory Types 1.2 C621x/C671x Compatible Memory Types 1.3 C64x Compatible Memory Types 1.4 C6000 EMIF-to-SDRAM Physical Interface Overview of the C6000 EMIF 2.1 C620x/C670x SDRAM Interface Summary 2.2 C6211/C6711 SDRAM Interface Summary 2.3 C64x SDRAM Interface Summary 2.4 C6000 EMIF Signal Descriptions 2.4.1 C6211/C6711 Byte-Lane Alignment 2.4.2 C64x Byte-Lane Alignment 2.4.3 C6211/C6711/C64x Clocking 2.4.4 C6000 Clock-to-Output Relationship Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 8 10 15 15 15 16 16 21 21 22 23 24 24 25 26 28 29 30 2.5 C6000 EMIF Registers 2.5.1 EMIF Global Control Register 2.5.2 CE Space Control Registers 2.5.3 SDRAM Control Register (SDCTL) 2.5.4 SDRAM Timing Register (SDTIM) 2.5.5 C6211/C6711/C64x SDRAM Extension Register (SDEXT) 2.6 Interchangeable SDRAM Devices and Upgrading (C64x only) TMS320C6000 is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 1

SPRA433B SDRAM 3.1 SDRAM Commands 3 4 5 6 3.2 SDRAM Initialization 3.3 Monitoring Page Boundaries 3.3.1 C620x/C670x Page Boundaries 3.3.2 C6211/C6711 Page Boundaries 3.3.3 C64x Page Boundaries 3.4 Address Shift 3.5 Timing Constraints 3.5.1 C6000 Outputs (ED, EA, CE, BE, SDCAS, SDRAS, SDWE) 3.5.2 C6000 Inputs (Output Data From the SDRAM, Read ED) 3.5.3 Timing Comparisons for Four SDRAMs 3.1.1 Timing Requirements 3.1.2 Deactivation (DCAB and DEAC) 3.1.3 Activate (ACTV) 3.1.4 SDRAM Read (READ) 3.1.5 SDRAM Write (WRT) 3.1.6 Mode Register Set (MRS) 3.1.7 Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 EMIF Global Control Register for C6414 to MT48LC4M32B2 6.1.2 EMIF CE2 Space Control Register for C6414 to MT48LC4M32B2 6.1.3 EMIF SDRAM Control Register for C6414 to MT48LC4M32B2 6.1.4 EMIF SDRAM Refresh Period for C6414 to MT48LC4M32B2 6.1.5 EMIF SDRAM Extension Register for C6414 to MT48LC4M32B2 5.1.1 EMIF Global Control Registers for C6211 to MT48LC16M8A2 5.1.2 EMIF CE3 Space Control Register for C6211 to MT48LC16M8A2 5.1.3 EMIF SDRAM Control Register for C6211 to MT48LC16M8A2 5.1.4 EMIF SDRAM Refresh Period for C6211 to MT48LC16M8A2 5.1.5 EMIF SDRAM Extension Register for C6211 to MT48LC16M8A2 Complete Example Using C6201B and Micron’s MT48LC4M16A2-10 4.1 Register Configuration for C6201B to MT48LC4M16A2 4.1.1 EMIF Global Control Registers for C6201B to MT48LC4M16A2 4.1.2 EMIF CE2 Space Control Register for C6201B to MT48LC4M16A2 4.1.3 EMIF SDRAM Control Register for C6201B to MT48LC4M16A2 4.1.4 EMIF SDRAM Refresh Period for C6201B to MT48LC4M16A2 References 7 Appendix A Code Example for C6201B to Micron MT48LC4M16A2-10 Appendix B Code Example for C6211 to Micron MT48LC16M8A2-8 Complete Example Using C6211 and Micron’s MT48LC16M8A2-8 5.1 Register Configuration for C6211 to MT48LC16M8A2 Complete Examples Using C6414 and Micron’s MT48LC4M32B2-7 6.1 Register Configuration for C6414 to MT48LC4M32B2 32 32 33 35 36 36 40 42 44 46 46 46 47 48 48 51 52 53 53 55 56 56 56 57 58 58 58 59 59 60 60 61 61 61 62 62 63 63 64 65 66 68 2 TMS320C6000 EMIF-to-External SDRAM Interface

List of Figures SPRA433B Figure 1. C6000 EMIF-to-16M-Bit SDRAM Interface Using Two 16-Bit-Wide Chips Figure 2. C6000 EMIF-to-16M-Bit SDRAM Interface Using Four 8-Bit-Wide Chips Figure 3. C6000 EMIF1-to-64M-Bit SDRAM Interface Using Two 16-Bit-Wide Chips Figure 4. C6000 EMIF-to-64M-Bit SDRAM Interface Using One 32-Bit-Wide Chip Figure 5. C6211/C6711 EMIF-to-64M-Bit SDRAM Interface Using One 16-Bit-Wide Chip (Big Endian) Figure 6. C64x EMIFA-to64M-Bit SDRAM Interface Using Two 32-Bit-Wide Chips Figure 7. C64x EMIFA-to-512M-Bit SDRAM Interface Using One 64-bit-Wide Chip Figure 8. C6201/C6701 EMIF Block Diagram Figure 9. C6202/C6203/C6204/C6205 EMIF Block Diagram Figure 10. C6211/C6711 EMIF Block Diagram Figure 11. C64x EMIF Block Diagram Figure 12. C6211/C6711 Byte-Lane Alignment vs. Endianness Figure 13. EMIFA (64-bit bus) Byte Alignment by Endianness Figure 14. EMIFB (16-bit Bus) Byte Alignment by Endianness Figure 15. C6201/C6202/C6203/C6204/C6205 vs. C6201B/C6701 Output Timing Figure 16. C6211/C6711/C64x Output Timing Figure 17. C62x/C7x EMIF Global Control Register Diagram Figure 18. C64x EMIF Global Control Register Diagram Figure 19. C620x/C670x EMIF CE Space Control Register Diagram Figure 20. C6211/C6711/C64x EMIF CE Space Control Register Diagram Figure 21. EMIF SDRAM Control Register Figure 22. EMIF SDRAM Timing Register Figure 23. C6211/C6711/C64x SDRAM Extension Register Figure 24. SDRAM Logical Address Bits Figure 25. Modified Type 2 Logical Address Bits Figure 26. EMIFA to SDRAM Pin Interface for x16-Bit SDRAM Figure 27. EMIFB to SDRAM Pin Interface for x32 Bit SDRAM Figure 28. SDRAM DCAB—Closes All Banks in a CE Space Figure 29. C6211/C6711/C64x SDRAM DEAC—Closes Single Bank Specified by BS Figure 30. C620x/C670x SDRAM Read—CAS Latency 3 Figure 31. C6211/C6711 SDRAM Read—CAS Latency 3 Figure 32. C6211/C6711 SDRAM Read With DEAC Figure 33. C64x SDRAM Read—CAS Latency 3 Figure 34. C620x/C670x SDRAM Burst Length 1 Write Figure 35. C6211/C6711 SDRAM Burst Length 4 Write Figure 36. C64x SDRAM Burst Length 4 Write Figure 37. SDRAM Mode Register Set: MRS Command Figure 38. SDRAM Refresh Figure 39. Logical Address Breakdown for 1 Bank Bit, 11 Row Bits, 8 Column Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 12 13 13 14 14 17 17 18 19 21 22 22 23 23 24 25 26 26 27 28 29 31 31 31 32 35 36 37 38 39 40 41 41 42 43 44 47 TMS320C6000 EMIF-to-External SDRAM Interface 3

SPRA433B Input to C6000 (Read Data) Figure 40. Logical Address Breakdown for 2 Banks, 11 Row Bits, 9 Column Bits Figure 41. Outputs From C620x/C670x (Write Data [ED], Control, and Address Signals) Figure 42. Outputs From C6211/C6711/C64x (Write Data [ED], Control, and Address Signals) Figure 43. Figure 44. EMIF Global Control Register Diagram for C6201B to MT48LC4M16A2 Figure 45. EMIF CE2 Space Control Register Diagram for C6201B to MT48LC4M16A2 Figure 46. EMIF SDRAM Control Register for C6201B to MT48LC4M16A2 Figure 47. EMIF SDRAM Refresh Period for C6201B to MT48LC4M16A2 Figure 48. EMIF Global Control Register Diagram for C6211 to MT48LC16M8A2 Figure 49. EMIF CE3 Space Control Register Diagram for C6211 to MT48LC16M8A2 Figure 50. EMIF SDRAM Control Register for C6211 to MT48LC16M8A2 Figure 51. EMIF SDRAM Refresh Period for C6211 to MT48LC16M8A2 Figure 52. EMIF Global Control Register Diagram for C6414 MT48LC4M32B2 Figure 53. EMIF CE2 Space Control Register Diagram Figure 54. EMIF SDRAM Control Register for C6414 to MT48LC4M32B2 Figure 55. EMIF SDRAM Refresh Period for C6414 to MT48LC4M32B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 52 53 53 56 57 57 58 59 59 60 60 62 63 63 64 List of Tables Table 1. C620x/C670x Compatible Memory Type Characteristics Table 2. C621x/C671x Compatible Memory Type Characteristics Table 3. C64x Compatible Memory Type Characteristics Table 4. C6000 EMIF Signal Descriptions: Shared Signals and SDRAM Signals Table 5. C6000 EMIF Memory Mapped Registers Table 6. EMIF Global Control Register Bit Field Description Table 7. C6000 EMIF CE Space Control Register Bit Field Description for SDRAM Table 8. EMIF SDRAM Control Register Bit Field Description Table 9. EMIF SDRAM Refresh Period Bit Field Description Table 10. C6211/C6711/C64x EMIF SDRAM Extension Register Bit Field Description Table 11. Upgradeable and Compatible SDRAM Devices Table 12. EMIF SDRAM Commands Table 13. Truth Table for SDRAM Commands Table 14. C620x/C670x SDRAM Timing Parameters Table 15. C6211/C6711/C64x SDRAM Timing Parameters Table 16. C6211/C6711/C64x Recommended Values for CMD to CMD Parameters Table 17. Mode Register Value† Table 18. Table 19. C620x/C670x Byte Address to EA Mapping for SDRAM RAS and CAS Table 20. C6211/C6711 Byte Address to EA Mapping for SDRAM RAS and CAS Table 21. C64x Byte Address to EA Mapping for SDRAM RAS and CAS Table 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MT48LC4M16A2-10 andC6201B-200 Timing Parameters 6 7 8 20 24 25 26 27 28 29 32 32 33 33 34 34 43 44 49 49 50 54 Implied SDRAM Configuration by MRS Value 4 TMS320C6000 EMIF-to-External SDRAM Interface

SPRA433B MT48LC4M16A2-8 and C6202/C6203/C6204/C6205-250 Timing Parameters MT48LC16M8A2-8 and C6211-150 Timing Parameters MT48LC16M8A2-8 and C6211-150 Timing Parameters Table 23. Table 24. Table 25. Table 26. SDRAM Registers Table 27. Timing Parameter Calculation for SDRAM Control Register for C6201B to MT48LC4M16A2 Table 28. Period Calculation for SDRAM Refresh Period for C6201B to MT48LC4M16A2 Table 29. SDRAM Registers for C6211 to MT48LC16M8A2 Table 30. Timing Parameter Calculation for SDRAM Control Register for C6211 to MT48LC16M8A2 Table 31. Period Calculation for SDRAM Refresh Period for C6211 to MT48LC16M8A2 Table 32. SDRAM Extension Register Values for C6211 to MT48LC16M8A2 Table 33. SDRAM Registers for C6414 Table 34. Global Control Register for C6414 Table 35. Timing Parameter Calculation for SDRAM Control Register for C6414 to MT48LC4M32B2 Table 36. Period Calculation for SDRAM Refresh Period for C6211 to MT48LC16M8A2 Table 37. SDRAM Extension Register Values for C6414 to MT48LC4M32B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 55 55 56 57 58 59 60 60 61 62 62 63 64 64 1 Interface of C6000 EMIF With SDRAM The EMIF of all C6000 devices offer a glueless interface to industry-standard SDRAM in the most commonly available configurations, including 16M bits x 8, 16M bits x 16, 64M bits x 16, and 64M bits x 32 devices.† Depending on the specific C6000 device, additional configurations may be supported. 1.1 C620x/C670x Compatible Memory Types The C620x/C670x EMIF supports a glueless interface to a 16M-bit, 2-bank and a 64M-bit, 4-bank SDRAM, offering system designers an interface to high-speed and high-density memory. lists the possible SDRAM configurations that are fully supported by the EMIF. As Table 1 shows, the SDRAM supported by the C620x/C670x EMIF has either eight or nine column address bits and maps into a memory space equal to or smaller than 16M bytes. Because the C620x/C670x EMIF has a 32-bit word size, four 8-bit or two 16-bit devices must be used in parallel to create a 32-bit word. C6000 is a trademark of Texas Instruments. † For a complete list of Texas Instruments DSP devices, go to the TI web site at http://www.ti.com TMS320C6000 EMIF-to-External SDRAM Interface 5

Table 1. C620x/C670x Compatible Memory Type Characteristics SPRA433B SDRAM Size 16M bits 64M bits Banks Width Depth 2 2 4 4 x8 1M x16 512K x16 1M x32 512K 128M bits 4 X32 1M Devices/ CE 4 Addressable Space (M Bytes) Column Address Row Address 8M SDRAM A8–A0 A10–A0 EMIF EA10–EA2 SDA10, EA11–EA2 4M SDRAM A7–A0 A10–A0 EMIF EA9–EA2 SDA10, EA11–EA2 Bank Select A11 EA13 A11 EA13 Pre-charge A10 SDA10 A10 SDA10 16M SDRAM A7–A0 A11–A0 A13–A12 A10 EMIF EA9–EA2 SDA10, EA13–EA2 EA15–EA14 SDA10 8M SDRAM A7–A0 A10–A0 A12–A11 A10 EMIF EA9–EA2 SDA10, EA11–EA2 EA14–EA13 SDA10 16M SDRAM A7–A0 A11–A0 A13–A12 A10 EMIF EA9–EA2 EA13, SDA10, EA11–EA2 EA15–EA14 SDA10 2 2 1 1 Table 1 summarizes the page characteristics of the fully supported SDRAM memory types and illustrates the EMIF-to-SDRAM pin mapping. The SDRAM uses addresses A[x:0]. These pins are mapped to EA[x+2:2] on the EMIF because the EMIF assumes that SDRAM memory spaces are 32 bits wide. The four BE signals serve as the two LSBs (least significant bits) of the external address. A key element of the supported SDRAM memory types is that A10 is always the precharge pin. To support this functionality, the EMIF’s SDRAM interface uses a pin named SDA10, instead of EA12 in the pin map, to support the necessary SDRAM operations. During row activate, SDA10 is logically equivalent to EA12. For other SDRAM operations, SDA10 is used as the precharge pin. 1.2 C621x/C671x Compatible Memory Types The C621x/C671x EMIF supports a glueless interface to almost any configuration of SDRAM memory types, including those supported by the C620x/C670x EMIF. This is possible because of 1) larger CE spaces and 2) programmable SDRAM page characteristics. Table 2 lists the common configurations of SDRAM that are fully supported by the C621x/C671x EMIF. 6 TMS320C6000 EMIF-to-External SDRAM Interface

Table 2. C621x/C671x Compatible Memory Type Characteristics Banks Width Depth CE Max Devices/ Addressable Space (M Bytes) Column Address Row Address Bank Select Pre-charge SPRA433B 2 2 2 4 4 4 4 4 4 4 4 4 4 x4 2M x8 1M x16 512K x4 4M x8 2M x16 1M x32† 512K X8 4M X16 2M X32 1M x8 8M x16 4M X16 8M 8 4 2 8 4 2 1 4 2 1 4 2 2 16M SDRAM A9–A0 A10–A0 EMIF EA11–EA2 EA12–EA2 8M SDRAM A8–A0 A10–A0 EMIF EA10–EA2 EA12–EA2 4M SDRAM A7–A0 A10–A0 EMIF EA9–EA2 EA12–EA2 A11 EA13 A11 EA13 A11 EA13 64M SDRAM A9–A0 A11–A0 A13–A12 A10 EA12 A10 EA12 A10 EA12 A10 EMIF EA11–EA2 EA13–EA2 EA15–EA14 EA12 32M SDRAM A8–A0 A11–A0 A13–A12 A10 EMIF EA10–EA2 EA13–EA2 EA15–EA14 EA12 16M SDRAM A7–A0 A11–A0 A13–A12 A10 EMIF EA9–EA2 EA13–EA2 EA15–EA14 EA12 8M SDRAM A7–A0 A10–A0 A12–A11 A10 EMIF EA9–EA2 EA12–EA2 EA14–EA13 EA12 64M SDRAM A9–A0 A11–A0 A13–A12 A10 EMIF EA11–EA2 EA13–EA2 EA15–EA14 EA12 32M SDRAM A8–A0 A11–A0 A13–A12 A10 EMIF EA10–EA2 EA13–EA2 EA15–EA14 EA12 16M SDRAM A7–A0 A11–A0 A13–A12 A10 EMIF EA9–EA2 EA13–EA2 EA15–EA14 EA12 128M SDRAM A9–A0 A12–A0 A14–A13 A10 EMIF EA11–EA2 EA14–EA2 EA16–EA15 EA12 64M SDRAM A8–A0 A12–A0 A14–A13 A10 EMIF EA10–EA2 EA14–EA2 EA16–EA15 EA12 128M SDRAM A9–A0 A12–A0 A14–A13 A10 EMIF EA11–EA2 EA14–EA2 EA16–EA15 EA12 SDRAM Size 16M bits 64M bits 128M bits 256M bits 512M bits † The x32 width does not apply to C6712 TMS320C6000 EMIF-to-External SDRAM Interface 7

SPRA433B Table 2 summarizes the page characteristics of the fully supported SDRAM memory types and illustrates the EMIF-to-SDRAM pin mapping. The SDRAM uses addresses A[x:0]. These pins are mapped to EA[x+2:2] on the EMIF because the C621x/C671x EMIF assumes that SDRAM memory spaces are 32 bits wide. The four BE signals serve as the two LSBs of the external address. A key element of the supported SDRAM memory types is that A10 is always the precharge pin. Because hidden refresh is not supported on the C621x/C671x EMIF, EA12 maps directly to A10 on the SDRAM. The C621x/C671x EMIF does not use the SDA10 signal, as it does on the C620x/C670x EMIF. Note that the C621x/C671x EMIF also supports SDRAM memory space widths of 8- or 16-bits wide. 1.3 C64x Compatible Memory Types The TMS320C64x EMIFA and EMIFB support a glueless interface to almost any configuration of SDRAM memory types, including those supported by the C620x/C670x and C6211/C6711 EMIF. Like the C6211/C6711, this is possible because of 1) larger CE spaces and 2) programmable SDRAM page characteristics. Table 3 lists the common configurations of SDRAM that are fully supported by the C64x EMIF. Table 3. C64x Compatible Memory Type Characteristics SDRAM Size Banks Width Depth 16M bits 2 x4 2M Max Devices/ CE 16 2 2 x8 1M x16 512K 64M bits 4 x4 4M 4 4 x8 2M x16 1M 8 4 8 4 2 Addressable Space (M Bytes) Column Address Row Address Bank Select Pre-charge 32M SDRAM A9–A0 A10–A0 EMIFA EA12–EA3 EA13–EA3 EMIFB EA10–EA1 EA11–EA1 16M SDRAM A8–A0 A10–A0 EMIFA EA11–EA3 EA13–EA3 EMIFB EA9–EA1 EA11–EA1 8M SDRAM A7–A0 A10–A0 EMIFA EA10–EA3 EA13–EA3 EMIFB – – A11 EA14 EA12 A11 EA14 EA12 A11 EA12 – 128M SDRAM A9–A0 A11–A0 A13–A12 EMIFA EA12–EA3 EA14–EA3 EA16–EA15 EMIBA EA10–EA1 EA12–EA1 EA14–EA13 64M SDRAM A8–A0 A11–A0 A13–A12 EMIFA EA11–EA3 EA14–EA3 EA16–EA15 EMIFB EA9–EA1 EA12–EA1 EA14–EA13 32M SDRAM A7–A0 A11–A0 A13–A12 A10 EA13 EA11 A10 EA13 EA11 A10 EA11 – A10 EA13 EA11 A10 EA13 EA11 A10 EMIFA EA10–EA3 EA14–EA3 EA16–EA15 EA13 TMS320C64x is a trademark of Texas Instruments. 8 TMS320C6000 EMIF-to-External SDRAM Interface

分享到：

赞收藏

资料库

DSP的EMIF接口使用手册.pdf

相关推荐

开发技术

热门标签

最新资料