The RISC-V Instruction Set Manual Volume II: Privileged Architec....pdf

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Preface

Introduction

RISC-V Hardware Platform Terminology

RISC-V Privileged Software Stack Terminology

Privilege Levels

Debug Mode

Control and Status Registers (CSRs)

CSR Address Mapping Conventions

CSR Listing

CSR Field Specifications

Machine-Level ISA, version 1.10

Machine-Level CSRs

Machine ISA Register misa

Machine Vendor ID Register mvendorid

Machine Architecture ID Register marchid

Machine Implementation ID Register mimpid

Hart ID Register mhartid

Machine Status Register (mstatus)

Privilege and Global Interrupt-Enable Stack in mstatus register

Base ISA Control in mstatus Register

Memory Privilege in mstatus Register

Virtualization Support in mstatus Register

Extension Context Status in mstatus Register

Machine Trap-Vector Base-Address Register (mtvec)

Machine Trap Delegation Registers (medeleg and mideleg)

Machine Interrupt Registers (mip and mie)

Machine Timer Registers (mtime and mtimecmp)

Hardware Performance Monitor

Counter-Enable Registers ([m|h|s]counteren)

Machine Scratch Register (mscratch)

Machine Exception Program Counter (mepc)

Machine Cause Register (mcause)

Machine Trap Value (mtval) Register

Machine-Mode Privileged Instructions

Environment Call and Breakpoint

Trap-Return Instructions

Wait for Interrupt

Reset

Non-Maskable Interrupts

Physical Memory Attributes

Main Memory versus I/O versus Empty Regions

Supported Access Type PMAs

Atomicity PMAs

Memory-Ordering PMAs

Coherence and Cacheability PMAs

Idempotency PMAs

Physical Memory Protection

Physical Memory Protection CSRs

Supervisor-Level ISA, Version 1.10

Supervisor CSRs

Supervisor Status Register (sstatus)

Base ISA Control in sstatus Register

Memory Privilege in sstatus Register

Supervisor Trap Vector Base Address Register (stvec)

Supervisor Interrupt Registers (sip and sie)

Supervisor Timers and Performance Counters

Counter-Enable Register (scounteren)

Supervisor Scratch Register (sscratch)

Supervisor Exception Program Counter (sepc)

Supervisor Cause Register (scause)

Supervisor Trap Value (stval) Register

Supervisor Address Translation and Protection (satp) Register

Supervisor Instructions

Supervisor Memory-Management Fence Instruction

Sv32: Page-Based 32-bit Virtual-Memory Systems

Addressing and Memory Protection

Virtual Address Translation Process

Sv39: Page-Based 39-bit Virtual-Memory System

Addressing and Memory Protection

Sv48: Page-Based 48-bit Virtual-Memory System

Addressing and Memory Protection

Hypervisor Extensions, Version 0.0

RISC-V Privileged Instruction Set Listings

Platform-Level Interrupt Controller (PLIC)

PLIC Overview

Interrupt Sources

Local Interrupt Sources

Global Interrupt Sources

Interrupt Targets and Hart Contexts

Interrupt Gateways

Interrupt Identifiers (IDs)

Interrupt Priorities

Interrupt Enables

Interrupt Priority Thresholds

Interrupt Notifications

Interrupt Claims

Interrupt Completion

Interrupt Flow

PLIC Core Specification

Controlling Access to the PLIC

Machine Configuration Description

Configuration String Search Procedure

History

Research Funding at UC Berkeley

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Privileged Architecture Version 1.10 Document Version 1.10 Warning! This draft speciﬁcation may change before being accepted as standard by the RISC-V Foundation. While the editors intend future changes to this speciﬁcation to be forward compatible, it remains possible that implementations made to this draft speciﬁcation will not conform to the future standard. Editors: Andrew Waterman1, Krste Asanovi´c1,2 1SiFive Inc., 2CS Division, EECS Department, University of California, Berkeley andrew@sifive.com, krste@berkeley.edu May 7, 2017

Contributors to all versions of the spec in alphabetical order (please contact editors to suggest corrections): Krste Asanovi´c, Rimas Aviˇzienis, Jacob Bachmeyer, Allen J. Baum, Paolo Bonzini, Ruslan Bukin, Christopher Celio, David Chisnall, Anthony Coulter, Palmer Dabbelt, Monte Dal- rymple, Dennis Ferguson, Mike Frysinger, John Hauser, David Horner, Olof Johansson, Yunsup Lee, Andrew Lutomirski, Jonathan Neusch¨afer, Rishiyur Nikhil, Stefan O’Rear, Albert Ou, John Ousterhout, David Patterson, Colin Schmidt, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray VanDeWalker, Megan Wachs, Andrew Waterman, and Reinoud Zandijk. This document is released under a Creative Commons Attribution 4.0 International License. This document is a derivative of the RISC-V privileged speciﬁcation version 1.9.1 released under following license: c 2010–2017 Andrew Waterman, Yunsup Lee, Rimas Aviˇzienis, David Patterson, Krste Asanovi´c. Creative Commons Attribution 4.0 International License. Please cite as: “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10”, Editors Andrew Waterman and Krste Asanovi´c, RISC-V Foundation, May 2017.

Preface This is version 1.10 of the RISC-V privileged architecture proposal. Changes from version 1.9.1 include: • The previous version of this document was released under a Creative Commons Attribution 4.0 International Licence by the original authors, and this and future versions of this document will be released under the same licence. • The explicit convention on shadow CSR addresses has been removed to reclaim CSR space. • The mvendorid register now contains the JEDEC code of the core provider as opposed to a code supplied by the Foundation. This avoids redundancy and oﬄoads work from the Foundation. Shadow CSRs can still be added as needed. of external interrupts. capture bad instruction bits on an illegal instruction fault to speed instruction emulation. • The interrupt-enable stack discipline has been simpliﬁed. • An optional mechanism to change the base ISA used by supervisor and user modes has been added to the mstatus CSR, and the ﬁeld previously called Base in misa has been renamed to MXL for consistency. • Clariﬁed expected use of XS to summarize additional extension state status ﬁelds in mstatus. • Optional vectored interrupt support has been added to the mtvec and stvec CSRs. • The SEIP and UEIP bits in the mip CSR have been redeﬁned to support software injection • The mbadaddr register has been subsumed by a more general mtval register that can now • The machine-mode base-and-bounds translation and protection schemes have been removed from the speciﬁcation as part of moving the virtual memory conﬁguration to sptbr (now satp). Some of the motivation for the base and bound schemes are now covered by the PMP registers, but space remains available in mstatus to add these back at a later date if deemed useful. • In systems with only M-mode, or with both M-mode and U-mode but without U-mode trap support, the medeleg and mideleg registers now do not exist, whereas previously they returned zero. • Virtual-memory page faults now have mcause values distinct from physical-memory access exceptions. Page-fault exceptions can now be delegated to S-mode without delegating excep- tions generated by PMA and PMP checks. • An optional physical-memory protection (PMP) scheme has been proposed. • The supervisor virtual memory conﬁguration has been moved from the mstatus register to the sptbr register. Accordingly, the sptbr register has been renamed to satp (Supervisor i

ii Volume II: RISC-V Privileged Architectures V1.10 Address Translation and Protection) to reﬂect is broadened role. management operations has been added. as a separate speciﬁcation. instruction. to U-mode. MXR. The bit has been renamed to SUM. simpler implementations may trap to software to set them. • The SFENCE.VM instruction has been removed in favor of the improved SFENCE.VMA • The mstatus bit MXR has been exposed to S-mode via sstatus. • The polarity of the PUM bit in sstatus has been inverted to shorten code sequences involving • Hardware management of page-table entry Accessed and Dirty bits has been made optional; • The counter-enable scheme has changed, so that S-mode can control availability of counters • H-mode has been removed, as we are focusing on recursive virtualization support in S-mode. • A mechanism to improve virtualization performance by trapping S-mode virtual-memory • The Supervisor Binary Interface (SBI) chapter has been removed, so that it can be maintained The encoding space has been reserved and may be repurposed at a later date.

Volume II: RISC-V Privileged Architectures V1.10 iii Preface to Version 1.9.1 This is version 1.9.1 of the RISC-V privileged architecture proposal. Changes from version 1.9 include: including Device Tree String and ﬂattened Device Tree. • Numerous additions and improvements to the commentary sections. • Change conﬁguration string proposal to be use a search process that supports various formats • Made misa optionally writable to support modifying base and supported ISA extensions. • Added description of debug mode and debug CSRs. • Added a hardware performance monitoring scheme. Simpliﬁed the handling of existing hard- ware counters, removing privileged versions of the counters and the corresponding delta reg- isters. CSR address of misa changed. • Fixed description of SPIE in presence of user-level interrupts.

iv Volume II: RISC-V Privileged Architectures V1.10

Contents Preface 1 Introduction 1.1 RISC-V Hardware Platform Terminology . . . . . . . . . . . . . . . . . . . . . . . . 1.2 RISC-V Privileged Software Stack Terminology . . . . . . . . . . . . . . . . . . . . . 1.3 Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Control and Status Registers (CSRs) 2.1 CSR Address Mapping Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 CSR Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i 1 1 2 3 5 7 7 9 2.3 CSR Field Speciﬁcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Machine-Level ISA, version 1.10 15 3.1 Machine-Level CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.1 Machine ISA Register misa . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.2 Machine Vendor ID Register mvendorid . . . . . . . . . . . . . . . . . . . . . 18 3.1.3 Machine Architecture ID Register marchid . . . . . . . . . . . . . . . . . . . 18 3.1.4 Machine Implementation ID Register mimpid . . . . . . . . . . . . . . . . . . 19 3.1.5 Hart ID Register mhartid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.6 Machine Status Register (mstatus) . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.7 Privilege and Global Interrupt-Enable Stack in mstatus register . . . . . . . 20 v

vi Volume II: RISC-V Privileged Architectures V1.10 3.1.8 Base ISA Control in mstatus Register . . . . . . . . . . . . . . . . . . . . . . 21 3.1.9 Memory Privilege in mstatus Register . . . . . . . . . . . . . . . . . . . . . . 22 3.1.10 Virtualization Support in mstatus Register . . . . . . . . . . . . . . . . . . . 22 3.1.11 Extension Context Status in mstatus Register . . . . . . . . . . . . . . . . . 23 3.1.12 Machine Trap-Vector Base-Address Register (mtvec) . . . . . . . . . . . . . . 26 3.1.13 Machine Trap Delegation Registers (medeleg and mideleg) . . . . . . . . . . 27 3.1.14 Machine Interrupt Registers (mip and mie) . . . . . . . . . . . . . . . . . . . 28 3.1.15 Machine Timer Registers (mtime and mtimecmp) . . . . . . . . . . . . . . . . 30 3.1.16 Hardware Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.17 Counter-Enable Registers ([m|h|s]counteren) . . . . . . . . . . . . . . . . . 32 3.1.18 Machine Scratch Register (mscratch) . . . . . . . . . . . . . . . . . . . . . . 33 3.1.19 Machine Exception Program Counter (mepc) . . . . . . . . . . . . . . . . . . 34 3.1.20 Machine Cause Register (mcause) . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.21 Machine Trap Value (mtval) Register . . . . . . . . . . . . . . . . . . . . . . 35 3.2 Machine-Mode Privileged Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.1 Environment Call and Breakpoint . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.2 Trap-Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.3 Wait for Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5 Physical Memory Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5.1 Main Memory versus I/O versus Empty Regions . . . . . . . . . . . . . . . . 41 3.5.2 Supported Access Type PMAs . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.3 Atomicity PMAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.4 Memory-Ordering PMAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.5 Coherence and Cacheability PMAs . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5.6 Idempotency PMAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 Physical Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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