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dw_apb_i2c_db.pdf
SolvNet
DesignWare
Documentation Overview
Release Notes
Installation Guide
Contents
Preface
Organization
Related Documentation
Document Revision History
Web Resources
Customer Support
1 Product Overview
1.1 DesignWare System Overview
1.2 General product Description
1.2.1 DW_apb_i2c Block Diagram
1.3 Features
1.3.1 I2C Features
1.3.2 DesignWare APB Slave Interface
1.4 Standards Compliance
1.5 Verification Environment Overview
1.6 Licenses
2 Building and Verifying a Component or Subsystem
2.1 Setting up Your Environment
2.2 Overview of the coreConsultant Configuration and Integration Process
2.2.1 coreConsultant Usage
2.2.2 Configuring the DW_apb_i2c within coreConsultant
2.2.3 Creating Gate-Level Netlists within coreConsultant
2.2.4 Verifying the DW_apb_i2c within coreConsultant
2.2.5 Running Leda on Generated Code with coreConsultant
2.3 Overview of the coreAssembler Configuration and Integration Process
2.3.1 coreAssembler Usage
2.3.2 Configuring the DW_apb_i2c within a Subsystem
2.3.3 Creating Gate-Level Netlists within coreAssembler
2.3.4 Verifying the DW_apb_i2c within coreAssembler
2.3.5 Running Leda on Generated Code with coreAssembler
2.4 Database Files
2.4.1 Design/HDL Files
2.4.2 Synthesis Files
2.4.3 Verification Reference Files
3 Functional Description
3.1 Overview
3.2 I2C Terminology
3.2.1 I2C Bus Terms
3.2.2 Bus Transfer Terms
3.3 I2C Behavior
3.3.1 START and STOP Generation
3.3.2 Combined Formats
3.4 I2C Protocols
3.4.1 START and STOP Conditions
3.4.2 Addressing Slave Protocol
3.4.3 Transmitting and Receiving Protocol
3.4.4 START BYTE Transfer Protocol
3.5 Tx FIFO Management and START, STOP and RESTART Generation
3.5.1 Tx FIFO Management When IC_EMPTYFIFO_HOLD_MASTER_EN = 0
3.5.2 Tx FIFO Management When IC_EMPTYFIFO_HOLD_MASTER_EN = 1
3.6 Multiple Master Arbitration
3.7 Clock Synchronization
3.8 Operation Modes
3.8.1 Slave Mode Operation
3.8.2 Master Mode Operation
3.8.3 Disabling DW_apb_i2c
3.9 Spike Suppression
3.10 IC_CLK Frequency Configuration
3.10.1 Minimum High and Low Counts
3.10.2 Minimum IC_CLK Frequency
3.11 SDA Hold Time
3.12 DMA Controller Interface
3.12.1 Enabling the DMA Controller Interface
3.12.2 Overview of Operation
3.12.3 Transmit Watermark Level and Transmit FIFO Underflow
3.12.4 Choosing the Transmit Watermark Level
3.12.5 Selecting DEST_MSIZE and Transmit FIFO Overflow
3.12.6 Receive Watermark Level and Receive FIFO Overflow
3.12.7 Choosing the Receive Watermark level
3.12.8 Selecting SRC_MSIZE and Receive FIFO Underflow
3.12.9 Handshaking Interface Operation
3.13 APB Interface
4 Parameters
4.1 Parameter Descriptions
4.2 Configuration Parameters
5 Signals
5.1 DW_apb_i2c Interface Diagram
5.2 I/O Connections
5.3 DW_apb_i2c Signal Descriptions
6 Registers
6.1 Register Memory Map
6.2 Operation of Interrupt Registers
6.3 Registers and Field Descriptions
6.3.1 IC_CON
6.3.2 IC_TAR
6.3.3 IC_SAR
6.3.4 IC_HS_MADDR
6.3.5 IC_DATA_CMD
6.3.6 IC_SS_SCL_HCNT
6.3.7 IC_SS_SCL_LCNT
6.3.8 IC_FS_SCL_HCNT
6.3.9 IC_FS_SCL_LCNT
6.3.10 IC_HS_SCL_HCNT
6.3.11 IC_HS_SCL_LCNT
6.3.12 IC_INTR_STAT
6.3.13 IC_INTR_MASK
6.3.14 IC_RAW_INTR_STAT
6.3.15 IC_RX_TL
6.3.16 IC_TX_TL
6.3.17 IC_CLR_INTR
6.3.18 IC_CLR_RX_UNDER
6.3.19 IC_CLR_RX_OVER
6.3.20 IC_CLR_TX_OVER
6.3.21 IC_CLR_RD_REQ
6.3.22 IC_CLR_TX_ABRT
6.3.23 IC_CLR_RX_DONE
6.3.24 IC_CLR_ACTIVITY
6.3.25 IC_CLR_STOP_DET
6.3.26 IC_CLR_START_DET
6.3.27 IC_CLR_GEN_CALL
6.3.28 IC_ENABLE
6.3.29 IC_STATUS
6.3.30 IC_TXFLR
6.3.31 IC_RXFLR
6.3.32 IC_SDA_HOLD
6.3.33 IC_TX_ABRT_SOURCE
6.3.34 IC_SLV_DATA_NACK_ONLY
6.3.35 IC_DMA_CR
6.3.36 IC_DMA_TDLR
6.3.37 IC_DMA_RDLR
6.3.38 IC_SDA_SETUP
6.3.39 IC_ACK_GENERAL_CALL
6.3.40 IC_ENABLE_STATUS
6.3.41 IC_FS_SPKLEN
6.3.42 IC_HS_SPKLEN
6.3.43 IC_COMP_PARAM_1
6.3.44 IC_COMP_VERSION
6.3.45 IC_COMP_TYPE
7 Programming the DW_apb_i2c
7.1 Software Registers
7.2 Software Drivers
8 Verification
8.1 Overview of Vera Tests
8.1.1 APB Slave Interface
8.1.2 DW_apb_i2c Master Operation
8.1.3 DW_apb_i2c Slave Operation
8.1.4 DW_apb_i2c Interrupts
8.1.5 DMA Handshaking Interface
8.1.6 DW_apb_i2c Dynamic IC_TAR and IC_10BITADDR_MASTER Update
8.1.7 Generate NACK as a Slave-Receiver
8.1.8 SCL Held Low for Duration Specified in IC_SDA_SETUP
8.1.9 Generate ACK/NACK for General Call
8.2 Overview of DW_apb_i2c Testbench
9 Integration Considerations
9.1 Digital/Analog Domain Functional Partitioning
9.2 Reading and Writing from an APB Slave
9.2.1 Reading From Unused Locations
9.2.2 32-bit Bus System
9.2.3 16-bit Bus System
9.2.4 8-bit Bus System
9.3 Write Timing Operation
9.4 Read Timing Operation
9.5 Accessing Top-level Constraints
10 Glossary
Index
A
B
C
D
E
F
G
H
I
L
M
N
O
P
R
S
T
V
W
Z
DesignWare DW_apb_i2c Databook
DW_apb_i2c
Version 1.15a
April 2011
DesignWare DW_apb_i2c Databook
Copyright Notice and Proprietary Information
Copyright © 2011 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information
that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or
copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced,
transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written
permission of Synopsys, Inc., or as expressly provided by the license agreement.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and
to comply with them.
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MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
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All other product or company names may be trademarks of their respective owners.
Synopsys, Inc.
700 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com
2
Synopsys, Inc.
April 2011
DesignWare DW_apb_i2c Databook
Contents
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.1 DesignWare System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.2 General product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2.1 DW_apb_i2c Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3.1 I2C Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3.2 DesignWare APB Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4 Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5 Verification Environment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.6 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Chapter 2
Building and Verifying a Component or Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.1 Setting up Your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.2 Overview of the coreConsultant Configuration and Integration Process . . . . . . . . . . . . . . . . . . . . . . .20
2.2.1 coreConsultant Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2.2 Configuring the DW_apb_i2c within coreConsultant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.3 Creating Gate-Level Netlists within coreConsultant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.4 Verifying the DW_apb_i2c within coreConsultant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.2.5 Running Leda on Generated Code with coreConsultant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.3 Overview of the coreAssembler Configuration and Integration Process . . . . . . . . . . . . . . . . . . . . . . .23
2.3.1 coreAssembler Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.3.2 Configuring the DW_apb_i2c within a Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3.3 Creating Gate-Level Netlists within coreAssembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3.4 Verifying the DW_apb_i2c within coreAssembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.5 Running Leda on Generated Code with coreAssembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.4 Database Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.4.1 Design/HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.4.2 Synthesis Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.4.3 Verification Reference Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Chapter 3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.2 I2C Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.2.1 I2C Bus Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.2.2 Bus Transfer Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
April 2011
Synopsys, Inc.
SolvNet
DesignWare.com
3
Contents
DesignWare DW_apb_i2c Databook
3.3 I2C Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.3.1 START and STOP Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.3.2 Combined Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.4 I2C Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.4.1 START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.4.2 Addressing Slave Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.4.3 Transmitting and Receiving Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.4.4 START BYTE Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.5 Tx FIFO Management and START, STOP and RESTART Generation . . . . . . . . . . . . . . . . . . . . . . . . .40
3.5.1 Tx FIFO Management When IC_EMPTYFIFO_HOLD_MASTER_EN = 0 . . . . . . . . . . . . . . . . .40
3.5.2 Tx FIFO Management When IC_EMPTYFIFO_HOLD_MASTER_EN = 1 . . . . . . . . . . . . . . . . .41
3.6 Multiple Master Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.8 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.8.1 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.8.2 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.8.3 Disabling DW_apb_i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.9 Spike Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.10 IC_CLK Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.10.1 Minimum High and Low Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.10.2 Minimum IC_CLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.11 SDA Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.12 DMA Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.12.1 Enabling the DMA Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.12.2 Overview of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.12.3 Transmit Watermark Level and Transmit FIFO Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.12.4 Choosing the Transmit Watermark Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.12.5 Selecting DEST_MSIZE and Transmit FIFO Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.12.6 Receive Watermark Level and Receive FIFO Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.12.7 Choosing the Receive Watermark level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.12.8 Selecting SRC_MSIZE and Receive FIFO Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.12.9 Handshaking Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.13 APB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Chapter 4
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.1 Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.2 Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Chapter 5
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.1 DW_apb_i2c Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.2 I/O Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.3 DW_apb_i2c Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Chapter 6
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
6.1 Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
6.2 Operation of Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
6.3 Registers and Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
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6.3.1 IC_CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
6.3.2 IC_TAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
6.3.3 IC_SAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
6.3.4 IC_HS_MADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
6.3.5 IC_DATA_CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
6.3.6 IC_SS_SCL_HCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
6.3.7 IC_SS_SCL_LCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
6.3.8 IC_FS_SCL_HCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
6.3.9 IC_FS_SCL_LCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
6.3.10 IC_HS_SCL_HCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
6.3.11 IC_HS_SCL_LCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
6.3.12 IC_INTR_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
6.3.13 IC_INTR_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.14 IC_RAW_INTR_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
6.3.15 IC_RX_TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
6.3.16 IC_TX_TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
6.3.17 IC_CLR_INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
6.3.18 IC_CLR_RX_UNDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
6.3.19 IC_CLR_RX_OVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
6.3.20 IC_CLR_TX_OVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
6.3.21 IC_CLR_RD_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
6.3.22 IC_CLR_TX_ABRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
6.3.23 IC_CLR_RX_DONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
6.3.24 IC_CLR_ACTIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
6.3.25 IC_CLR_STOP_DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
6.3.26 IC_CLR_START_DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
6.3.27 IC_CLR_GEN_CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
6.3.28 IC_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
6.3.29 IC_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
6.3.30 IC_TXFLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
6.3.31 IC_RXFLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
6.3.32 IC_SDA_HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
6.3.33 IC_TX_ABRT_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
6.3.34 IC_SLV_DATA_NACK_ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
6.3.35 IC_DMA_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
6.3.36 IC_DMA_TDLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
6.3.37 IC_DMA_RDLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
6.3.38 IC_SDA_SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
6.3.39 IC_ACK_GENERAL_CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
6.3.40 IC_ENABLE_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
6.3.41 IC_FS_SPKLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
6.3.42 IC_HS_SPKLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
6.3.43 IC_COMP_PARAM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
6.3.44 IC_COMP_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
6.3.45 IC_COMP_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Chapter 7
Programming the DW_apb_i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
7.1 Software Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
7.2 Software Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
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DesignWare DW_apb_i2c Databook
Chapter 8
Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
8.1 Overview of Vera Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
8.1.1 APB Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
8.1.2 DW_apb_i2c Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
8.1.3 DW_apb_i2c Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
8.1.4 DW_apb_i2c Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
8.1.5 DMA Handshaking Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
8.1.6 DW_apb_i2c Dynamic IC_TAR and IC_10BITADDR_MASTER Update . . . . . . . . . . . . . . . . .149
8.1.7 Generate NACK as a Slave-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
8.1.8 SCL Held Low for Duration Specified in IC_SDA_SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
8.1.9 Generate ACK/NACK for General Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
8.2 Overview of DW_apb_i2c Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Chapter 9
Integration Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9.1 Digital/Analog Domain Functional Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9.2 Reading and Writing from an APB Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9.2.1 Reading From Unused Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
9.2.2 32-bit Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
9.2.3 16-bit Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
9.2.4 8-bit Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
9.3 Write Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
9.4 Read Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
9.5 Accessing Top-level Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Appendix 10
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
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Preface
Preface
This databook provides information that you need to interface the DW_apb_i2c to the Advanced Peripheral
Bus (APB). The DW_apb_i2c conforms to the AMBA Specification, Revision 2.0 from ARM.
The information in this databook includes an overview, pin and parameter descriptions, a memory map,
and functional behavior of the component. An overview of the testbench, a description of the tests that are
run to verify the coreKit, and synthesis information for the component are also provided.
Organization
The chapters of this databook are organized as follows:
❖ Chapter 1, “Product Overview,” provides a system overview, a component block diagram, basic
features, and an overview of the verification environment.
❖ Chapter 2, “Building and Verifying a Component or Subsystem,” introduces you to using the
DW_apb_i2c within the coreAssembler and coreConsultant tools.
❖ Chapter 3, “Functional Description,” describes the functional operation of the DW_apb_i2c.
❖ Chapter 4, “Parameters,” identifies the configurable parameters supported by the DW_apb_i2c.
❖ Chapter 5, “Signals,” provides a list and description of the DW_apb_i2c signals.
❖ Chapter 6, “Registers,” describes the programmable registers of the DW_apb_i2c.
❖ Chapter 7, “Programming the DW_apb_i2c,” provides information needed to program the
configured DW_apb_i2c.
❖ Chapter 8, “Verification,” provides information on verifying the configured DW_apb_i2c.
❖ Chapter 9, “Integration Considerations,” includes information you need to integrate the configured
DW_apb_i2c into your design.
❖ Appendix A, “DW_apb_i2c Application Notes,” contains information about application notes for the
DW_apb_i2c component.
❖ Appendix 10, “Glossary,” provides a glossary of general terms.
Related Documentation
To see a complete listing of documentation within the DesignWare Synthesizable Components for AMBA 2,
refer to the Guide to Documentation for DesignWare Synthesizable Components for AMBA 2 and AMBA 3 AXI.
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Preface
DesignWare DW_apb_i2c Databook
Document Revision History
This table shows the revision history for the databook from release to release. This is being tracked from
version 1.08a onward.
Table 1-1
Databook Revision History
Version Databook Date Description
1.15a
1.14a
1.13a
Apr 2011
Dec 2010
Oct 2010
Added spike suppression material.
Corrected subsection numbering in Registers chapter.
Added information on calculating maximum value for IC_DEFAULT_SDA_HOLD
parameter and IC_SDA_HOLD register; “SDA Hold Time” section, description of
IC_DEFAULT_SDA_HOLD parameter, and IC_SDA_HOLD register updated
1.12a
7 Sep 2010
Corrected DW_ahb_dmac response in “Receive Watermark Level and Receive FIFO
Overflow” section
1.12a
1.11a
Sep 2010
Mar 2010
1.10a
1.10a
Jan 2010
Dec 2009
Corrected names of include files and vcs command used for simulation
Corrected information regarding how DW_apb_i2c communicates with slaves when
operating in master mode; corrected default value for IC_DEFAULT_SDA_SETUP
parameter; added SDA hold time information; added IC_SDA_HOLD register
description; removed references to 300ns hold time in integration considerations;
removed DW_apb_i2c Application Notes appendix.
Removed reference to I2C protocol created by Philips (NXP).
Corrected dependencies for IC_SS_SCL_HIGH_COUNT, IC_SS_SCL_LOW_COUNT,
IC_FS_SCL_HIGH_COUNT, and IC_FS_SCL_LOW_COUNT parameters; corrected
IC_RESTART_EN parameter description; modified description of IC_SDA_SETUP
register; updated databook to new template for consistency with other IIP/VIP/PHY
databooks.
1.10a
Jul 2009
Corrected equations for avoiding underflow when programming a source burst
transaction.
1.10a
1.10a
1.10a
Jun 2009
Corrected name of IC_10BITADDR_SLAVE parameter in “Parameters” chapter.
May 2009
Removed references to QuickStarts, as they are no longer supported.
24 Apr 2009
Enhanced IC_CON description with table for IC_SLAVE_DISABLE and
MASTER_MODE combinations that result in configuration errors.
1.10a
23 Apr 2009
Enhanced “Master Transmit and Master Receive” subsection to clarify reads for multiple
bytes.
1.10a
Oct 2008
IC_RX_FULL_GEN_NACK parameter removed; IC_INTR_MASK is active low;
dependency changed for IC_HS_MASTER_CODE parameter; IC_SLAVE_DISABLE
default changed to 1; values for HS mode corrected in Table 8; debug_* signal default
values corrected; version change for 2008.10a release.
1.09a
Jul 2008
Removed IC_RX_FULL_GEN_NACK configuration parameter and its conditional text.
Changed reference to non-existent table for IC_*S_SCL_*CNT registers to link to
“IC_CLK Frequency Configuration” section. Removed USE_FOUNDATION parameter.
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