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vivado fir IP核的使用.pdf
FIR Compiler v7.2
Table of Contents
IP Facts
Ch. 1: Overview
Feature Summary
Feature Support Matrix
Notable Limitations
Licensing and Ordering Information
Ch. 2: Product Specification
Performance
Maximum Frequencies
Latency
Throughput
Resource Utilization
Port Descriptions
Ch. 3: Designing with the Core
Clocking
Resets
AXI4-Stream Considerations
Basic Handshake
Input and Output DATA Channels
TREADY and TVALID
TDATA Structure
TLAST Options
TUSER Options
CONFIG Channel
Blocking Behavior
Packet Consumption Rate and Synchronization
TREADY
TLAST Options
TDATA
RELOAD Channel
TREADY
TLAST
TDATA
Event Interface
Interface Timing
Core Features
Filter Architectures
Multiply-Accumulate
Systolic Multiply-Accumulate
Transpose Multiply-Accumulate
Filter Structures and Optimizations
Filter Symmetry
Single-rate FIR Filter
Half-band FIR Filter
Hilbert Transform
Interpolated FIR Filter
Polyphase Decimator
Polyphase Interpolator
Half-band Decimator
Half-band Interpolator
Small Non-zero Even Terms in a Half-band Filter Impulse Response
Fixed Fractional Rate Resampling Filters
Filter Coefficient Data
Single-rate FIR
Half-band Filter
Hilbert Transform
Interpolated Filter
Multiple Coefficient Sets
Coefficient Specification Using Non-integer Real Numbers
Interleaved Data Channel Filters
Basic
Advanced
Parallel Data Channel Filters
Coefficient Reload
Reload Order File
Coefficient Quantization
Integer Coefficients
Quantize Only
Maximize Dynamic Range
Best Precision Fractional Length
Output Width and Bit Growth
Output Rounding
Full Precision
Truncation
Non-symmetric Rounding to Positive
Non-symmetric Rounding to Negative
Symmetric Rounding to Highest Magnitude
Symmetric Rounding to Zero
Convergent Rounding
Resource Implications of Rounding
Multiple Column Filter Implementation
Super Sample Rate Filters
Input and Output Sample Rate
Integer Rate Change
Fractional Rate Change
Super Sample Rate
Resource Considerations
Data and Coefficient Bit Width
Output Rounding Selection
Multiple Channel versus Parallel Datapaths
Multichannel implementation
Parallel Datapaths
Multichannel implementation
Parallel Datapaths
Coefficient Reload
Ch. 4: Design Flow Steps
Customizing and Generating the Core
IP Symbol Tab
Freq. Response Tab
Implementation Details Tab
Coefficient Reload Tab
Filter Options Tab
Channel Specification Tab
Implementation Tab
Detailed Implementation Tab
Interface Tab
Summary Tab
User Parameters
Output Generation
System Generator for DSP
Filter Specification
Channel Specification
Implementation
Interface
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Ch. 5: C Model
Unpacking and Model Contents
Installation
Linux
Windows
C Model Interface
Constants
Type Definitions
Dynamic Arrays
Structure
General Functions
FIR Compiler Specific Functions
Structures
Functions
Model Configuration Functions
Model Operation Functions
Compiling
Linking
Linux
Windows
Example
MATLAB Interface
Compiling
Installation
MATLAB Class Interface
Constructor
Get Version
Get Configuration
Reset
Send CONFIG Packet
Send RELOAD Packet
Filter
Example
Dependent Libraries
Ch. 6: Test Bench
Demonstration Test Bench
Using the Demonstration Test Bench
The Demonstration Test Bench in Detail
Customizing the Demonstration Test Bench
Simulation
Appx. A: Migrating and Upgrading
Migrating to the Vivado Design Suite from ISE
Parameter Changes
Updating from FIR Compiler Versions 6.0 through 6.3
Updating from FIR Compiler v5.0
Port Changes
Functionality Changes
Latency Changes
Instructions for Minimum Change Migration
Parameters
Ports
Upgrading within the Vivado Design Suite
Parameter Changes
Port Changes
Simulation
Appx. B: Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
C-Model Reference
Simulation Debug
AXI4-Stream Interface Debug
Appx. C: Additional Resources and Legal Notices
Xilinx Resources
References
Revision History
Please Read: Important Legal Notices
FIR Compiler v7.2
LogiCORE IP Product Guide
Vivado Design Suite
PG149 November 18, 2015
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Licensing and Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: Product Specification
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 3: Designing with the Core
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AXI4-Stream Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input and Output Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Resource Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
System Generator for DSP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Chapter 5: C Model
Unpacking and Model Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
C Model Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MATLAB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Dependent Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
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Chapter 6: Test Bench
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Appendix A: Migrating and Upgrading
Migrating to the Vivado Design Suite from ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Upgrading within the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
AXI4-Stream Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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IP Facts
LogiCORE IP Facts Table
Core Specifics
UltraScale+™ Families
UltraScale™ Architecture
Zynq-7000 All Programmable SoC
7 Series
AXI4-Stream
Performance and Resource Utilization web page
Provided with Core
Encrypted RTL
Not Provided
VHDL
Not Provided
Encrypted VHDL
N/A
Tested Design Flows(2)
Vivado® Design Suite
System Generator for DSP
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Vivado Synthesis
Support
Supported
Device Family(1)
Supported User
Interfaces
Resources
Design Files
Example Design
Test Bench
Constraints File
Simulation
Model
Supported
S/W Driver
Design Entry
Simulation
Synthesis
Provided by Xilinx at the at the Xilinx Support web page
Notes:
1. For a complete listing of supported devices, see the Vivado IP
catalog.
2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
Introduction
The Xilinx® LogiCORE ™ IP FIR Compiler core
provides a common interface to generate
highly parameterizable, area-efficient
high-performance FIR filters.
Features
• AXI4-Stream-compliant interfaces
• High-performance finite impulse response
(FIR), polyphase decimator, polyphase
interpolator, half-band, half-band
decimator and half-band interpolator,
Hilbert transform and interpolated filter
implementations
Support for up to 256 sets of coefficients,
with 2 to 2048 coefficients per set
Input data up to 49-bit precision
Filter coefficients up to 49-bit precision
Support for up to 1024 interleaved data
channels
Support for advanced interleaved data
channel sequences
Support for multiple parallel data channels
with shared control logic
Interpolation and decimation factors of up
to 64 generally and up to 1024 for single
channel filters
Support for sample frequency greater than
clock frequency
•
•
•
•
•
•
•
•
• Online coefficient reload capability
• User-selectable output rounding
•
Efficient multi-column structures for all
filter implementations and optimizations
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Product Specification
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Chapter 1
Overview
A wide range of filter types can be implemented in the Vivado® Integrated Design
Environment (IDE): single-rate, polyphase decimators and interpolators and half-band
decimators and interpolators. Structure in the coefficient set is exploited to produce
area-efficient FPGA implementations. Sufficient arithmetic precision is employed in the
internal datapath to avoid the possibility of overflow.
The conventional single-rate FIR version of the core computes the convolution sum defined
in Equation 1-1, where N is the number of filter coefficients.
y k( )
N 1–
=
0=
n
a n(
)x k n–(
)
k
=
0 1 …,
,
Equation 1-1
Figure 1-1 shows the conventional tapped delay line realization of this inner-product
calculation, and although the illustration is a useful conceptualization of the computation
performed by the core, the actual FPGA realization is quite different.
One or more time-shared multiply-accumulate (MAC) functional units are used to service
the N sum-of-product calculations in the filter. The core automatically determines the
minimum number of MAC engines required to meet user-specified throughput.
X-Ref Target - Figure 1-1
Figure 1-1: Conventional Tapped Delay Line FIR Filter Representation
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Chapter 1: Overview
Feature Summary
Table 1-1 and Table 1-2 show the features and filter configuration support for the FIR
Compiler.
Feature Support Matrix
Table 1-1:
Feature Support Matrix
Feature
Systolic
Multiply-Accumulate
Transpose
Multiply-Accumulate
Number of Coefficients
Coefficient Width(1)
Data Width(1)(2)
Number of Interleaved Channels
Number of Parallel Data Channels(3)
Maximum Rate Change
Single Channel
Multiple Channels
Fractional Rate Support
Coefficient Reload
Coefficient Sets
Output Rounding
Super Sample Rate(5)
2–2048
2–49
2–49
1–1024(4)
1-16
1024
512
Yes
Yes
1–256
Yes
Yes
2–2048
2–49
2–49
1
1-16
1024
N/A
No
Yes
1–256
Yes
No
Notes:
1. Maximum Coefficient Width reduces by one when the Coefficients are signed. Similarly for Maximum Data Width
when the Data values are signed.
2. The allowable range for the Data Width field in the Vivado IDE might reduce further to ensure that the
accumulator width does not exceed the maximum.
3. Maximum Parallel Datapaths reduces to 8 when Coefficient Width or Data Width is greater than 25-bits.
4. Continuous 1 to 256, plus 512 and 1024.
5. Sample frequency greater than clock frequency.
Table 1-2 shows the classes of filters that are supported for the FIR Compiler core.
Table 1-2:
Filter Configuration Support Matrix
Filter Configuration
Supported
Conventional Single-rate FIR
Half-band FIR
Hilbert Transform [Ref 1]
Interpolated FIR [Ref 2] [Ref 3]
Polyphase Decimator
Yes
Yes
Yes
Yes
Yes
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Chapter 1: Overview
Table 1-2:
Filter Configuration Support Matrix (Cont’d)
Filter Configuration
Polyphase Interpolator
Half-band Decimator
Half-band Interpolator
Supported
Yes
Yes
Yes
The supported filter configurations are described in separate sections within this document.
Notable Limitations
In conjunction with Table 1-1 and Table 1-2, it is important to note some further limitations
inherent in the core.
When selecting the Systolic Multiply-Accumulate architecture, the limitations are as
follows:
Fractional Rate filters do not currently exploit coefficient symmetry.
•
• Non Half-band rate change filters utilizing the advanced channel sequence feature do
not exploit coefficient symmetry.
When selecting the Transpose Multiply-Accumulate architecture, the limitations are as
follows:
Symmetry is not exploited.
•
• Multiple interleaved channels are not supported.
Super sample rate filters (sample frequency greater than clock frequency) have the
following limitations:
Symmetry is only exploited for single rate implementations.
Fractional rate filters are not supported.
•
•
• Half-band optimizations are not exploited.
Licensing and Ordering Information
This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado
Design Suite under the terms of the Xilinx End User License. Information about this and
other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For
information about pricing and availability of other Xilinx LogiCORE IP modules and tools,
contact your local Xilinx sales representative.
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Chapter 2
Product Specification
Performance
Maximum Frequencies
For details about frequency, visit Performance and Resource Utilization.
Latency
The core latency is dependent on many of the core parameters. The Implementation Details
Tab on the core GUI displays the core latency value, in clock cycles, given the current
configuration.
Throughput
The core throughput is completely configurable; from full throughput, one clock cycle per
input sample, through to a completely over-sampled implementation. Refer to Hardware
Oversampling Specification on the Channel Specification Screen of the core GUI for details.
Resource Utilization
For details about resource utilization, visit Performance and Resource Utilization.
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