Digital Logic and Microprocessor Design With VHDL.pdf

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ELECTRONiX

Cover

Contents

Preface

Using This Book

Chapter 1 Designing Microprocessors

Chapter 2 Digital Circuits

Chapter 3 Combinational Circuits

Chapter 4 Standard Combinational Components

Chapter 5 Implementation Technologies

Chapter 6 Latches and Flip-Flops

Chapter 7 Sequential Circuits

Chapter 8 Standard Sequential Components

Chapter 9 Datapaths

Chapter 10 Control Units

Chapter 11 Dedicated Microprocessors

Chapter 12 General-Purpose Microprocessors

Appendix A Schematic Entry Tutorial 1

Appendix B VHDL Entry Tutorial 2

Appendix C UP2 Programming Tutorial 3

Appendix D VHDL Summary

About the Author

Digital Logic and Microprocessor Design With VHDL Enoch O. Hwang La Sierra University, Riverside

To my wife and children, Windy, Jonathan and Michelle

Contents Contents .................................................................................................................................................................... Preface ................................................................................................................................................................... 1.3.1 1.3.2 1.3.3 Chapter 1 Designing Microprocessors...................................................................................... 1.1 Overview of a Microprocessor ....................................................................................................................... 1.2 Design Abstraction Levels.............................................................................................................................. 1.3 Examples of a 2-to-1 Multiplexer................................................................................................................... Behavioral Level.................................................................................................................................... Gate Level.............................................................................................................................................. Transistor Level ..................................................................................................................................... 1.4 Introduction to VHDL .................................................................................................................................... 1.5 Synthesis....................................................................................................................................................... 1.6 Going Forward.............................................................................................................................................. 1.7 Summary Checklist....................................................................................................................................... 1.8 Problems ....................................................................................................................................................... 2.5.1 2.5.2 2.5.3 Chapter 2 Digital Circuits..........................................................................................................2 2.1 Binary Numbers.............................................................................................................................................. 3 2.2 Binary Switch ................................................................................................................................................. 2.3 Basic Logic Operators and Logic Expressions ............................................................................................... 2.4 Truth Tables.................................................................................................................................................... 2.5 Boolean Algebra and Boolean Function......................................................................................................... Boolean Algebra .................................................................................................................................... * Duality Principle............................................................................................................................... Boolean Function and the Inverse........................................................................................................ 2.6 Minterms and Maxterms............................................................................................................................... 2.6.1 Minterms.............................................................................................................................................. 2.6.2 * Maxterms .......................................................................................................................................... 2.7 Canonical, Standard, and non-Standard Forms............................................................................................. 2.8 Logic Gates and Circuit Diagrams................................................................................................................ 2.9 Example: Designing a Car Security System ................................................................................................. 2.10 VHDL for Digital Circuits............................................................................................................................ 2.10.1 VHDL code for a 2-input NAND gate................................................................................................. 2.10.2 VHDL code for a 3-input NOR gate.................................................................................................... 2.10.3 VHDL code for a function................................................................................................................... 2.11 Summary Checklist....................................................................................................................................... 2.12 Problems ....................................................................................................................................................... Chapter 3 Combinational Circuits............................................................................................ 3.1 Analysis of Combinational Circuits................................................................................................................ Using a Truth Table............................................................................................................................... Using a Boolean Function...................................................................................................................... 3.2 Synthesis of Combinational Circuits .............................................................................................................. 3.3 * Technology Mapping................................................................................................................................... 3.4 Minimization of Combinational Circuits...................................................................................................... Karnaugh Maps.................................................................................................................................... Don’t-cares .......................................................................................................................................... * Tabulation Method............................................................................................................................ * Timing Hazards and Glitches .................................................................................................................... 3.4.1 3.4.2 3.4.3 3.1.1 3.1.2 3.5 5

3.5.1 Using Glitches ..................................................................................................................................... 3.6 BCD to 7-Segment Decoder ......................................................................................................................... 3.7 VHDL for Combinational Circuits ............................................................................................................... Structural BCD to 7-Segment Decoder................................................................................................ Dataflow BCD to 7-Segment Decoder ................................................................................................ Behavioral BCD to 7-Segment Decoder.............................................................................................. 3.8 Summary Checklist....................................................................................................................................... 3.9 Problems ....................................................................................................................................................... 3.7.1 3.7.2 3.7.3 4.2.1 4.2.2 4.2.3 Chapter 4 Standard Combinational Components................................................................... 4.1 Signal Naming Conventions ........................................................................................................................... 4.2 Adder .............................................................................................................................................................. Full Adder.............................................................................................................................................. Ripple-carry Adder ................................................................................................................................ * Carry-lookahead Adder....................................................................................................................... 4.3 Two’s Complement Binary Numbers ............................................................................................................. 4.4 Subtractor........................................................................................................................................................ 4.5 Adder-Subtractor Combination..................................................................................................................... 4.6 Arithmetic Logic Unit................................................................................................................................... 4.7 Decoder......................................................................................................................................................... 4.8 Encoder......................................................................................................................................................... * Priority Encoder................................................................................................................................ 4.9 Multiplexer ................................................................................................................................................... * Using Multiplexers to Implement a Function ................................................................................... 4.10 Tri-state Buffer ............................................................................................................................................. 4.11 Comparator ................................................................................................................................................... 4.12 Shifter ........................................................................................................................................................... * Barrel Shifter .................................................................................................................................... 4.13 * Multiplier................................................................................................................................................... 4.14 Summary Checklist....................................................................................................................................... 4.15 Problems ....................................................................................................................................................... 4.12.1 4.8.1 4.9.1 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 Chapter 5 * Implementation Technologies ............................................................................. 5.1 Physical Abstraction ....................................................................................................................................... 5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).................................................................. 5.3 CMOS Logic................................................................................................................................................... 5.4 CMOS Circuits ............................................................................................................................................... CMOS Inverter ...................................................................................................................................... CMOS NAND gate................................................................................................................................ CMOS AND gate................................................................................................................................... CMOS NOR and OR Gates ................................................................................................................ 1 Transmission Gate ............................................................................................................................... 2-input Multiplexer CMOS Circuit.....................................................................................................1 CMOS XOR and XNOR Gates............................................................................................................1 5.5 Analysis of CMOS Circuits .......................................................................................................................... 1 5.6 Using ROMs to Implement a Function......................................................................................................... 15 5.7 Using PLAs to Implement a Function .......................................................................................................... 1 5.8 Using PALs to Implement a Function ..........................................................................................................1 5.9 Complex Programmable Logic Device (CPLD)........................................................................................... 5.10 Field Programmable Gate Array (FPGA) ..................................................................................................... 5.11 Summary Checklist....................................................................................................................................... 5.12 Problems ....................................................................................................................................................... 6

6.7.1 Chapter 6 Latches and Flip-Flops ............................................................................................ 6.1 Bistable Element............................................................................................................................................. 6.2 SR Latch ......................................................................................................................................................... 6.3 SR Latch with Enable ..................................................................................................................................... 6.4 D Latch ........................................................................................................................................................... 6.5 D Latch with Enable ....................................................................................................................................... 6.6 Clock............................................................................................................................................................... 6.7 D Flip-Flop ................................................................................................................................................... 1 * Alternative Smaller Circuit............................................................................................................... 1 6.8 D Flip-Flop with Enable ............................................................................................................................... 1 6.9 Asynchronous Inputs .................................................................................................................................... 1 6.10 Description of a Flip-Flop ............................................................................................................................ 6.10.1 Characteristic Table............................................................................................................................. 1 6.10.2 Characteristic Equation........................................................................................................................ 1 6.10.3 State Diagram ...................................................................................................................................... 1 6.10.4 Excitation Table................................................................................................................................... 1 6.11 Timing Issues................................................................................................................................................ 1 6.12 Example: Car Security System – Version 2.................................................................................................. 6.13 VHDL for Latches and Flip-Flops................................................................................................................ 1 6.13.1 Implied Memory Element.................................................................................................................... 1 6.13.2 VHDL Code for a D Latch with Enable .............................................................................................. 6.13.3 VHDL Code for a D Flip-Flop ............................................................................................................ 19 6.13.4 VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear ................................... 6.14 * Flip-Flop Types ......................................................................................................................................... 6.14.1 SR Flip-Flop ........................................................................................................................................ 6.14.2 JK Flip-Flop......................................................................................................................................... 6.14.3 T Flip-Flop........................................................................................................................................... 6.15 Summary Checklist....................................................................................................................................... 6.16 Problems ....................................................................................................................................................... 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 Chapter 7 Sequential Circuits...................................................................................................2 7.1 Finite-State-Machine (FSM) Models.............................................................................................................. 7.2 State Diagrams................................................................................................................................................ 7.3 Analysis of Sequential Circuits....................................................................................................................... Excitation Equation ............................................................................................................................... Next-state Equation ............................................................................................................................... Next-state Table..................................................................................................................................... Output Equation................................................................................................................................... Output Table........................................................................................................................................ State Diagram ......................................................................................................................................0 Example: Analysis of a Moore FSM ................................................................................................... Example: Analysis of a Mealy FSM.................................................................................................... 7.4 Synthesis of Sequential Circuits ................................................................................................................... State Diagram ...................................................................................................................................... Next-state Table................................................................................................................................... Implementation Table.......................................................................................................................... Excitation Equation and Next-state Circuit ......................................................................................... Output Table and Equation.................................................................................................................. 1 FSM Circuit ......................................................................................................................................... Examples: Synthesis of Moore FSMs.................................................................................................. Example: Synthesis of a Mealy FSM................................................................................................... 7.5 Unused State Encodings and the Encoding of States.................................................................................... 7.6 Example: Car Security System – Version 3.................................................................................................. 7.7 VHDL for Sequential Circuits ...................................................................................................................... 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7

7.8 7.8.1 7.8.2 7.8.3 * Optimization for Sequential Circuits ......................................................................................................... State Reduction.................................................................................................................................... 3 State Encoding..................................................................................................................................... Choice of Flip-Flops............................................................................................................................ 7.9 Summary Checklist....................................................................................................................................... 7.10 Problems ....................................................................................................................................................... 8.2.1 8.2.2 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 Chapter 8 Standard Sequential Components ..........................................................................2 8.1 Registers ......................................................................................................................................................... 8.2 Shift Registers................................................................................................................................................. Serial-to-Parallel Shift Register ............................................................................................................. Serial-to-Parallel and Parallel-to-Serial Shift Register .......................................................................... 8.3 Counters.......................................................................................................................................................... Binary Up Counter................................................................................................................................. Binary Up-Down Counter.................................................................................................................... Binary Up-Down Counter with Parallel Load ..................................................................................... BCD Up Counter ................................................................................................................................. BCD Up-Down Counter ...................................................................................................................... 8.4 Register Files ................................................................................................................................................ 8.5 Static Random Access Memory.................................................................................................................... 2 * Larger Memories ....................................................................................................................................... 8.6 8.6.1 More Memory Locations ..................................................................................................................... 2 8.6.2 Wider Bit Width .................................................................................................................................. 2 8.7 Summary Checklist....................................................................................................................................... 2 8.8 Problems ....................................................................................................................................................... 2 9.1.1 9.1.2 9.1.3 9.1.4 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 Chapter 9 Datapaths ..................................................................................................................2 9.1 Designing Dedicated Datapaths...................................................................................................................... Selecting Registers................................................................................................................................. Selecting Functional Units..................................................................................................................... Data Transfer Methods .......................................................................................................................... Generating Status Signals .................................................................................................................... 9.2 Using Dedicated Datapaths........................................................................................................................... 9.3 Examples of Dedicated Datapaths ................................................................................................................ Simple IF-THEN-ELSE....................................................................................................................... Counting 1 to 10 .................................................................................................................................. Summation of n down to 1................................................................................................................... Factorial............................................................................................................................................... Count Zero-One................................................................................................................................... 9.4 General Datapaths......................................................................................................................................... 9.5 Using General Datapaths .............................................................................................................................. 9.6 A More Complex General Datapath ............................................................................................................. 9.7 Timing Issues................................................................................................................................................ 9.8 VHDL for Datapaths..................................................................................................................................... Dedicated Datapath.............................................................................................................................. General Datapath ................................................................................................................................. 9.9 Summary Checklist....................................................................................................................................... 9.10 Problems ....................................................................................................................................................... 9.8.1 9.8.2 Chapter 10 Control Units ............................................................................................................ 10.1 Constructing the Control Unit......................................................................................................................... 10.2 Examples ........................................................................................................................................................ 8

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