Contents
Unified Command-line Interface (UCLI)
Running UCLI
UCLI with VCS
How to Enable UCLI Debugging
Compile-time Options
Runtime Options
Debugging During Initialization of SystemVerilog Static Functions and Tasks
UCLI Commands
Using a UCLI Command Alias File
Default Alias File
Customizing Command Aliases and Settings
Creating Custom Command Aliases
Operating System Commands
Configuring End-of-Simulation Behavior
Using Key and Log Files
Log Files
Key Files
Current Scope and Active Scope
Capturing Output of Commands and Scripts
Command-line Editing in UCLI
Keeping the UCLI Prompt Active After a Runtime Error
UCLI Interface Guidelines
Numbering Conventions
VHDL Numbering Conventions
Verilog Numbering Conventions
Hierarchical Path Names
Multiple Levels in a Path Name
Absolute Path Names
Relative Path Names
bit_select/index
part_select/slice
Naming Fields in Records or Structures
Generate Statements
More Examples on Path Names
Name Case Sensitivity
Extended/Escaped Identifiers
Verilog escape name VHDL Extended Identifier
Wildcard Characters
Tcl Variables
Simulation Time Values
Commands
Simulation Invocation Commands
start
restart
“start”
start_verdi
loaddl
cbug
ucli2Proc
Session Management Commands
save
restore
Restrictions for Save and Restore Commands
Simulation Advancing Commands
step
next
run
finish
Navigation Commands
scope
thread
stack
Signal/Variable/Expression Commands
get
force
xprop
report_violations
power
saif
lp_show
release
sexpr
call
search
virtual bus (vbus)
Viewing Values in Symbolic Format
Simulation Environment Array Commands
senv
Breakpoint Commands
stop
Timing Check Control Command
tcheck
report_timing
Signal Value and Memory Dump Specification Commands
dump
Limitations
Examples
Filtering Data in the VPD Dump File
Dumping Analog Signals in FSDB File in VCS- CustomSim Cosimulation Flow
initreg
memory
Support for VHDL Object to Read and Write Verilog Memory File Format
Design Query Commands
search
find_forces
find_identifier
show
constraints
drivers
loads
Macro Control Routines
do
onbreak
onerror
onfail
resume
pause
abort
status
Coverage Command
coverage
Assertion Command
assertion
Precedence Levels for Controlling Assertions
Helper Routine Commands
help
alias
unalias
listing
config
Multi-level Mixed-signal Simulation
ace
Specman Interface Command
sn
Expression Evaluation for stop/sexpr Commands
Extended the Expression Grammar
Verilog Array and Bit Select Indexing Syntax Support
Using the C, C++, and SystemC Debugger
Getting Started
Using a Specific gdb Version
Starting UCLI With the C-Source Debugger
Detaching the C-Source Debugger
C Debugger Supported Commands
SystemC Datatypes
Changing Values of SystemC and Local C Objects With synopsys::change
Changing SystemC Objects
Changing Local C Variables
Using Line Breakpoints
Set a Breakpoint
Deleting a Line Breakpoint
Stepping Through C Source Code
Stepping within C Sources
Cross-stepping Between HDL and C code
Cross-stepping in and out of Verilog PLI Functions
Cross-Stepping In and Out of VhPI Functions
Cross-Stepping from C into HDL:
Cross-Stepping In and Out of SystemC Processes
Direct gdb Commands
Add Directories to Search for Source Files
Common Design Hierarchy
Post-Processing Debug Flow
Interaction With the Simulator
Prompt Indicates Current Domain
Commands Affecting the C Domain
Combined Error Message
Update of Time, Scope, and Traces
Configuring CBug
Startup Mode
Attach Mode
cbug::config add_sc_source_info auto|always|explicit
STL Types Variables for Improved CBug Flow
Use Model
Usage Example
Limitations
Using a Different gdb Version
Supported Platforms
CBug Stepping Features
Using Step-Out Feature
Automatic Step-Through for SystemC
Enabling and Disabling Step-Through Feature
Recovering from Error Conditions
Specifying Value-Change Breakpoint on SystemC Signals
Capabilities for All Data Types
Capabilities for Single-Bit Objects
Capabilities for Bit-Slices
Points to Note
Limitations
Driver/Load Support for SystemC Designs in Post- Processing Mode
Dumping Source Names of Ports and Signals in VPD
Dumping Plain Members of SystemC in VPD
Supported and Unsupported UCLI and CBug Features
UCLI Save Restore Support for SystemC-on-top and Pure-SystemC Designs
SystemC with UCLI Save and Restore Use Model
SystemC with UCLI Save and Restore Coding Guidelines
Saving and Restoring Files During Save and Restore
Restoring the Saved Files from the Previous Saved Session
Limitations of UCLI Save Restore Support
Interactive Rewind
Interactive Rewind Vs Save and Restore
Use Model
Additional Configuration Options
Creating Checkpoints on Breakpoint Hits
Support for Reverse Debug in UCLI
Enabling Reverse Debug
Keep Future
Virtual Checkpoints
Using Reverse Simulation Control Commands
Limitations
Debugging Transactions
Introduction
Transaction Debug in UCLI
Debugging Virtual Interface Arrays and Queues in UCLI
Example
Limitations
Debugging Mixed-Signal Designs
Support for Top Spice Module
Using UCLI show Commands for SPICE
Using show -domain Command
Using show -type Command
Using show -value Command
Support for the UCLI force or release Command on SPICE Ports
Limitations
Usage Example
Examples
Verilog Example
Compiling the VCS Design and Starting Simulation
Running Simulation on a VCS Design
VHDL Example
Compiling the VHDL Design and Starting Simulation
Simulating the VHDL the Design
SystemVerilog Example
Compiling the SystemVerilog Design and Starting Simulation
Simulating the SystemVerilog Design
Native Testbench OpenVera (OV) Example
Compiling the NTB OpenVera Testbench Design and Starting Simulation
Simulating the NTB OpenVera Testbench Design
SCL and UCLI Equivalent Commands
SCL and UCLI Equivalent Commands
Index