STM32F407用户手册.pdf

发布时间：2022-06-03 发布人：admin 分类：说明书资料大小：5.84M 资料格式：pdf 举报版权申诉

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Table 1. Device summary

1 Introduction

2 Description

Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued)

2.1 Full compatibility throughout the family

2.2 Device overview

2.2.1 ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM

2.2.2 Adaptive real-time memory accelerator (ART Accelerator™)

2.2.3 Memory protection unit

2.2.4 Embedded Flash memory

2.2.5 CRC (cyclic redundancy check) calculation unit

2.2.6 Embedded SRAM

2.2.7 Multi-AHB bus matrix

2.2.8 DMA controller (DMA)

2.2.9 Flexible static memory controller (FSMC)

2.2.10 Nested vectored interrupt controller (NVIC)

2.2.11 External interrupt/event controller (EXTI)

2.2.12 Clocks and startup

2.2.13 Boot modes

2.2.14 Power supply schemes

2.2.15 Power supply supervisor

2.2.16 Voltage regulator

2.2.17 Regulator ON/OFF and internal reset ON/OFF availability

Table 3. Regulator ON/OFF and internal reset ON/OFF availability

2.2.18 Real-time clock (RTC), backup SRAM and backup registers

2.2.19 Low-power modes

2.2.20 VBAT operation

2.2.21 Timers and watchdogs

Table 4. Timer feature comparison

2.2.22 Inter-integrated circuit interface (I²C)

2.2.23 Universal synchronous/asynchronous receiver transmitters (USART)

Table 5. USART feature comparison

2.2.24 Serial peripheral interface (SPI)

2.2.25 Inter-integrated sound (I2S)

2.2.26 Audio PLL (PLLI2S)

2.2.27 Secure digital input/output interface (SDIO)

2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support

2.2.29 Controller area network (bxCAN)

2.2.30 Universal serial bus on-the-go full-speed (OTG_FS)

2.2.31 Universal serial bus on-the-go high-speed (OTG_HS)

2.2.32 Digital camera interface (DCMI)

2.2.33 Random number generator (RNG)

2.2.34 General-purpose input/outputs (GPIOs)

2.2.35 Analog-to-digital converters (ADCs)

2.2.36 Temperature sensor

2.2.37 Digital-to-analog converter (DAC)

2.2.38 Serial wire JTAG debug port (SWJ-DP)

2.2.39 Embedded Trace Macrocell™

3 Pinouts and pin description

Table 6. Legend/abbreviations used in the pinout table

Table 7. STM32F40xxx pin and ball definitions

Table 8. FSMC pin definition

Table 9. Alternate function mapping

4 Memory mapping

Table 10. register boundary addresses

5 Electrical characteristics

5.1 Parameter conditions

5.1.1 Minimum and maximum values

5.1.2 Typical values

5.1.3 Typical curves

5.1.4 Loading capacitor

5.1.5 Pin input voltage

5.1.6 Power supply scheme

5.1.7 Current consumption measurement

5.2 Absolute maximum ratings

Table 11. Voltage characteristics

Table 12. Current characteristics

Table 13. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

Table 14. General operating conditions

Table 15. Limitations depending on the operating power supply range

5.3.2 VCAP_1/VCAP_2 external capacitor

Table 16. VCAP_1/VCAP_2 operating conditions

5.3.3 Operating conditions at power-up / power-down (regulator ON)

Table 17. Operating conditions at power-up / power-down (regulator ON)

5.3.4 Operating conditions at power-up / power-down (regulator OFF)

Table 18. Operating conditions at power-up / power-down (regulator OFF)

5.3.5 Embedded reset and power control block characteristics

Table 19. Embedded reset and power control block characteristics

5.3.6 Supply current characteristics

Table 20. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM

Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled)

Table 22. Typical and maximum current consumption in Sleep mode

Table 23. Typical and maximum current consumptions in Stop mode

Table 24. Typical and maximum current consumptions in Standby mode

Table 25. Typical and maximum current consumptions in VBAT mode

Table 26. Typical current consumption in Run mode, code with data processing running from Flash memory, regulator ON (ART accelerator enabled except prefetch), VDD = 1.8 V

Table 27. Switching output I/O current consumption

Table 28. Peripheral current consumption

5.3.7 Wakeup time from low-power mode

Table 29. Low-power mode wakeup timings

5.3.8 External clock source characteristics

Table 30. High-speed external user clock characteristics

Table 31. Low-speed external user clock characteristics

Table 32. HSE 4-26 MHz oscillator characteristics

Table 33. LSE oscillator characteristics (fLSE = 32.768 kHz)

5.3.9 Internal clock source characteristics

Table 34. HSI oscillator characteristics

Table 35. LSI oscillator characteristics

5.3.10 PLL characteristics

Table 36. Main PLL characteristics

Table 37. PLLI2S (audio PLL) characteristics

5.3.11 PLL spread spectrum clock generation (SSCG) characteristics

Table 38. SSCG parameters constraint

5.3.12 Memory characteristics

Table 39. Flash memory characteristics

Table 40. Flash memory programming

Table 41. Flash memory programming with VPP

Table 42. Flash memory endurance and data retention

5.3.13 EMC characteristics

Table 43. EMS characteristics

Table 44. EMI characteristics

5.3.14 Absolute maximum ratings (electrical sensitivity)

Table 45. ESD absolute maximum ratings

Table 46. Electrical sensitivities

5.3.15 I/O current injection characteristics

Table 47. I/O current injection susceptibility

5.3.16 I/O port characteristics

Table 48. I/O static characteristics

Table 49. Output voltage characteristics

Table 50. I/O AC characteristics

5.3.17 NRST pin characteristics

Table 51. NRST pin characteristics

5.3.18 TIM timer characteristics

Table 52. Characteristics of TIMx connected to the APB1 domain

Table 53. Characteristics of TIMx connected to the APB2 domain

5.3.19 Communications interfaces

Table 54. I2C analog filter characteristics

Table 55. SPI dynamic characteristics

Table 56. I2S dynamic characteristics

Table 57. USB OTG FS startup time

Table 58. USB OTG FS DC electrical characteristics

Table 59. USB OTG FS electrical characteristics

Table 60. USB HS DC electrical characteristics

Table 61. USB HS clock timing parameters

Table 62. ULPI timing

Table 63. Ethernet DC electrical characteristics

Table 64. Dynamic characteristics: Eternity MAC signals for SMI

Table 65. Dynamic characteristics: Ethernet MAC signals for RMII

Table 66. Dynamic characteristics: Ethernet MAC signals for MII

5.3.20 CAN (controller area network) interface

5.3.21 12-bit ADC characteristics

Table 67. ADC characteristics

Table 68. ADC accuracy at fADC = 30 MHz

5.3.22 Temperature sensor characteristics

Table 69. Temperature sensor characteristics

Table 70. Temperature sensor calibration values

5.3.23 VBAT monitoring characteristics

Table 71. VBAT monitoring characteristics

5.3.24 Embedded reference voltage

Table 72. Embedded internal reference voltage

Table 73. Internal reference voltage calibration values

5.3.25 DAC electrical characteristics

Table 74. DAC characteristics

5.3.26 FSMC characteristics

Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

Table 77. Asynchronous multiplexed PSRAM/NOR read timings

Table 78. Asynchronous multiplexed PSRAM/NOR write timings

Table 79. Synchronous multiplexed NOR/PSRAM read timings

Table 80. Synchronous multiplexed PSRAM write timings

Table 81. Synchronous non-multiplexed NOR/PSRAM read timings

Table 82. Synchronous non-multiplexed PSRAM write timings

Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space

Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space

Table 85. Switching characteristics for NAND Flash read cycles

Table 86. Switching characteristics for NAND Flash write cycles

5.3.27 Camera interface (DCMI) timing specifications

Table 87. DCMI characteristics

5.3.28 SD/SDIO MMC card host interface (SDIO) characteristics

Table 88. Dynamic characteristics: SD / MMC characteristics

5.3.29 RTC characteristics

Table 89. RTC characteristics

6 Package information

6.1 WLCSP90 package information

Table 90. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data

Table 91. WLCSP90 recommended PCB design rules

6.2 LQFP64 package information

Table 92. LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package mechanical data

6.3 LQPF100 package information

Table 93. LQPF100 – 100-pin, 14 x 14 mm low-profile quad flat package mechanical data

6.4 LQFP144 package information

Table 94. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data

6.5 UFBGA176+25 package information

Table 95. UFBGA176+25 ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data

Table 96. UFBGA176+2 recommended PCB design rules (0.65 mm pitch BGA)

6.6 LQFP176 package information

Table 97. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data

6.7 Thermal characteristics

Table 98. Package thermal characteristics

7 Part numbering

Table 99. Ordering information scheme

Appendix A Application block diagrams

A.1 USB OTG full speed (FS) interface solutions

A.2 USB OTG high speed (HS) interface solutions

A.3 Ethernet interface solutions

8 Revision history

Table 100. Document revision history (continued)

STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features • Core: ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories • Up to 1 Mbyte of Flash memory • Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled memory) data RAM • Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories • LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 1.8 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low-power operation – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) LQFP176 (24 × 24 mm) WLCSP90 (4.223x3.969 mm) UFBGA176 (10 × 10 mm) • Up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™ • Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 84 MHz – Up to 138 5 V-tolerant I/Os • Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock – 2 × CAN interfaces (2.0B Active) – SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII September 2016 This is information on a product in full production. DocID022152 Rev 8 1/202 www.st.com

• 8- to 14-bit parallel camera interface up to 54 Mbytes/s • True random number generator • CRC calculation unit Table 1. Device summary Part number STM32F405xx, STM32F407xx • 96-bit unique ID • RTC: subsecond accuracy, hardware calendar Reference STM32F405xx STM32F407xx STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE 2/202 DocID022152 Rev 8

STM32F405xx, STM32F407xx Contents Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2 ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM . . 20 2.2.1 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 20 2.2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.3 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 21 2.2.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.6 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.8 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.9 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 23 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.12 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.14 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.15 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 29 2.2.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 29 2.2.18 2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.20 2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.22 Universal synchronous/asynchronous receiver transmitters (USART) . 34 2.2.23 2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.25 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.26 2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 36 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 36 2.2.28 2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DocID022152 Rev 8 3/202

Contents STM32F405xx, STM32F407xx 3 4 5 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 37 2.2.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 38 2.2.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.32 2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.35 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.36 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.37 2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 40 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.39 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 5.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.2 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.3 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.5 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.1 VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.2 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 82 Operating conditions at power-up / power-down (regulator OFF) . . . . . 82 5.3.4 Embedded reset and power control block characteristics . . . . . . . . . . . 83 5.3.5 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.8 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 103 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.10 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 106 4/202 DocID022152 Rev 8

STM32F405xx, STM32F407xx Contents 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.13 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 112 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.16 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.3.18 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3.19 5.3.20 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . 133 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.3.22 5.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3.25 5.3.26 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 161 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 162 5.3.28 5.3.29 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.1 WLCSP90 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.2 6.3 LQPF100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.4 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.5 6.6 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.7 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 186 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 188 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 A.1 A.2 A.3 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 DocID022152 Rev 8 5/202

List of tables List of tables STM32F405xx, STM32F407xx Table 21. Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 14 Table 3. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 4. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 5. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 7. STM32F40xxx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 8. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 9. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 10. register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 81 Table 15. Table 16. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 82 Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 82 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 19. Typical and maximum current consumption in Run mode, code with data processing Table 20. running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 85 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 89 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 90 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 90 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 91 Typical current consumption in Run mode, code with data processing running from Flash memory, regulator ON (ART accelerator enabled except prefetch), VDD = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 27. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 28. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 31. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 33. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 34. Table 35. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 36. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 37. Table 38. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 39. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 40. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 41. Table 42. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 43. Table 44. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 22. Table 23. Table 24. Table 25. Table 26. 6/202 DocID022152 Rev 8

STM32F405xx, STM32F407xx List of tables Table 45. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 46. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 47. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 48. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 49. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 50. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 51. Table 52. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 120 Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 53. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 54. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 55. Table 56. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 57. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 58. USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 59. Table 60. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 61. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 62. Ethernet DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 63. Dynamic characteristics: Eternity MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 64. Table 65. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 132 Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 67. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 68. Table 69. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 70. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 71. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 72. Table 73. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 74. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 143 Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 144 Table 76. Table 77. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 78. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 79. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 80. Table 81. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 151 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 82. Switching characteristics for PC Card/CF read and write cycles Table 83. in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 161 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale Table 84. package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 91. WLCSP90 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 92. LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 DocID022152 Rev 8 7/202

List of tables STM32F405xx, STM32F407xx Table 93. Table 94. Table 95. LQPF100 – 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 UFBGA176+25 ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 UFBGA176+2 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . . 178 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 98. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 99. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 100. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 96. Table 97. 8/202 DocID022152 Rev 8

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